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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
*
*/
/ {
aliases {
mmc0 = &sdhci;
mmc1 = &sdmmc;
mmc2 = &sdio;
};
chosen: chosen {
bootargs = "earlycon=uart8250,mmio32,0x2ad40000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rw rootwait rcupdate.rcu_expedited=1 rcu_nocbs=all";
};
fiq_debugger: fiq-debugger {
compatible = "rockchip,fiq-debugger";
rockchip,serial-id = <0>;
rockchip,wake-irq = <0>;
/* If enable uart uses irq instead of fiq */
rockchip,irq-mode-enable = <1>;
rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&uart0m0_xfer>;
status = "okay";
};
firmware {
optee: optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
drm_logo: drm-logo@0 {
compatible = "rockchip,drm-logo";
reg = <0x0 0x0 0x0 0x0>;
};
drm_cubic_lut: drm-cubic-lut@0 {
compatible = "rockchip,drm-cubic-lut";
reg = <0x0 0x0 0x0 0x0>;
};
ramoops: ramoops@40110000 {
compatible = "ramoops";
/* 0x40110000 to 0x401f0000 is for ramoops */
reg = <0x0 0x40110000 0x0 0xe0000>;
boot-log-size = <0x8000>; /* do not change */
boot-log-count = <0x1>; /* do not change */
console-size = <0x80000>;
pmsg-size = <0x30000>;
ftrace-size = <0x00000>;
record-size = <0x14000>;
};
};
};
&dfi {
status = "okay";
};
&display_subsystem {
memory-region = <&drm_logo>, <&drm_cubic_lut>;
memory-region-names = "drm-logo", "drm-cubic-lut";
/* devfreq = <&dmc>; */
};
&dmc {
status = "okay";
center-supply = <&vdd_ddr_s0>;
mem-supply = <&vdd_logic_s0>;
};
&rng {
status = "okay";
};