225 lines
5.6 KiB
C
225 lines
5.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* AMD ALSA SoC PCM Driver
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*
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* Copyright (C) 2021 Advanced Micro Devices, Inc. All rights reserved.
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*/
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#include "vg_chip_offset_byte.h"
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#include <sound/pcm.h>
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#define ACP5x_PHY_BASE_ADDRESS 0x1240000
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#define ACP_DEVICE_ID 0x15E2
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#define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK 0x00010001
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#define ACP_PGFSM_CNTL_POWER_ON_MASK 0x01
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#define ACP_PGFSM_CNTL_POWER_OFF_MASK 0x00
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#define ACP_PGFSM_STATUS_MASK 0x03
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#define ACP_POWERED_ON 0x00
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#define ACP_POWER_ON_IN_PROGRESS 0x01
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#define ACP_POWERED_OFF 0x02
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#define ACP_POWER_OFF_IN_PROGRESS 0x03
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#define ACP_ERR_INTR_MASK 0x20000000
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#define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF
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#define ACP5x_DEVS 4
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#define ACP5x_REG_START 0x1240000
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#define ACP5x_REG_END 0x1250200
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#define ACP5x_I2STDM_REG_START 0x1242400
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#define ACP5x_I2STDM_REG_END 0x1242410
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#define ACP5x_HS_TDM_REG_START 0x1242814
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#define ACP5x_HS_TDM_REG_END 0x1242824
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#define I2S_MODE 0
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#define ACP5x_I2S_MODE 1
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#define ACP5x_RES 4
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#define I2S_RX_THRESHOLD 27
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#define I2S_TX_THRESHOLD 28
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#define HS_TX_THRESHOLD 24
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#define HS_RX_THRESHOLD 23
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#define I2S_SP_INSTANCE 1
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#define I2S_HS_INSTANCE 2
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#define ACP_SRAM_PTE_OFFSET 0x02050000
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#define ACP_SRAM_SP_PB_PTE_OFFSET 0x0
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#define ACP_SRAM_SP_CP_PTE_OFFSET 0x100
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#define ACP_SRAM_HS_PB_PTE_OFFSET 0x200
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#define ACP_SRAM_HS_CP_PTE_OFFSET 0x300
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#define PAGE_SIZE_4K_ENABLE 0x2
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#define I2S_SP_TX_MEM_WINDOW_START 0x4000000
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#define I2S_SP_RX_MEM_WINDOW_START 0x4020000
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#define I2S_HS_TX_MEM_WINDOW_START 0x4040000
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#define I2S_HS_RX_MEM_WINDOW_START 0x4060000
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#define SP_PB_FIFO_ADDR_OFFSET 0x500
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#define SP_CAPT_FIFO_ADDR_OFFSET 0x700
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#define HS_PB_FIFO_ADDR_OFFSET 0x900
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#define HS_CAPT_FIFO_ADDR_OFFSET 0xB00
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#define PLAYBACK_MIN_NUM_PERIODS 2
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#define PLAYBACK_MAX_NUM_PERIODS 8
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#define PLAYBACK_MAX_PERIOD_SIZE 8192
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#define PLAYBACK_MIN_PERIOD_SIZE 1024
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#define CAPTURE_MIN_NUM_PERIODS 2
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#define CAPTURE_MAX_NUM_PERIODS 8
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#define CAPTURE_MAX_PERIOD_SIZE 8192
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#define CAPTURE_MIN_PERIOD_SIZE 1024
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#define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
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#define MIN_BUFFER MAX_BUFFER
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#define FIFO_SIZE 0x100
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#define DMA_SIZE 0x40
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#define FRM_LEN 0x100
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#define I2S_MASTER_MODE_ENABLE 1
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#define I2S_MASTER_MODE_DISABLE 0
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#define SLOT_WIDTH_8 8
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#define SLOT_WIDTH_16 16
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#define SLOT_WIDTH_24 24
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#define SLOT_WIDTH_32 32
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#define TDM_ENABLE 1
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#define TDM_DISABLE 0
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#define ACP5x_ITER_IRER_SAMP_LEN_MASK 0x38
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struct i2s_dev_data {
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bool tdm_mode;
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bool master_mode;
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int i2s_irq;
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u16 i2s_instance;
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u32 tdm_fmt;
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void __iomem *acp5x_base;
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struct snd_pcm_substream *play_stream;
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struct snd_pcm_substream *capture_stream;
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struct snd_pcm_substream *i2ssp_play_stream;
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struct snd_pcm_substream *i2ssp_capture_stream;
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};
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struct i2s_stream_instance {
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u16 num_pages;
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u16 i2s_instance;
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u16 direction;
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u16 channels;
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u32 xfer_resolution;
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u32 val;
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dma_addr_t dma_addr;
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u64 bytescount;
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void __iomem *acp5x_base;
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u32 lrclk_div;
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u32 bclk_div;
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};
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union acp_dma_count {
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struct {
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u32 low;
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u32 high;
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} bcount;
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u64 bytescount;
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};
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struct acp5x_platform_info {
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u16 play_i2s_instance;
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u16 cap_i2s_instance;
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};
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union acp_i2stdm_mstrclkgen {
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struct {
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u32 i2stdm_master_mode : 1;
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u32 i2stdm_format_mode : 1;
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u32 i2stdm_lrclk_div_val : 9;
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u32 i2stdm_bclk_div_val : 11;
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u32:10;
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} bitfields, bits;
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u32 u32_all;
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};
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/* common header file uses exact offset rather than relative
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* offset which requires subtraction logic from base_addr
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* for accessing ACP5x MMIO space registers
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*/
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static inline u32 acp_readl(void __iomem *base_addr)
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{
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return readl(base_addr - ACP5x_PHY_BASE_ADDRESS);
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}
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static inline void acp_writel(u32 val, void __iomem *base_addr)
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{
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writel(val, base_addr - ACP5x_PHY_BASE_ADDRESS);
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}
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int snd_amd_acp_find_config(struct pci_dev *pci);
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static inline u64 acp_get_byte_count(struct i2s_stream_instance *rtd,
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int direction)
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{
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union acp_dma_count byte_count;
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if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
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switch (rtd->i2s_instance) {
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case I2S_HS_INSTANCE:
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byte_count.bcount.high =
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acp_readl(rtd->acp5x_base +
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ACP_HS_TX_LINEARPOSCNTR_HIGH);
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byte_count.bcount.low =
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acp_readl(rtd->acp5x_base +
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ACP_HS_TX_LINEARPOSCNTR_LOW);
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break;
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case I2S_SP_INSTANCE:
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default:
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byte_count.bcount.high =
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acp_readl(rtd->acp5x_base +
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ACP_I2S_TX_LINEARPOSCNTR_HIGH);
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byte_count.bcount.low =
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acp_readl(rtd->acp5x_base +
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ACP_I2S_TX_LINEARPOSCNTR_LOW);
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}
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} else {
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switch (rtd->i2s_instance) {
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case I2S_HS_INSTANCE:
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byte_count.bcount.high =
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acp_readl(rtd->acp5x_base +
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ACP_HS_RX_LINEARPOSCNTR_HIGH);
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byte_count.bcount.low =
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acp_readl(rtd->acp5x_base +
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ACP_HS_RX_LINEARPOSCNTR_LOW);
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break;
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case I2S_SP_INSTANCE:
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default:
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byte_count.bcount.high =
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acp_readl(rtd->acp5x_base +
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ACP_I2S_RX_LINEARPOSCNTR_HIGH);
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byte_count.bcount.low =
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acp_readl(rtd->acp5x_base +
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ACP_I2S_RX_LINEARPOSCNTR_LOW);
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}
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}
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return byte_count.bytescount;
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}
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static inline void acp5x_set_i2s_clk(struct i2s_dev_data *adata,
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struct i2s_stream_instance *rtd)
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{
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union acp_i2stdm_mstrclkgen mclkgen;
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u32 master_reg;
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switch (rtd->i2s_instance) {
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case I2S_HS_INSTANCE:
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master_reg = ACP_I2STDM2_MSTRCLKGEN;
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break;
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case I2S_SP_INSTANCE:
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default:
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master_reg = ACP_I2STDM0_MSTRCLKGEN;
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break;
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}
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mclkgen.bits.i2stdm_master_mode = 0x1;
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if (adata->tdm_mode)
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mclkgen.bits.i2stdm_format_mode = 0x01;
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else
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mclkgen.bits.i2stdm_format_mode = 0x00;
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mclkgen.bits.i2stdm_bclk_div_val = rtd->bclk_div;
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mclkgen.bits.i2stdm_lrclk_div_val = rtd->lrclk_div;
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acp_writel(mclkgen.u32_all, rtd->acp5x_base + master_reg);
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}
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