74 lines
2.8 KiB
Plaintext
74 lines
2.8 KiB
Plaintext
/*
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* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/clock/rockchip-ddr.h>
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#include <dt-bindings/memory/rk3128-dram.h>
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/ {
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ddr_timing: ddr_timing {
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compatible = "rockchip,ddr-timing";
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ddr3_speed_bin = <DDR3_DEFAULT>;
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pd_idle = <0x40>;
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sr_idle = <0x1>;
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auto_pd_dis_freq = <300>;
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auto_sr_dis_freq = <300>;
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ddr3_dll_dis_freq = <300>;
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lpddr2_dll_dis_freq = <300>;
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phy_dll_dis_freq = <266>;
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ddr3_odt_dis_freq = <333>;
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phy_ddr3_odt_disb_freq = <333>;
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ddr3_drv = <DDR3_DS_40ohm>;
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ddr3_odt = <DDR3_ODT_120ohm>;
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phy_ddr3_clk_drv = <PHY_RON_44ohm>;
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phy_ddr3_cmd_drv = <PHY_RON_44ohm>;
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phy_ddr3_dqs_drv = <PHY_RON_44ohm>;
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phy_ddr3_odt = <PHY_RTT_216ohm>;
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lpddr2_drv = <LP2_DS_34ohm>;
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phy_lpddr2_clk_drv = <PHY_RON_44ohm>;
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phy_lpddr2_cmd_drv = <PHY_RON_44ohm>;
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phy_lpddr2_dqs_drv = <PHY_RON_44ohm>;
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ddr_2t = <0>;
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};
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};
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