199 lines
5.8 KiB
YAML
199 lines
5.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/renesas,pfc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas Pin Function Controller (GPIO and Pin Mux/Config)
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maintainers:
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- Geert Uytterhoeven <geert+renesas@glider.be>
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description:
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The Pin Function Controller (PFC) is a Pin Mux/Config controller.
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On SH/R-Mobile SoCs it also acts as a GPIO controller.
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properties:
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compatible:
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enum:
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- renesas,pfc-emev2 # EMMA Mobile EV2
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- renesas,pfc-r8a73a4 # R-Mobile APE6
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- renesas,pfc-r8a7740 # R-Mobile A1
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- renesas,pfc-r8a7742 # RZ/G1H
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- renesas,pfc-r8a7743 # RZ/G1M
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- renesas,pfc-r8a7744 # RZ/G1N
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- renesas,pfc-r8a7745 # RZ/G1E
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- renesas,pfc-r8a77470 # RZ/G1C
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- renesas,pfc-r8a774a1 # RZ/G2M
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- renesas,pfc-r8a774b1 # RZ/G2N
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- renesas,pfc-r8a774c0 # RZ/G2E
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- renesas,pfc-r8a774e1 # RZ/G2H
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- renesas,pfc-r8a7778 # R-Car M1
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- renesas,pfc-r8a7779 # R-Car H1
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- renesas,pfc-r8a7790 # R-Car H2
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- renesas,pfc-r8a7791 # R-Car M2-W
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- renesas,pfc-r8a7792 # R-Car V2H
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- renesas,pfc-r8a7793 # R-Car M2-N
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- renesas,pfc-r8a7794 # R-Car E2
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- renesas,pfc-r8a7795 # R-Car H3
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- renesas,pfc-r8a7796 # R-Car M3-W
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- renesas,pfc-r8a77961 # R-Car M3-W+
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- renesas,pfc-r8a77965 # R-Car M3-N
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- renesas,pfc-r8a77970 # R-Car V3M
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- renesas,pfc-r8a77980 # R-Car V3H
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- renesas,pfc-r8a77990 # R-Car E3
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- renesas,pfc-r8a77995 # R-Car D3
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- renesas,pfc-r8a779a0 # R-Car V3U
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- renesas,pfc-r8a779f0 # R-Car S4-8
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- renesas,pfc-r8a779g0 # R-Car V4H
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- renesas,pfc-sh73a0 # SH-Mobile AG5
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reg:
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minItems: 1
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maxItems: 10
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gpio-controller: true
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'#gpio-cells':
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const: 2
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gpio-ranges:
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minItems: 1
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maxItems: 16
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interrupts-extended:
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minItems: 32
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maxItems: 64
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description:
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Specify the interrupts associated with external IRQ pins on SoCs where
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the PFC acts as a GPIO controller. It must contain one interrupt per
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external IRQ, sorted by external IRQ number.
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power-domains:
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maxItems: 1
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allOf:
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- $ref: "pinctrl.yaml#"
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required:
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- compatible
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- reg
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if:
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properties:
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compatible:
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enum:
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- renesas,pfc-r8a73a4
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- renesas,pfc-r8a7740
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- renesas,pfc-sh73a0
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then:
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required:
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- interrupts-extended
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- gpio-controller
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- '#gpio-cells'
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- gpio-ranges
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- power-domains
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additionalProperties:
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anyOf:
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- type: object
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allOf:
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- $ref: pincfg-node.yaml#
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- $ref: pinmux-node.yaml#
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description:
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Pin controller client devices use pin configuration subnodes (children
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and grandchildren) for desired pin configuration.
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Client device subnodes use below standard properties.
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properties:
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phandle: true
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function: true
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groups: true
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pins: true
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bias-disable: true
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bias-pull-down: true
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bias-pull-up: true
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drive-strength:
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enum: [ 3, 6, 9, 12, 15, 18, 21, 24 ] # Superset of supported values
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power-source:
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enum: [ 1800, 3300 ]
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gpio-hog: true
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gpios: true
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input: true
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output-high: true
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output-low: true
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additionalProperties: false
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- type: object
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properties:
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phandle: true
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additionalProperties:
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$ref: "#/additionalProperties/anyOf/0"
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examples:
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- |
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pfc: pinctrl@e6050000 {
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compatible = "renesas,pfc-r8a7740";
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reg = <0xe6050000 0x8000>,
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<0xe605800c 0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pfc 0 0 212>;
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interrupts-extended =
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<&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
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<&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
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<&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
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<&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
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<&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
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<&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
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<&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
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<&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
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power-domains = <&pd_c5>;
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lcd0-mux-hog {
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/* DBGMD/LCDC0/FSIA MUX */
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gpio-hog;
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gpios = <176 0>;
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output-high;
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};
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};
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- |
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pinctrl@e6060000 {
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compatible = "renesas,pfc-r8a7795";
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reg = <0xe6060000 0x50c>;
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avb_pins: avb {
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mux {
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groups = "avb_link", "avb_mdio", "avb_mii";
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function = "avb";
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};
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pins_mdio {
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groups = "avb_mdio";
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drive-strength = <24>;
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};
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pins_mii_tx {
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pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC",
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"PIN_AVB_TD0", "PIN_AVB_TD1", "PIN_AVB_TD2",
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"PIN_AVB_TD3";
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drive-strength = <12>;
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};
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};
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keys_pins: keys {
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pins = "GP_5_17", "GP_5_20", "GP_5_22", "GP_2_1";
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bias-pull-up;
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};
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sdhi0_pins: sd0 {
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groups = "sdhi0_data4", "sdhi0_ctrl";
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function = "sdhi0";
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power-source = <3300>;
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};
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};
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