232 lines
7.3 KiB
YAML
232 lines
7.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8183-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Mediatek MT8183 Pin Controller
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maintainers:
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- Sean Wang <sean.wang@kernel.org>
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description: |+
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The MediaTek's MT8183 Pin controller is used to control SoC pins.
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properties:
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compatible:
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const: mediatek,mt8183-pinctrl
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reg:
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minItems: 10
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maxItems: 10
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reg-names:
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items:
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- const: iocfg0
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- const: iocfg1
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- const: iocfg2
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- const: iocfg3
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- const: iocfg4
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- const: iocfg5
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- const: iocfg6
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- const: iocfg7
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- const: iocfg8
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- const: eint
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gpio-controller: true
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"#gpio-cells":
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const: 2
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description: |
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Number of cells in GPIO specifier. Since the generic GPIO
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binding is used, the amount of cells must be specified as 2. See the below
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mentioned gpio binding representation for description of particular cells.
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gpio-ranges:
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minItems: 1
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maxItems: 5
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description: |
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GPIO valid number range.
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interrupt-controller: true
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interrupts:
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maxItems: 1
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"#interrupt-cells":
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const: 2
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allOf:
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- $ref: "pinctrl.yaml#"
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required:
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- compatible
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- reg
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- gpio-controller
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- "#gpio-cells"
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- gpio-ranges
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patternProperties:
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'-[0-9]+$':
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type: object
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additionalProperties: false
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patternProperties:
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'pins':
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type: object
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additionalProperties: false
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description: |
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A pinctrl node should contain at least one subnodes representing the
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pinctrl groups available on the machine. Each subnode will list the
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pins it needs, and how they should be configured, with regard to muxer
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configuration, pullups, drive strength, input enable/disable and input
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schmitt.
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$ref: "/schemas/pinctrl/pincfg-node.yaml"
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properties:
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pinmux:
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description:
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integer array, represents gpio pin number and mux setting.
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Supported pin number and mux varies for different SoCs, and are
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defined as macros in <soc>-pinfunc.h directly.
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bias-disable: true
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bias-pull-up: true
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bias-pull-down: true
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input-enable: true
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input-disable: true
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output-low: true
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output-high: true
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input-schmitt-enable: true
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input-schmitt-disable: true
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drive-strength:
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enum: [2, 4, 6, 8, 10, 12, 14, 16]
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mediatek,drive-strength-adv:
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description: |
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Describe the specific driving setup property.
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For I2C pins, the existing generic driving setup can only support
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2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they
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can support 0.125/0.25/0.5/1mA adjustment. If we enable specific
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driving setup, the existing generic setup will be disabled.
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The specific driving setup is controlled by E1E0EN.
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When E1=0/E0=0, the strength is 0.125mA.
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When E1=0/E0=1, the strength is 0.25mA.
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When E1=1/E0=0, the strength is 0.5mA.
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When E1=1/E0=1, the strength is 1mA.
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EN is used to enable or disable the specific driving setup.
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Valid arguments are described as below:
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0: (E1, E0, EN) = (0, 0, 0)
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1: (E1, E0, EN) = (0, 0, 1)
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2: (E1, E0, EN) = (0, 1, 0)
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3: (E1, E0, EN) = (0, 1, 1)
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4: (E1, E0, EN) = (1, 0, 0)
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5: (E1, E0, EN) = (1, 0, 1)
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6: (E1, E0, EN) = (1, 1, 0)
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7: (E1, E0, EN) = (1, 1, 1)
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So the valid arguments are from 0 to 7.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1, 2, 3, 4, 5, 6, 7]
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mediatek,pull-up-adv:
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description: |
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Pull up setings for 2 pull resistors, R0 and R1. User can
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configure those special pins. Valid arguments are described as below:
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0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
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1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
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2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
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3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1, 2, 3]
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mediatek,pull-down-adv:
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description: |
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Pull down settings for 2 pull resistors, R0 and R1. User can
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configure those special pins. Valid arguments are described as below:
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0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
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1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
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2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
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3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1, 2, 3]
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mediatek,tdsel:
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description: |
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An integer describing the steps for output level shifter duty
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cycle when asserted (high pulse width adjustment). Valid arguments
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are from 0 to 15.
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$ref: /schemas/types.yaml#/definitions/uint32
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mediatek,rdsel:
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description: |
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An integer describing the steps for input level shifter duty cycle
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when asserted (high pulse width adjustment). Valid arguments are
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from 0 to 63.
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$ref: /schemas/types.yaml#/definitions/uint32
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required:
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- pinmux
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/mt8183-pinfunc.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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pio: pinctrl@10005000 {
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compatible = "mediatek,mt8183-pinctrl";
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reg = <0 0x10005000 0 0x1000>,
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<0 0x11f20000 0 0x1000>,
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<0 0x11e80000 0 0x1000>,
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<0 0x11e70000 0 0x1000>,
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<0 0x11e90000 0 0x1000>,
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<0 0x11d30000 0 0x1000>,
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<0 0x11d20000 0 0x1000>,
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<0 0x11c50000 0 0x1000>,
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<0 0x11f30000 0 0x1000>,
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<0 0x1000b000 0 0x1000>;
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reg-names = "iocfg0", "iocfg1", "iocfg2",
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"iocfg3", "iocfg4", "iocfg5",
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"iocfg6", "iocfg7", "iocfg8",
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"eint";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pio 0 0 192>;
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interrupt-controller;
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interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <2>;
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i2c0_pins_a: i2c-0 {
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pins1 {
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pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
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<PINMUX_GPIO49__FUNC_SDA5>;
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mediatek,pull-up-adv = <3>;
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mediatek,drive-strength-adv = <7>;
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};
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};
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i2c1_pins_a: i2c-1 {
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pins {
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pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
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<PINMUX_GPIO51__FUNC_SDA3>;
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mediatek,pull-down-adv = <2>;
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mediatek,drive-strength-adv = <4>;
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};
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};
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};
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};
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