76 lines
2.2 KiB
C
76 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
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*/
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#ifndef __ROCKCHIP_DSMC_LB_SLAVE_H
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#define __ROCKCHIP_DSMC_LB_SLAVE_H
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#define S2H_INT_FOR_DMA_NUM (15)
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/* LBC_SLAVE_CMN register */
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#define CMN_CON(n) (0x4 * (n))
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#define CMN_STATUS (0x80)
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#define RGN_CMN_CON(rgn, com) (0x100 + 0x100 * (rgn) + 0x4 * (com))
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#define DBG_STATUS(n) (0x900 + 0x4 * (n))
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/* LBC_SLAVE_CSR register */
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#define APP_CON(n) (0x4 * (n))
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#define APP_H2S_INT_STA (0x80)
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#define APP_H2S_INT_STA_EN (0x84)
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#define APP_H2S_INT_STA_SIG_EN (0x88)
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#define LBC_CON(n) (0x100 + 0x4 * (n))
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#define LBC_S2H_INT_STA (0x180)
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#define LBC_S2H_INT_STA_EN (0x184)
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#define LBC_S2H_INT_STA_SIG_EN (0x188)
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#define AXI_WR_ADDR_BASE (0x800)
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#define AXI_RD_ADDR_BASE (0x804)
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#define DBG_STA(n) (0x900 + 0x4 * (n))
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/* LBC_SLAVE_CMN_CMN_CON0 */
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#define CA_CYC_16BIT (0)
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#define CA_CYC_32BIT (1)
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#define CA_CYC_SHIFT (0)
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#define CA_CYC_MASK (0x1)
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#define WR_LATENCY_CYC_SHIFT (4)
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#define WR_LATENCY_CYC_MASK (0x7)
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#define RD_LATENCY_CYC_SHIFT (8)
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#define RD_LATENCY_CYC_MASK (0x7)
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#define WR_DATA_CYC_EXTENDED_SHIFT (11)
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#define WR_DATA_CYC_EXTENDED_MASK (0x1)
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/* LBC_SLAVE_CMN_CMN_CON3 */
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#define DATA_WIDTH_SHIFT (0)
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#define DATA_WIDTH_MASK (0x1)
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#define RDYN_GEN_CTRL_SHIFT (4)
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#define RDYN_GEN_CTRL_MASK (0x1)
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/* APP_H2S_INT_STA */
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#define APP_H2S_INT_STA_SHIFT (0)
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#define APP_H2S_INT_STA_MASK (0xFFFF)
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/* APP_H2S_INT_STA_EN */
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#define APP_H2S_INT_STA_EN_SHIFT (0)
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#define APP_H2S_INT_STA_EN_MASK (0xFFFF)
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/* APP_H2S_INT_STA_SIG_EN */
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#define APP_H2S_INT_STA_SIG_EN_SHIFT (0)
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#define APP_H2S_INT_STA_SIG_EN_MASK (0xFFFF)
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/* LBC_S2H_INT_STA */
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#define LBC_S2H_INT_STA_SHIFT (0)
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#define LBC_S2H_INT_STA_MASK (0xFFFF)
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/* LBC_S2H_INT_STA_EN */
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#define LBC_S2H_INT_STA_EN_SHIFT (0)
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#define LBC_S2H_INT_STA_EN_MASK (0xFFFF)
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/* LBC_S2H_INT_STA_SIG_EN */
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#define LBC_S2H_INT_STA_SIG_EN_SHIFT (0)
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#define LBC_S2H_INT_STA_SIG_EN_MASK (0xFFFF)
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#define DSMC_SLAVE_ENABLE(n) ((0x1 << (4 + 16)) | ((n) << 4))
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#define DSMC_SLAVE_RDYN_MODE(n) ((0x1 << (5 + 16)) | ((n) << 5))
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#define AXI_ADDR_4GB_RANGE (1ULL << 32)
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#endif /* __BUS_ROCKCHIP_ROCKCHIP_DSMC_SLAVE_H */
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