535 lines
15 KiB
C
535 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (c) 2024, Rockchip Electronics Co., Ltd.
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*/
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/mailbox_controller.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <soc/rockchip/rockchip-mailbox.h>
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#define MAILBOX_A2B_INTEN 0x00
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#define MAILBOX_A2B_STATUS 0x04
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#define MAILBOX_A2B_CMD(x) (0x08 + (x) * 8)
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#define MAILBOX_A2B_DAT(x) (0x0c + (x) * 8)
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#define MAILBOX_B2A_INTEN 0x28
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#define MAILBOX_B2A_STATUS 0x2C
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#define MAILBOX_B2A_CMD(x) (0x30 + (x) * 8)
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#define MAILBOX_B2A_DAT(x) (0x34 + (x) * 8)
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#define MAILBOX_V2_A2B_INTEN MAILBOX_A2B_INTEN
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#define MAILBOX_V2_A2B_STATUS MAILBOX_A2B_STATUS
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#define MAILBOX_V2_A2B_CMD 0x08
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#define MAILBOX_V2_A2B_DAT 0x0c
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#define MAILBOX_V2_B2A_INTEN 0x10
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#define MAILBOX_V2_B2A_STATUS 0x14
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#define MAILBOX_V2_B2A_CMD 0x18
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#define MAILBOX_V2_B2A_DAT 0x1c
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#define MAILBOX_V2_TRIGGER_SHIFT 8
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#define MAILBOX_V2_TRIGGER_MASK BIT(8)
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#define MAILBOX_V2_INTEN_TX_DONE BIT(0)
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#define MAILBOX_V2_INTEN_RX_DONE BIT(1)
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#define MAILBOX_V2_INTEN_RX_DONE_SHIFT 1
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#define MAILBOX_V2_STATUS_TX_DONE BIT(0)
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#define MAILBOX_V2_STATUS_RX_DONE BIT(1)
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#define MAILBOX_V2_STATUS_MASK GENMASK(1, 0)
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#define MAILBOX_POLLING_MS 5 /* default polling interval 5ms */
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#define BIT_WRITEABLE_SHIFT 16
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struct rockchip_mbox_reg {
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u32 tx_int;
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u32 tx_sts;
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u32 tx_cmd;
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u32 tx_dat;
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u32 rx_int;
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u32 rx_sts;
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u32 rx_cmd;
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u32 rx_dat;
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};
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struct rockchip_mbox_data {
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int num_chans;
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struct rockchip_mbox_reg reg_a2b;
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struct rockchip_mbox_reg reg_b2a;
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const struct mbox_chan_ops *ops;
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irqreturn_t (*irq_func)(int irq, void *dev_id);
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};
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struct rockchip_mbox_chan {
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int idx;
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int irq;
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};
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struct rockchip_mbox {
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struct mbox_controller mbox;
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struct clk *pclk;
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void __iomem *mbox_base;
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spinlock_t cfg_lock; /* Serialise access to the register */
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unsigned char trigger_method; /* 0 = write cmd, 1 = write cmd first, then write data */
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struct rockchip_mbox_msg *msg;
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const struct rockchip_mbox_reg *reg;
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struct rockchip_mbox_chan *chans;
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};
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static int rockchip_mbox_send_data(struct mbox_chan *chan, void *data)
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{
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struct rockchip_mbox *mb = dev_get_drvdata(chan->mbox->dev);
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struct rockchip_mbox_msg *msg = data;
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struct rockchip_mbox_chan *chans = chan->con_priv;
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u32 status;
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if (!msg)
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return -EINVAL;
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status = readl_relaxed(mb->mbox_base + MAILBOX_A2B_STATUS);
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if (status & (1U << chans->idx)) {
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dev_err(mb->mbox.dev, "The mailbox channel is busy\n");
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return -EBUSY;
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}
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dev_dbg(mb->mbox.dev, "Chan[%d]: A2B message, cmd 0x%08x, data 0x%08x\n",
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chans->idx, msg->cmd, msg->data);
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writel_relaxed(msg->cmd, mb->mbox_base + MAILBOX_A2B_CMD(chans->idx));
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writel_relaxed(msg->data, mb->mbox_base +
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MAILBOX_A2B_DAT(chans->idx));
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return 0;
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}
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static int rockchip_mbox_startup(struct mbox_chan *chan)
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{
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struct rockchip_mbox *mb = dev_get_drvdata(chan->mbox->dev);
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struct rockchip_mbox_chan *chans = chan->con_priv;
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u32 val = 0U;
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/* Enable the corresponding B2A interrupt */
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spin_lock(&mb->cfg_lock);
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val = readl_relaxed(mb->mbox_base + MAILBOX_B2A_INTEN) |
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(1U << chans->idx);
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writel_relaxed(val, mb->mbox_base + MAILBOX_B2A_INTEN);
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spin_unlock(&mb->cfg_lock);
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return 0;
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}
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static void rockchip_mbox_shutdown(struct mbox_chan *chan)
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{
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struct rockchip_mbox *mb = dev_get_drvdata(chan->mbox->dev);
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struct rockchip_mbox_chan *chans = chan->con_priv;
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u32 val = 0U;
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/* Disable the corresponding B2A interrupt */
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spin_lock(&mb->cfg_lock);
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val = readl_relaxed(mb->mbox_base + MAILBOX_B2A_INTEN) &
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~(1U << chans->idx);
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writel_relaxed(val, mb->mbox_base + MAILBOX_B2A_INTEN);
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spin_unlock(&mb->cfg_lock);
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}
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static bool rockchip_mbox_last_tx_done(struct mbox_chan *chan)
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{
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struct rockchip_mbox *mb = dev_get_drvdata(chan->mbox->dev);
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struct rockchip_mbox_chan *chans = chan->con_priv;
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u32 status;
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status = readl_relaxed(mb->mbox_base + MAILBOX_A2B_STATUS);
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return !(status & (1U << chans->idx));
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}
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static irqreturn_t rockchip_mbox_irq(int irq, void *dev_id)
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{
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int idx;
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struct rockchip_mbox_msg *msg;
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struct rockchip_mbox *mb = (struct rockchip_mbox *)dev_id;
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u32 status = readl_relaxed(mb->mbox_base + MAILBOX_B2A_STATUS);
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for (idx = 0; idx < mb->mbox.num_chans; idx++) {
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if ((status & (1U << idx)) && irq == mb->chans[idx].irq) {
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/* Get cmd/data from the channel of B2A */
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msg = &mb->msg[idx];
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msg->cmd = readl_relaxed(mb->mbox_base +
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MAILBOX_B2A_CMD(idx));
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msg->data = readl_relaxed(mb->mbox_base +
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MAILBOX_B2A_DAT(idx));
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dev_dbg(mb->mbox.dev, "Chan[%d]: B2A message, cmd 0x%08x, data 0x%08x\n",
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idx, msg->cmd, msg->data);
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if (mb->mbox.chans[idx].cl)
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mbox_chan_received_data(&mb->mbox.chans[idx], msg);
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/* Clear mbox interrupt */
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writel_relaxed(1U << idx,
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mb->mbox_base + MAILBOX_B2A_STATUS);
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}
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}
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return IRQ_HANDLED;
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}
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static int rockchip_mbox_v2_send_data(struct mbox_chan *chan, void *data)
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{
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struct rockchip_mbox *mb = dev_get_drvdata(chan->mbox->dev);
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struct rockchip_mbox_msg *msg = data;
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u32 status;
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if (!msg)
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return -EINVAL;
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status = readl_relaxed(mb->mbox_base + mb->reg->tx_sts);
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if (status & MAILBOX_V2_STATUS_TX_DONE) {
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dev_err(mb->mbox.dev, "The mailbox is busy\n");
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return -EBUSY;
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}
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dev_dbg(mb->mbox.dev, "TX: cmd 0x%08x, data 0x%08x\n", msg->cmd, msg->data);
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if (mb->trigger_method) {
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writel_relaxed(msg->cmd, mb->mbox_base + mb->reg->tx_cmd);
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writel_relaxed(msg->data, mb->mbox_base + mb->reg->tx_dat);
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} else {
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writel_relaxed(msg->cmd, mb->mbox_base + mb->reg->tx_cmd);
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}
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return 0;
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}
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static int rockchip_mbox_v2_startup(struct mbox_chan *chan)
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{
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struct rockchip_mbox *mb = dev_get_drvdata(chan->mbox->dev);
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/* Set the TX interrupt trigger method */
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writel_relaxed((1U << (BIT_WRITEABLE_SHIFT + MAILBOX_V2_TRIGGER_SHIFT) |
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mb->trigger_method << MAILBOX_V2_TRIGGER_SHIFT),
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mb->mbox_base + mb->reg->tx_int);
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/* Enable the tx_done interrupt */
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writel_relaxed((1U << BIT_WRITEABLE_SHIFT | MAILBOX_V2_INTEN_TX_DONE),
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mb->mbox_base + mb->reg->rx_int);
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/* Enable the rx_done interrupt */
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if (mb->mbox.txdone_irq)
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writel_relaxed((1U << (BIT_WRITEABLE_SHIFT + MAILBOX_V2_INTEN_RX_DONE_SHIFT) |
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MAILBOX_V2_INTEN_RX_DONE),
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mb->mbox_base + mb->reg->rx_int);
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return 0;
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}
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static bool rockchip_mbox_v2_last_tx_done(struct mbox_chan *chan)
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{
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struct rockchip_mbox *mb = dev_get_drvdata(chan->mbox->dev);
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u32 status;
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status = readl_relaxed(mb->mbox_base + mb->reg->tx_sts);
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return !(status & MAILBOX_V2_STATUS_TX_DONE);
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}
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static void rockchip_mbox_v2_shutdown(struct mbox_chan *chan)
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{
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struct rockchip_mbox *mb = dev_get_drvdata(chan->mbox->dev);
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/* Disable the tx_done interrupt */
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writel_relaxed(1U << BIT_WRITEABLE_SHIFT, mb->mbox_base + mb->reg->rx_int);
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/* Disable the rx_done interrupt */
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if (mb->mbox.txdone_irq)
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writel_relaxed(1U << (BIT_WRITEABLE_SHIFT + MAILBOX_V2_INTEN_RX_DONE_SHIFT),
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mb->mbox_base + mb->reg->rx_int);
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}
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static irqreturn_t rockchip_mbox_v2_irq(int irq, void *dev_id)
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{
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struct rockchip_mbox *mb = (struct rockchip_mbox *)dev_id;
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struct rockchip_mbox_msg *msg = mb->msg;
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u32 status;
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status = readl_relaxed(mb->mbox_base + mb->reg->rx_sts);
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if (!(status & MAILBOX_V2_STATUS_MASK))
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return IRQ_NONE;
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if (status & MAILBOX_V2_STATUS_TX_DONE) {
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/* Get cmd/data from the channel */
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msg->cmd = readl_relaxed(mb->mbox_base + mb->reg->rx_cmd);
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msg->data = readl_relaxed(mb->mbox_base + mb->reg->rx_dat);
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dev_dbg(mb->mbox.dev, "RX: cmd 0x%08x, data 0x%08x\n",
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msg->cmd, msg->data);
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/* Clear the tx_done interrupt */
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writel_relaxed(MAILBOX_V2_STATUS_TX_DONE,
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mb->mbox_base + mb->reg->rx_sts);
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if (mb->mbox.chans[0].cl)
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mbox_chan_received_data(&mb->mbox.chans[0], msg);
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}
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if (status & MAILBOX_V2_STATUS_RX_DONE) {
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if (mb->mbox.txdone_irq)
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mbox_chan_txdone(&mb->mbox.chans[0], 0);
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/* Clear the rx_done interrupt */
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writel_relaxed(MAILBOX_V2_STATUS_RX_DONE,
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mb->mbox_base + mb->reg->rx_sts);
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}
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return IRQ_HANDLED;
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}
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static const struct mbox_chan_ops rockchip_mbox_chan_ops = {
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.send_data = rockchip_mbox_send_data,
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.startup = rockchip_mbox_startup,
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.shutdown = rockchip_mbox_shutdown,
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.last_tx_done = rockchip_mbox_last_tx_done,
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};
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static const struct mbox_chan_ops rockchip_mbox_v2_chan_ops = {
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.send_data = rockchip_mbox_v2_send_data,
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.startup = rockchip_mbox_v2_startup,
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.shutdown = rockchip_mbox_v2_shutdown,
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.last_tx_done = rockchip_mbox_v2_last_tx_done,
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};
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int rockchip_mbox_read_msg(struct mbox_chan *chan,
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struct rockchip_mbox_msg *msg)
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{
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struct rockchip_mbox *mb;
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struct rockchip_mbox_chan *chans;
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if (!chan || !msg)
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return -EINVAL;
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mb = dev_get_drvdata(chan->mbox->dev);
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chans = chan->con_priv;
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msg->cmd = mb->msg[chans->idx].cmd;
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msg->data = mb->msg[chans->idx].data;
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return 0;
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}
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EXPORT_SYMBOL_GPL(rockchip_mbox_read_msg);
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static const struct rockchip_mbox_data rk3368_drv_data = {
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.num_chans = 4,
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.ops = &rockchip_mbox_chan_ops,
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.irq_func = rockchip_mbox_irq,
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};
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static const struct rockchip_mbox_data rk3576_drv_data = {
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.num_chans = 1,
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.reg_a2b = { MAILBOX_V2_A2B_INTEN, MAILBOX_V2_A2B_STATUS,
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MAILBOX_V2_A2B_CMD, MAILBOX_V2_A2B_DAT,
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MAILBOX_V2_B2A_INTEN, MAILBOX_V2_B2A_STATUS,
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MAILBOX_V2_B2A_CMD, MAILBOX_V2_B2A_DAT },
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.reg_b2a = { MAILBOX_V2_B2A_INTEN, MAILBOX_V2_B2A_STATUS,
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MAILBOX_V2_B2A_CMD, MAILBOX_V2_B2A_DAT,
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MAILBOX_V2_A2B_INTEN, MAILBOX_V2_A2B_STATUS,
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MAILBOX_V2_A2B_CMD, MAILBOX_V2_A2B_DAT },
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.ops = &rockchip_mbox_v2_chan_ops,
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.irq_func = rockchip_mbox_v2_irq,
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};
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static const struct of_device_id rockchip_mbox_of_match[] = {
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{ .compatible = "rockchip,rk3368-mailbox", .data = &rk3368_drv_data},
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{ .compatible = "rockchip,rk3576-mailbox", .data = &rk3576_drv_data},
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{ },
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};
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MODULE_DEVICE_TABLE(of, rockchip_mbox_of_match);
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static int rockchip_mbox_probe(struct platform_device *pdev)
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{
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struct rockchip_mbox *mb;
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const struct of_device_id *match;
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const struct rockchip_mbox_data *drv_data;
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struct resource *res;
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int ret, irq, i;
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u32 txpoll_period;
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if (!pdev->dev.of_node)
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return -ENODEV;
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match = of_match_node(rockchip_mbox_of_match, pdev->dev.of_node);
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drv_data = (const struct rockchip_mbox_data *)match->data;
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mb = devm_kzalloc(&pdev->dev, sizeof(*mb), GFP_KERNEL);
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if (!mb)
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return -ENOMEM;
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mb->msg = devm_kcalloc(&pdev->dev, drv_data->num_chans,
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sizeof(*mb->msg), GFP_KERNEL);
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if (!mb->msg)
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return -ENOMEM;
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mb->chans = devm_kcalloc(&pdev->dev, drv_data->num_chans,
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sizeof(*mb->chans), GFP_KERNEL);
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if (!mb->chans)
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return -ENOMEM;
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mb->mbox.chans = devm_kcalloc(&pdev->dev, drv_data->num_chans,
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sizeof(*mb->mbox.chans), GFP_KERNEL);
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if (!mb->mbox.chans)
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return -ENOMEM;
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platform_set_drvdata(pdev, mb);
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mb->mbox.dev = &pdev->dev;
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mb->mbox.num_chans = drv_data->num_chans;
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mb->mbox.ops = drv_data->ops;
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spin_lock_init(&mb->cfg_lock);
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if (device_property_present(&pdev->dev, "rockchip,tx-direction-b2a"))
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mb->reg = &drv_data->reg_b2a;
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else
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mb->reg = &drv_data->reg_a2b;
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/*
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* rockchip,txdone-ack: the mailbox client uses its own ACK to check
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* TX_DONE, and call mbox_client_txdone() API to schedule tx_tick.
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* rockchip,txdone-irq: the feature only support from RK3506, the ISR
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* function call mbox_chan_txdone() API to schedule tx_tick.
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* txdone_poll is default for all the platform, it cooperates with
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* "rockchip,txpoll-period-ms" or "rockchip,txpoll-period-us"
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* periodically call last_tx_done() to check TX_DONE by the hrtimer
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* in mailbox framework.
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*/
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if (device_property_present(&pdev->dev, "rockchip,txdone-ack")) {
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mb->mbox.txdone_irq = false;
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mb->mbox.txdone_poll = false;
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} else if (device_property_present(&pdev->dev, "rockchip,txdone-irq")) {
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mb->mbox.txdone_irq = true;
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} else {
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mb->mbox.txdone_poll = true;
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if (IS_REACHABLE(CONFIG_MAILBOX_POLL_PERIOD_US)) {
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ret = device_property_read_u32(&pdev->dev,
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"rockchip,txpoll-period-us",
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&txpoll_period);
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if (!ret) {
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mb->mbox.txpoll_period = txpoll_period;
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} else {
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ret = device_property_read_u32(&pdev->dev,
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"rockchip,txpoll-period-ms",
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&txpoll_period);
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mb->mbox.txpoll_period = !ret ? txpoll_period : MAILBOX_POLLING_MS;
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mb->mbox.txpoll_period *= 1000U; /* Convert to us */
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}
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} else {
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ret = device_property_read_u32(&pdev->dev,
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"rockchip,txpoll-period-ms",
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&txpoll_period);
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mb->mbox.txpoll_period = !ret ? txpoll_period : MAILBOX_POLLING_MS;
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}
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}
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if (device_property_present(&pdev->dev, "rockchip,enable-cmd-trigger"))
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mb->trigger_method = 0;
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else
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mb->trigger_method = 1;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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return -ENODEV;
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mb->mbox_base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(mb->mbox_base))
|
|
return PTR_ERR(mb->mbox_base);
|
|
|
|
mb->pclk = devm_clk_get(&pdev->dev, "pclk_mailbox");
|
|
if (IS_ERR(mb->pclk)) {
|
|
ret = PTR_ERR(mb->pclk);
|
|
dev_err(&pdev->dev, "failed to get pclk_mailbox clock: %d\n",
|
|
ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = clk_prepare_enable(mb->pclk);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "failed to enable pclk: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
for (i = 0; i < mb->mbox.num_chans; i++) {
|
|
irq = platform_get_irq(pdev, i);
|
|
if (irq < 0) {
|
|
/* For shared irq case, only could be got one time */
|
|
if (i > 0 && irq == -ENXIO) {
|
|
mb->chans[i].irq = mb->chans[0].irq;
|
|
} else {
|
|
ret = irq;
|
|
goto disable_clk;
|
|
}
|
|
} else {
|
|
mb->chans[i].irq = irq;
|
|
}
|
|
|
|
mb->chans[i].idx = i;
|
|
mb->mbox.chans[i].con_priv = &mb->chans[i];
|
|
}
|
|
|
|
ret = devm_mbox_controller_register(&pdev->dev, &mb->mbox);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "Failed to register mailbox: %d\n", ret);
|
|
goto disable_clk;
|
|
}
|
|
|
|
for (i = 0; i < mb->mbox.num_chans; i++) {
|
|
/* For shared irq case, only request irq thread one time */
|
|
if (i > 0 && mb->chans[i].irq == mb->chans[0].irq)
|
|
break;
|
|
|
|
ret = devm_request_threaded_irq(&pdev->dev, mb->chans[i].irq,
|
|
NULL,
|
|
drv_data->irq_func,
|
|
IRQF_ONESHOT,
|
|
dev_name(&pdev->dev),
|
|
mb);
|
|
if (ret < 0)
|
|
goto disable_clk;
|
|
|
|
if (device_property_present(&pdev->dev, "wakeup-source"))
|
|
enable_irq_wake(mb->chans[i].irq);
|
|
}
|
|
|
|
return 0;
|
|
|
|
disable_clk:
|
|
clk_disable_unprepare(mb->pclk);
|
|
return ret;
|
|
}
|
|
|
|
static struct platform_driver rockchip_mbox_driver = {
|
|
.probe = rockchip_mbox_probe,
|
|
.driver = {
|
|
.name = "rockchip-mailbox",
|
|
.of_match_table = of_match_ptr(rockchip_mbox_of_match),
|
|
},
|
|
};
|
|
|
|
#if defined(CONFIG_ROCKCHIP_THUNDER_BOOT)
|
|
static int __init rockchip_mbox_driver_init(void)
|
|
{
|
|
return platform_driver_register(&rockchip_mbox_driver);
|
|
}
|
|
core_initcall(rockchip_mbox_driver_init);
|
|
#else
|
|
module_platform_driver(rockchip_mbox_driver);
|
|
#endif
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DESCRIPTION("Rockchip mailbox: communicate between CPU cores and MCU");
|
|
MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
|
|
MODULE_AUTHOR("Caesar Wang <wxt@rock-chips.com>");
|