982 lines
25 KiB
C
982 lines
25 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
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* Author: Lin Huang <hl@rock-chips.com>
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*/
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#include <linux/clk.h>
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#include <linux/devfreq-event.h>
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <linux/list.h>
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#include <linux/of.h>
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#include <soc/rockchip/rk3399_grf.h>
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#define PX30_PMUGRF_OS_REG2 0x208
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#define PX30_PMUGRF_OS_REG3 0x20c
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#define RK3588_PMUGRF_OS_REG(n) (0x200 + (n) * 4)
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#define RK3128_GRF_SOC_CON0 0x140
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#define RK3128_GRF_OS_REG1 0x1cc
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#define RK3128_GRF_DFI_WRNUM 0x220
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#define RK3128_GRF_DFI_RDNUM 0x224
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#define RK3128_GRF_DFI_TIMERVAL 0x22c
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#define RK3128_DDR_MONITOR_EN ((1 << (16 + 6)) + (1 << 6))
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#define RK3128_DDR_MONITOR_DISB ((1 << (16 + 6)) + (0 << 6))
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#define RK3288_PMU_SYS_REG2 0x9c
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#define RK3288_GRF_SOC_CON4 0x254
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#define RK3288_GRF_SOC_STATUS(n) (0x280 + (n) * 4)
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#define RK3288_DFI_EN (0x30003 << 14)
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#define RK3288_DFI_DIS (0x30000 << 14)
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#define RK3288_LPDDR_SEL (0x10001 << 13)
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#define RK3288_DDR3_SEL (0x10000 << 13)
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#define RK3328_GRF_OS_REG2 0x5d0
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#define RK3368_GRF_DDRC0_CON0 0x600
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#define RK3368_GRF_SOC_STATUS5 0x494
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#define RK3368_GRF_SOC_STATUS6 0x498
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#define RK3368_GRF_SOC_STATUS8 0x4a0
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#define RK3368_GRF_SOC_STATUS9 0x4a4
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#define RK3368_GRF_SOC_STATUS10 0x4a8
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#define RK3368_DFI_EN (0x30003 << 5)
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#define RK3368_DFI_DIS (0x30000 << 5)
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#define RK3528_PMUGRF_OFFSET 0x70000
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#define RK3528_PMUGRF_OS_REG18 0x248
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#define RK3528_PMUGRF_OS_REG19 0x24c
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#define MAX_DMC_NUM_CH 4
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#define READ_DRAMTYPE_INFO(n) (((n) >> 13) & 0x7)
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#define READ_CH_INFO(n) (((n) >> 28) & 0x3)
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#define READ_DRAMTYPE_INFO_V3(n, m) ((((n) >> 13) & 0x7) | ((((m) >> 12) & 0x3) << 3))
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#define READ_SYSREG_VERSION(m) (((m) >> 28) & 0xf)
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#define READ_LP5_BANK_MODE(m) (((m) >> 1) & 0x3)
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#define READ_LP5_CKR(m) (((m) >> 0) & 0x1)
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/* DDRMON_CTRL */
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#define DDRMON_CTRL 0x04
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#define CLR_DDRMON_CTRL (0xffff0000 << 0)
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#define DDR2_3_EN (0x10001 << 15)
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#define LPDDR5_BANK_MODE(m) ((0x30000 | ((m) & 0x3)) << 7)
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#define LPDDR5_EN (0x10001 << 6)
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#define DDR4_EN (0x10001 << 5)
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#define LPDDR4_EN (0x10001 << 4)
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#define HARDWARE_EN (0x10001 << 3)
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#define LPDDR2_3_EN (0x10001 << 2)
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#define SOFTWARE_EN (0x10001 << 1)
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#define SOFTWARE_DIS (0x10000 << 1)
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#define TIME_CNT_EN (0x10001 << 0)
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/* DDRMON_CTRL1 */
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#define LPDDR5_BANK_MODE_CTRL1(m) ((0x30000 | ((m) & 0x3)) << 1)
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#define LPDDR5_EN_CTRL1 (0x10001 << 0)
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#define DDRMON_CH0_COUNT_NUM 0x28
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#define DDRMON_CH0_DFI_ACCESS_NUM 0x2c
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#define DDRMON_CH1_COUNT_NUM 0x3c
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#define DDRMON_CH1_DFI_ACCESS_NUM 0x40
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/* pmu grf */
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#define PMUGRF_OS_REG2 0x308
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enum {
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DDR4 = 0,
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DDR2 = 2,
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DDR3 = 3,
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LPDDR2 = 5,
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LPDDR3 = 6,
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LPDDR4 = 7,
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LPDDR4X = 8,
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LPDDR5 = 9,
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DDR5 = 10,
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UNUSED = 0xFF
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};
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struct dmc_usage {
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u64 access;
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u64 total;
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};
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/*
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* The dfi controller can monitor DDR load. It has an upper and lower threshold
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* for the operating points. Whenever the usage leaves these bounds an event is
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* generated to indicate the DDR frequency should be changed.
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*/
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struct rockchip_dfi {
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struct devfreq_event_dev *edev;
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struct devfreq_event_desc *desc;
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struct dmc_usage ch_usage[MAX_DMC_NUM_CH];
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struct device *dev;
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void __iomem *regs;
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struct regmap *regmap_pmu;
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struct regmap *regmap_grf;
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struct regmap *regmap_pmugrf;
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struct clk *clk[MAX_DMC_NUM_CH];
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u32 dram_type;
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u32 mon_version;
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u32 mon_idx;
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u32 mon_ctrl0;
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u32 mon_ctrl1;
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u32 mon_access_num;
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u32 mon_count_num;
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u32 lp5_ctrl_val;
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u32 count_rate;
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u32 dram_dynamic_info_reg;
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/* 0: BG mode, 1: 16 Bank mode, 2: 8 bank mode */
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u32 lp5_bank_mode;
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/* 0: clk:dqs = 1:2, 1: 1:4 */
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u32 lp5_ckr;
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/*
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* available mask, 1: available, 0: not available
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* each bit represent a channel
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*/
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u32 ch_msk;
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};
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static void rk3128_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
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{
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struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
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regmap_write(info->regmap_grf,
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RK3128_GRF_SOC_CON0,
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RK3128_DDR_MONITOR_EN);
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}
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static void rk3128_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
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{
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struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
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regmap_write(info->regmap_grf,
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RK3128_GRF_SOC_CON0,
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RK3128_DDR_MONITOR_DISB);
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}
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static int rk3128_dfi_disable(struct devfreq_event_dev *edev)
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{
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rk3128_dfi_stop_hardware_counter(edev);
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return 0;
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}
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static int rk3128_dfi_enable(struct devfreq_event_dev *edev)
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{
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rk3128_dfi_start_hardware_counter(edev);
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return 0;
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}
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static int rk3128_dfi_set_event(struct devfreq_event_dev *edev)
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{
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return 0;
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}
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static int rk3128_dfi_get_event(struct devfreq_event_dev *edev,
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struct devfreq_event_data *edata)
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{
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struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
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unsigned long flags;
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u32 dfi_wr, dfi_rd, dfi_timer;
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local_irq_save(flags);
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rk3128_dfi_stop_hardware_counter(edev);
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regmap_read(info->regmap_grf, RK3128_GRF_DFI_WRNUM, &dfi_wr);
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regmap_read(info->regmap_grf, RK3128_GRF_DFI_RDNUM, &dfi_rd);
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regmap_read(info->regmap_grf, RK3128_GRF_DFI_TIMERVAL, &dfi_timer);
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edata->load_count = (dfi_wr + dfi_rd) * 4;
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edata->total_count = dfi_timer;
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rk3128_dfi_start_hardware_counter(edev);
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local_irq_restore(flags);
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return 0;
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}
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static const struct devfreq_event_ops rk3128_dfi_ops = {
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.disable = rk3128_dfi_disable,
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.enable = rk3128_dfi_enable,
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.get_event = rk3128_dfi_get_event,
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.set_event = rk3128_dfi_set_event,
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};
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static void rk3288_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
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{
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struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
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regmap_write(info->regmap_grf, RK3288_GRF_SOC_CON4, RK3288_DFI_EN);
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}
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static void rk3288_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
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{
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struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
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regmap_write(info->regmap_grf, RK3288_GRF_SOC_CON4, RK3288_DFI_DIS);
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}
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static int rk3288_dfi_disable(struct devfreq_event_dev *edev)
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{
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rk3288_dfi_stop_hardware_counter(edev);
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return 0;
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}
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static int rk3288_dfi_enable(struct devfreq_event_dev *edev)
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{
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rk3288_dfi_start_hardware_counter(edev);
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return 0;
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}
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static int rk3288_dfi_set_event(struct devfreq_event_dev *edev)
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{
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return 0;
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}
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static int rk3288_dfi_get_busier_ch(struct devfreq_event_dev *edev)
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{
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struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
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u32 tmp, max = 0;
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u32 i, busier_ch = 0;
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u32 rd_count, wr_count, total_count;
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rk3288_dfi_stop_hardware_counter(edev);
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/* Find out which channel is busier */
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for (i = 0; i < MAX_DMC_NUM_CH; i++) {
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if (!(info->ch_msk & BIT(i)))
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continue;
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regmap_read(info->regmap_grf,
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RK3288_GRF_SOC_STATUS(11 + i * 4), &wr_count);
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regmap_read(info->regmap_grf,
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RK3288_GRF_SOC_STATUS(12 + i * 4), &rd_count);
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regmap_read(info->regmap_grf,
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RK3288_GRF_SOC_STATUS(14 + i * 4), &total_count);
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info->ch_usage[i].access = (wr_count + rd_count) * 4;
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info->ch_usage[i].total = total_count;
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tmp = info->ch_usage[i].access;
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if (tmp > max) {
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busier_ch = i;
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max = tmp;
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}
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}
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rk3288_dfi_start_hardware_counter(edev);
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return busier_ch;
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}
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static int rk3288_dfi_get_event(struct devfreq_event_dev *edev,
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struct devfreq_event_data *edata)
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{
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struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
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int busier_ch;
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unsigned long flags;
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local_irq_save(flags);
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busier_ch = rk3288_dfi_get_busier_ch(edev);
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local_irq_restore(flags);
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edata->load_count = info->ch_usage[busier_ch].access;
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edata->total_count = info->ch_usage[busier_ch].total;
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return 0;
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}
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static const struct devfreq_event_ops rk3288_dfi_ops = {
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.disable = rk3288_dfi_disable,
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.enable = rk3288_dfi_enable,
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.get_event = rk3288_dfi_get_event,
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.set_event = rk3288_dfi_set_event,
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};
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static void rk3368_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
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{
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struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
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regmap_write(info->regmap_grf, RK3368_GRF_DDRC0_CON0, RK3368_DFI_EN);
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}
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static void rk3368_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
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{
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struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
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regmap_write(info->regmap_grf, RK3368_GRF_DDRC0_CON0, RK3368_DFI_DIS);
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}
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static int rk3368_dfi_disable(struct devfreq_event_dev *edev)
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{
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rk3368_dfi_stop_hardware_counter(edev);
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return 0;
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}
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static int rk3368_dfi_enable(struct devfreq_event_dev *edev)
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{
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rk3368_dfi_start_hardware_counter(edev);
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return 0;
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}
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static int rk3368_dfi_set_event(struct devfreq_event_dev *edev)
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{
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return 0;
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}
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static int rk3368_dfi_get_event(struct devfreq_event_dev *edev,
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struct devfreq_event_data *edata)
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{
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struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
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unsigned long flags;
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u32 dfi0_wr, dfi0_rd, dfi1_wr, dfi1_rd, dfi_timer;
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local_irq_save(flags);
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rk3368_dfi_stop_hardware_counter(edev);
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regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS5, &dfi0_wr);
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regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS6, &dfi0_rd);
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regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS9, &dfi1_wr);
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regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS10, &dfi1_rd);
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regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS8, &dfi_timer);
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edata->load_count = (dfi0_wr + dfi0_rd + dfi1_wr + dfi1_rd) * 2;
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edata->total_count = dfi_timer;
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rk3368_dfi_start_hardware_counter(edev);
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local_irq_restore(flags);
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return 0;
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}
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static const struct devfreq_event_ops rk3368_dfi_ops = {
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.disable = rk3368_dfi_disable,
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.enable = rk3368_dfi_enable,
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.get_event = rk3368_dfi_get_event,
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.set_event = rk3368_dfi_set_event,
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};
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static void rockchip_dfi_get_mon_version(struct devfreq_event_dev *edev)
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{
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struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
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void __iomem *dfi_regs = info->regs;
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info->mon_version = readl_relaxed(dfi_regs);
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if (info->mon_version < 0x40) {
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info->mon_ctrl0 = 0x4;
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info->mon_ctrl1 = 0x4;
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info->mon_access_num = 0x2c;
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info->mon_count_num = 0x28;
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} else {
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info->mon_ctrl0 = 0x4;
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info->mon_ctrl1 = 0x8;
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info->mon_access_num = 0x34;
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info->mon_count_num = 0x30;
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}
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}
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static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
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{
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struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
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void __iomem *dfi_regs = info->regs;
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u32 mon_idx = 0, val_6 = 0;
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u32 ctrl0 = info->mon_ctrl0, ctrl1 = info->mon_ctrl1;
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u32 i;
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if (info->mon_idx)
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mon_idx = info->mon_idx;
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if (info->dram_dynamic_info_reg)
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regmap_read(info->regmap_pmugrf, info->dram_dynamic_info_reg, &val_6);
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if (info->dram_type == LPDDR5) {
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info->lp5_bank_mode = READ_LP5_BANK_MODE(val_6);
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info->lp5_ckr = READ_LP5_CKR(val_6);
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}
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for (i = 0; i < MAX_DMC_NUM_CH; i++) {
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if (!(info->ch_msk & BIT(i)))
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continue;
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if (i > 0 && mon_idx == 0)
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continue;
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/* clear DDRMON_CTRL setting */
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writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + i * mon_idx + ctrl0);
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/* set ddr type to dfi */
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if (info->dram_type == LPDDR3 || info->dram_type == LPDDR2) {
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writel_relaxed(LPDDR2_3_EN, dfi_regs + i * mon_idx + ctrl0);
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} else if (info->dram_type == LPDDR4 || info->dram_type == LPDDR4X) {
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writel_relaxed(LPDDR4_EN, dfi_regs + i * mon_idx + ctrl0);
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} else if ((info->dram_type == DDR2) || (info->dram_type == DDR3)) {
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writel_relaxed(DDR2_3_EN, dfi_regs + i * mon_idx + ctrl0);
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} else if (info->dram_type == DDR4) {
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writel_relaxed(DDR4_EN, dfi_regs + i * mon_idx + ctrl0);
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} else if (info->dram_type == LPDDR5) {
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if (info->mon_version < 0x40)
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writel_relaxed(LPDDR5_EN | LPDDR5_BANK_MODE(info->lp5_bank_mode),
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dfi_regs + i * mon_idx + ctrl0);
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else
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writel_relaxed(LPDDR5_EN_CTRL1 |
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LPDDR5_BANK_MODE_CTRL1(info->lp5_bank_mode),
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dfi_regs + i * mon_idx + ctrl1);
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}
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/* enable count, use software mode */
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writel_relaxed(SOFTWARE_EN, dfi_regs + i * mon_idx + ctrl0);
|
|
}
|
|
}
|
|
|
|
static void rockchip_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
|
|
{
|
|
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
|
void __iomem *dfi_regs = info->regs;
|
|
u32 mon_idx = 0, i;
|
|
|
|
if (info->mon_idx)
|
|
mon_idx = info->mon_idx;
|
|
|
|
for (i = 0; i < MAX_DMC_NUM_CH; i++) {
|
|
if (!(info->ch_msk & BIT(i)))
|
|
continue;
|
|
|
|
if (i > 0 && mon_idx == 0)
|
|
continue;
|
|
|
|
writel_relaxed(SOFTWARE_DIS, dfi_regs + i * mon_idx + DDRMON_CTRL);
|
|
}
|
|
}
|
|
|
|
static int rockchip_dfi_get_busier_ch(struct devfreq_event_dev *edev)
|
|
{
|
|
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
|
u32 tmp, max = 0;
|
|
u32 i, busier_ch = 0;
|
|
void __iomem *dfi_regs = info->regs;
|
|
u32 mon_idx = 0x14, count_rate = 1;
|
|
|
|
rockchip_dfi_stop_hardware_counter(edev);
|
|
|
|
if (info->mon_idx)
|
|
mon_idx = info->mon_idx;
|
|
if (info->count_rate)
|
|
count_rate = info->count_rate;
|
|
|
|
/* Find out which channel is busier */
|
|
for (i = 0; i < MAX_DMC_NUM_CH; i++) {
|
|
if (!(info->ch_msk & BIT(i)))
|
|
continue;
|
|
|
|
/* rk3588 counter is dfi clk rate */
|
|
info->ch_usage[i].total = readl_relaxed(dfi_regs +
|
|
info->mon_count_num + i * mon_idx) * count_rate;
|
|
|
|
/* LPDDR5 LPDDR4 and LPDDR4X BL = 16,other DDR type BL = 8 */
|
|
tmp = readl_relaxed(dfi_regs +
|
|
info->mon_access_num + i * mon_idx);
|
|
if (info->dram_type == LPDDR4 || info->dram_type == LPDDR4X)
|
|
tmp *= 8;
|
|
else if (info->dram_type == LPDDR5)
|
|
tmp *= 16 / (4 << info->lp5_ckr);
|
|
else
|
|
tmp *= 4;
|
|
info->ch_usage[i].access = tmp;
|
|
|
|
if (tmp > max) {
|
|
busier_ch = i;
|
|
max = tmp;
|
|
}
|
|
}
|
|
rockchip_dfi_start_hardware_counter(edev);
|
|
|
|
return busier_ch;
|
|
}
|
|
|
|
static int rockchip_dfi_clk_enable(struct rockchip_dfi *info)
|
|
{
|
|
u32 i;
|
|
int ret;
|
|
|
|
for (i = 0; i < MAX_DMC_NUM_CH; i++) {
|
|
if (!(info->ch_msk & BIT(i)))
|
|
continue;
|
|
if (info->clk[i]) {
|
|
ret = clk_prepare_enable(info->clk[i]);
|
|
if (ret) {
|
|
dev_err(info->dev, "failed to enable ch%d dfi clk: %d\n",
|
|
i, ret);
|
|
return ret;
|
|
}
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rockchip_dfi_clk_disable(struct rockchip_dfi *info)
|
|
{
|
|
u32 i;
|
|
|
|
for (i = 0; i < MAX_DMC_NUM_CH; i++) {
|
|
if (!(info->ch_msk & BIT(i)))
|
|
continue;
|
|
if (info->clk[i])
|
|
clk_disable_unprepare(info->clk[i]);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
static int rockchip_dfi_disable(struct devfreq_event_dev *edev)
|
|
{
|
|
int ret;
|
|
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
|
|
|
ret = rockchip_dfi_clk_enable(info);
|
|
if (ret)
|
|
return ret;
|
|
|
|
rockchip_dfi_stop_hardware_counter(edev);
|
|
rockchip_dfi_clk_disable(info);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rockchip_dfi_enable(struct devfreq_event_dev *edev)
|
|
{
|
|
int ret;
|
|
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
|
|
|
ret = rockchip_dfi_clk_enable(info);
|
|
if (ret)
|
|
return ret;
|
|
|
|
rockchip_dfi_get_mon_version(edev);
|
|
|
|
rockchip_dfi_start_hardware_counter(edev);
|
|
rockchip_dfi_clk_disable(info);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rockchip_dfi_set_event(struct devfreq_event_dev *edev)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int rockchip_dfi_get_event(struct devfreq_event_dev *edev,
|
|
struct devfreq_event_data *edata)
|
|
{
|
|
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
|
int busier_ch;
|
|
unsigned long flags;
|
|
int ret;
|
|
|
|
ret = rockchip_dfi_clk_enable(info);
|
|
if (ret)
|
|
return ret;
|
|
|
|
local_irq_save(flags);
|
|
busier_ch = rockchip_dfi_get_busier_ch(edev);
|
|
local_irq_restore(flags);
|
|
|
|
rockchip_dfi_clk_disable(info);
|
|
|
|
edata->load_count = info->ch_usage[busier_ch].access;
|
|
edata->total_count = info->ch_usage[busier_ch].total;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct devfreq_event_ops rockchip_dfi_ops = {
|
|
.disable = rockchip_dfi_disable,
|
|
.enable = rockchip_dfi_enable,
|
|
.get_event = rockchip_dfi_get_event,
|
|
.set_event = rockchip_dfi_set_event,
|
|
};
|
|
|
|
static __maybe_unused __init int rk3588_dfi_init(struct platform_device *pdev,
|
|
struct rockchip_dfi *data,
|
|
struct devfreq_event_desc *desc)
|
|
{
|
|
struct device_node *np = pdev->dev.of_node;
|
|
struct resource *res;
|
|
u32 val_2, val_3, val_4, i;
|
|
char clk_name[20];
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
data->regs = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(data->regs))
|
|
return PTR_ERR(data->regs);
|
|
|
|
data->regmap_pmugrf = syscon_regmap_lookup_by_phandle(np, "rockchip,pmu_grf");
|
|
if (IS_ERR(data->regmap_pmugrf))
|
|
return PTR_ERR(data->regmap_pmugrf);
|
|
|
|
regmap_read(data->regmap_pmugrf, RK3588_PMUGRF_OS_REG(2), &val_2);
|
|
regmap_read(data->regmap_pmugrf, RK3588_PMUGRF_OS_REG(3), &val_3);
|
|
regmap_read(data->regmap_pmugrf, RK3588_PMUGRF_OS_REG(4), &val_4);
|
|
if (READ_SYSREG_VERSION(val_3) >= 0x3)
|
|
data->dram_type = READ_DRAMTYPE_INFO_V3(val_2, val_3);
|
|
else
|
|
data->dram_type = READ_DRAMTYPE_INFO(val_2);
|
|
|
|
data->mon_idx = 0x4000;
|
|
if (data->dram_type == LPDDR5)
|
|
data->count_rate = 1;
|
|
else
|
|
data->count_rate = 2;
|
|
data->dram_dynamic_info_reg = RK3588_PMUGRF_OS_REG(6);
|
|
data->ch_msk = READ_CH_INFO(val_2) | READ_CH_INFO(val_4) << 2;
|
|
|
|
for (i = 0; i < MAX_DMC_NUM_CH; i++) {
|
|
if (data->ch_msk & BIT(i)) {
|
|
snprintf(clk_name, sizeof(clk_name), "pclk_ddr_mon_ch%d", i);
|
|
data->clk[i] = devm_clk_get(&pdev->dev, clk_name);
|
|
if (IS_ERR(data->clk[i])) {
|
|
dev_err(&pdev->dev, "Failed to get %s\n", clk_name);
|
|
return PTR_ERR(data->clk[i]);
|
|
}
|
|
}
|
|
}
|
|
|
|
desc->ops = &rockchip_dfi_ops;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static __maybe_unused __init int rk3576_dfi_init(struct platform_device *pdev,
|
|
struct rockchip_dfi *data,
|
|
struct devfreq_event_desc *desc)
|
|
{
|
|
int ret;
|
|
|
|
ret = rk3588_dfi_init(pdev, data, desc);
|
|
if (ret)
|
|
return ret;
|
|
|
|
data->mon_idx = 0x10000;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static __maybe_unused __init int px30_dfi_init(struct platform_device *pdev,
|
|
struct rockchip_dfi *data,
|
|
struct devfreq_event_desc *desc)
|
|
{
|
|
struct device_node *np = pdev->dev.of_node, *node;
|
|
struct resource *res;
|
|
u32 val_2, val_3;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
data->regs = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(data->regs))
|
|
return PTR_ERR(data->regs);
|
|
|
|
node = of_parse_phandle(np, "rockchip,pmugrf", 0);
|
|
if (node) {
|
|
data->regmap_pmugrf = syscon_node_to_regmap(node);
|
|
if (IS_ERR(data->regmap_pmugrf))
|
|
return PTR_ERR(data->regmap_pmugrf);
|
|
}
|
|
|
|
regmap_read(data->regmap_pmugrf, PX30_PMUGRF_OS_REG2, &val_2);
|
|
regmap_read(data->regmap_pmugrf, PX30_PMUGRF_OS_REG3, &val_3);
|
|
if (READ_SYSREG_VERSION(val_3) >= 0x3)
|
|
data->dram_type = READ_DRAMTYPE_INFO_V3(val_2, val_3);
|
|
else
|
|
data->dram_type = READ_DRAMTYPE_INFO(val_2);
|
|
data->ch_msk = 1;
|
|
|
|
desc->ops = &rockchip_dfi_ops;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static __maybe_unused __init int rk3128_dfi_init(struct platform_device *pdev,
|
|
struct rockchip_dfi *data,
|
|
struct devfreq_event_desc *desc)
|
|
{
|
|
struct device_node *np = pdev->dev.of_node, *node;
|
|
|
|
node = of_parse_phandle(np, "rockchip,grf", 0);
|
|
if (node) {
|
|
data->regmap_grf = syscon_node_to_regmap(node);
|
|
if (IS_ERR(data->regmap_grf))
|
|
return PTR_ERR(data->regmap_grf);
|
|
}
|
|
|
|
desc->ops = &rk3128_dfi_ops;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static __maybe_unused __init int rk3288_dfi_init(struct platform_device *pdev,
|
|
struct rockchip_dfi *data,
|
|
struct devfreq_event_desc *desc)
|
|
{
|
|
struct device_node *np = pdev->dev.of_node, *node;
|
|
u32 val;
|
|
|
|
node = of_parse_phandle(np, "rockchip,pmu", 0);
|
|
if (node) {
|
|
data->regmap_pmu = syscon_node_to_regmap(node);
|
|
if (IS_ERR(data->regmap_pmu))
|
|
return PTR_ERR(data->regmap_pmu);
|
|
}
|
|
|
|
node = of_parse_phandle(np, "rockchip,grf", 0);
|
|
if (node) {
|
|
data->regmap_grf = syscon_node_to_regmap(node);
|
|
if (IS_ERR(data->regmap_grf))
|
|
return PTR_ERR(data->regmap_grf);
|
|
}
|
|
|
|
regmap_read(data->regmap_pmu, RK3288_PMU_SYS_REG2, &val);
|
|
data->dram_type = READ_DRAMTYPE_INFO(val);
|
|
data->ch_msk = READ_CH_INFO(val);
|
|
|
|
if (data->dram_type == DDR3)
|
|
regmap_write(data->regmap_grf, RK3288_GRF_SOC_CON4,
|
|
RK3288_DDR3_SEL);
|
|
else
|
|
regmap_write(data->regmap_grf, RK3288_GRF_SOC_CON4,
|
|
RK3288_LPDDR_SEL);
|
|
|
|
desc->ops = &rk3288_dfi_ops;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static __maybe_unused __init int rk3368_dfi_init(struct platform_device *pdev,
|
|
struct rockchip_dfi *data,
|
|
struct devfreq_event_desc *desc)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
|
|
if (!dev->parent || !dev->parent->of_node)
|
|
return -EINVAL;
|
|
|
|
data->regmap_grf = syscon_node_to_regmap(dev->parent->of_node);
|
|
if (IS_ERR(data->regmap_grf))
|
|
return PTR_ERR(data->regmap_grf);
|
|
|
|
desc->ops = &rk3368_dfi_ops;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static __maybe_unused __init int rockchip_dfi_init(struct platform_device *pdev,
|
|
struct rockchip_dfi *data,
|
|
struct devfreq_event_desc *desc)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct device_node *np = pdev->dev.of_node, *node;
|
|
u32 val;
|
|
|
|
data->regs = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(data->regs))
|
|
return PTR_ERR(data->regs);
|
|
|
|
data->clk[0] = devm_clk_get(dev, "pclk_ddr_mon");
|
|
if (IS_ERR(data->clk[0]))
|
|
return dev_err_probe(dev, PTR_ERR(data->clk[0]),
|
|
"Cannot get the clk pclk_ddr_mon\n");
|
|
|
|
node = of_parse_phandle(np, "rockchip,pmu", 0);
|
|
if (!node)
|
|
return dev_err_probe(&pdev->dev, -ENODEV, "Can't find pmu_grf registers\n");
|
|
|
|
data->regmap_pmu = syscon_node_to_regmap(node);
|
|
of_node_put(node);
|
|
if (IS_ERR(data->regmap_pmu))
|
|
return PTR_ERR(data->regmap_pmu);
|
|
|
|
regmap_read(data->regmap_pmu, PMUGRF_OS_REG2, &val);
|
|
data->dram_type = READ_DRAMTYPE_INFO(val);
|
|
data->ch_msk = READ_CH_INFO(val);
|
|
|
|
desc->ops = &rockchip_dfi_ops;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static __maybe_unused __init int rk3328_dfi_init(struct platform_device *pdev,
|
|
struct rockchip_dfi *data,
|
|
struct devfreq_event_desc *desc)
|
|
{
|
|
struct device_node *np = pdev->dev.of_node, *node;
|
|
struct resource *res;
|
|
u32 val;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
data->regs = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(data->regs))
|
|
return PTR_ERR(data->regs);
|
|
|
|
node = of_parse_phandle(np, "rockchip,grf", 0);
|
|
if (node) {
|
|
data->regmap_grf = syscon_node_to_regmap(node);
|
|
if (IS_ERR(data->regmap_grf))
|
|
return PTR_ERR(data->regmap_grf);
|
|
}
|
|
|
|
regmap_read(data->regmap_grf, RK3328_GRF_OS_REG2, &val);
|
|
data->dram_type = READ_DRAMTYPE_INFO(val);
|
|
data->ch_msk = 1;
|
|
|
|
desc->ops = &rockchip_dfi_ops;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static __maybe_unused __init int rk3528_dfi_init(struct platform_device *pdev,
|
|
struct rockchip_dfi *data,
|
|
struct devfreq_event_desc *desc)
|
|
{
|
|
struct device_node *np = pdev->dev.of_node, *node;
|
|
struct resource *res;
|
|
u32 val_18, val_19;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
data->regs = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(data->regs))
|
|
return PTR_ERR(data->regs);
|
|
|
|
node = of_parse_phandle(np, "rockchip,grf", 0);
|
|
if (node) {
|
|
data->regmap_grf = syscon_node_to_regmap(node);
|
|
if (IS_ERR(data->regmap_grf))
|
|
return PTR_ERR(data->regmap_grf);
|
|
}
|
|
|
|
regmap_read(data->regmap_grf, RK3528_PMUGRF_OFFSET + RK3528_PMUGRF_OS_REG18, &val_18);
|
|
regmap_read(data->regmap_grf, RK3528_PMUGRF_OFFSET + RK3528_PMUGRF_OS_REG19, &val_19);
|
|
if (READ_SYSREG_VERSION(val_19) >= 0x3)
|
|
data->dram_type = READ_DRAMTYPE_INFO_V3(val_18, val_19);
|
|
else
|
|
data->dram_type = READ_DRAMTYPE_INFO(val_18);
|
|
data->count_rate = 2;
|
|
data->ch_msk = 1;
|
|
|
|
desc->ops = &rockchip_dfi_ops;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id rockchip_dfi_id_match[] = {
|
|
#ifdef CONFIG_CPU_PX30
|
|
{ .compatible = "rockchip,px30-dfi", .data = px30_dfi_init },
|
|
#endif
|
|
#ifdef CONFIG_CPU_RK1808
|
|
{ .compatible = "rockchip,rk1808-dfi", .data = px30_dfi_init },
|
|
#endif
|
|
#ifdef CONFIG_CPU_RK312X
|
|
{ .compatible = "rockchip,rk3128-dfi", .data = rk3128_dfi_init },
|
|
#endif
|
|
#ifdef CONFIG_CPU_RK3288
|
|
{ .compatible = "rockchip,rk3288-dfi", .data = rk3288_dfi_init },
|
|
#endif
|
|
#ifdef CONFIG_CPU_RK3328
|
|
{ .compatible = "rockchip,rk3328-dfi", .data = rk3328_dfi_init },
|
|
#endif
|
|
#ifdef CONFIG_CPU_RK3368
|
|
{ .compatible = "rockchip,rk3368-dfi", .data = rk3368_dfi_init },
|
|
#endif
|
|
#ifdef CONFIG_CPU_RK3399
|
|
{ .compatible = "rockchip,rk3399-dfi", .data = rockchip_dfi_init },
|
|
#endif
|
|
#ifdef CONFIG_CPU_RK3528
|
|
{ .compatible = "rockchip,rk3528-dfi", .data = rk3528_dfi_init },
|
|
#endif
|
|
#ifdef CONFIG_CPU_RK3562
|
|
{ .compatible = "rockchip,rk3562-dfi", .data = px30_dfi_init },
|
|
#endif
|
|
#ifdef CONFIG_CPU_RK3568
|
|
{ .compatible = "rockchip,rk3568-dfi", .data = px30_dfi_init },
|
|
#endif
|
|
#ifdef CONFIG_CPU_RK3576
|
|
{ .compatible = "rockchip,rk3576-dfi", .data = rk3576_dfi_init },
|
|
#endif
|
|
#ifdef CONFIG_CPU_RK3588
|
|
{ .compatible = "rockchip,rk3588-dfi", .data = rk3588_dfi_init },
|
|
#endif
|
|
#ifdef CONFIG_CPU_RV1126
|
|
{ .compatible = "rockchip,rv1126-dfi", .data = px30_dfi_init },
|
|
#endif
|
|
{ },
|
|
};
|
|
|
|
static int rockchip_dfi_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct rockchip_dfi *data;
|
|
struct devfreq_event_desc *desc;
|
|
struct device_node *np = pdev->dev.of_node;
|
|
const struct of_device_id *match;
|
|
int (*init)(struct platform_device *pdev, struct rockchip_dfi *data,
|
|
struct devfreq_event_desc *desc);
|
|
|
|
data = devm_kzalloc(dev, sizeof(struct rockchip_dfi), GFP_KERNEL);
|
|
if (!data)
|
|
return -ENOMEM;
|
|
|
|
desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
|
|
if (!desc)
|
|
return -ENOMEM;
|
|
|
|
match = of_match_node(rockchip_dfi_id_match, pdev->dev.of_node);
|
|
if (match) {
|
|
init = match->data;
|
|
if (init) {
|
|
if (init(pdev, data, desc))
|
|
return -EINVAL;
|
|
} else {
|
|
return 0;
|
|
}
|
|
} else {
|
|
return 0;
|
|
}
|
|
|
|
desc->driver_data = data;
|
|
desc->name = np->name;
|
|
|
|
data->edev = devm_devfreq_event_add_edev(dev, desc);
|
|
if (IS_ERR(data->edev)) {
|
|
dev_err(dev, "failed to add devfreq-event device\n");
|
|
return PTR_ERR(data->edev);
|
|
}
|
|
data->desc = desc;
|
|
data->dev = &pdev->dev;
|
|
|
|
platform_set_drvdata(pdev, data);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver rockchip_dfi_driver = {
|
|
.probe = rockchip_dfi_probe,
|
|
.driver = {
|
|
.name = "rockchip-dfi",
|
|
.of_match_table = rockchip_dfi_id_match,
|
|
},
|
|
};
|
|
module_platform_driver(rockchip_dfi_driver);
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
|
|
MODULE_DESCRIPTION("Rockchip DFI driver");
|