937 lines
23 KiB
C
937 lines
23 KiB
C
/*
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* Rockchip CPUFreq Driver
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*
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* Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/cpu.h>
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#include <linux/cpufreq.h>
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#include <linux/cpuidle.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/nvmem-consumer.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/panic_notifier.h>
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#include <linux/platform_device.h>
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#include <linux/pm_opp.h>
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#include <linux/pm_qos.h>
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#include <linux/slab.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#include <linux/rockchip/cpu.h>
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#include <soc/rockchip/rockchip_opp_select.h>
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#include <soc/rockchip/rockchip_system_monitor.h>
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#include "cpufreq-dt.h"
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#include "rockchip-cpufreq.h"
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struct cluster_info {
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struct list_head list_head;
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struct monitor_dev_info *mdev_info;
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struct rockchip_opp_info opp_info;
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struct freq_qos_request bus_qos_req;
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cpumask_t cpus;
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unsigned int idle_threshold_freq;
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unsigned int cpu_freq_percent;
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bool is_idle_disabled;
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bool is_opp_shared_cpu_bus;
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unsigned long rate;
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unsigned long volt, mem_volt;
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};
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static LIST_HEAD(cluster_info_list);
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static struct cluster_info *rockchip_cluster_info_lookup(int cpu);
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static int px30_get_soc_info(struct device *dev, struct device_node *np,
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int *bin, int *process)
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{
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int ret = 0;
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u8 value = 0;
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if (!bin)
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return 0;
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if (of_property_match_string(np, "nvmem-cell-names",
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"performance") >= 0) {
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ret = rockchip_nvmem_cell_read_u8(np, "performance", &value);
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if (ret) {
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dev_err(dev, "Failed to get soc performance value\n");
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return ret;
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}
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*bin = value;
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}
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if (*bin >= 0)
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dev_info(dev, "bin=%d\n", *bin);
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return ret;
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}
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static int rk3288_get_soc_info(struct device *dev, struct device_node *np,
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int *bin, int *process)
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{
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int ret = 0;
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u8 value = 0;
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char *name;
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if (!bin)
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goto next;
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if (of_property_match_string(np, "nvmem-cell-names", "special") >= 0) {
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ret = rockchip_nvmem_cell_read_u8(np, "special", &value);
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if (ret) {
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dev_err(dev, "Failed to get soc special value\n");
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goto out;
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}
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if (value == 0xc)
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*bin = 0;
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else
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*bin = 1;
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}
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if (soc_is_rk3288w())
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name = "performance-w";
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else
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name = "performance";
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if (of_property_match_string(np, "nvmem-cell-names", name) >= 0) {
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ret = rockchip_nvmem_cell_read_u8(np, name, &value);
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if (ret) {
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dev_err(dev, "Failed to get soc performance value\n");
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goto out;
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}
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if (value & 0x2)
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*bin = 3;
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else if (value & 0x01)
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*bin = 2;
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}
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if (*bin >= 0)
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dev_info(dev, "bin=%d\n", *bin);
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next:
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if (!process)
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goto out;
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if (of_property_match_string(np, "nvmem-cell-names",
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"process") >= 0) {
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ret = rockchip_nvmem_cell_read_u8(np, "process", &value);
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if (ret) {
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dev_err(dev, "Failed to get soc process version\n");
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goto out;
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}
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if (soc_is_rk3288() && (value == 0 || value == 1))
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*process = 0;
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}
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if (*process >= 0)
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dev_info(dev, "process=%d\n", *process);
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out:
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return ret;
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}
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static int rk3399_get_soc_info(struct device *dev, struct device_node *np,
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int *bin, int *process)
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{
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int ret = 0;
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u8 value = 0;
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if (!bin)
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return 0;
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if (of_property_match_string(np, "nvmem-cell-names",
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"specification_serial_number") >= 0) {
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ret = rockchip_nvmem_cell_read_u8(np,
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"specification_serial_number",
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&value);
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if (ret) {
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dev_err(dev,
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"Failed to get specification_serial_number\n");
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goto out;
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}
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if (value == 0xb) {
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*bin = 0;
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} else if (value == 0x1) {
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if (of_property_match_string(np, "nvmem-cell-names",
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"customer_demand") >= 0) {
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ret = rockchip_nvmem_cell_read_u8(np,
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"customer_demand",
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&value);
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if (ret) {
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dev_err(dev, "Failed to get customer_demand\n");
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goto out;
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}
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if (value == 0x0)
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*bin = 0;
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else
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*bin = 1;
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}
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} else if (value == 0x10) {
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*bin = 1;
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}
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}
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out:
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if (*bin >= 0)
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dev_info(dev, "bin=%d\n", *bin);
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return ret;
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}
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static int rk3576_cpu_set_read_margin(struct device *dev,
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struct rockchip_opp_info *opp_info,
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u32 rm)
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{
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if (!opp_info->volt_rm_tbl)
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return 0;
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if (rm == opp_info->current_rm || rm == UINT_MAX)
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return 0;
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dev_dbg(dev, "set rm to %d\n", rm);
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if (opp_info->grf) {
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regmap_write(opp_info->grf, 0x3c, 0x001c0000 | (rm << 2));
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regmap_write(opp_info->grf, 0x44, 0x001c0000 | (rm << 2));
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regmap_write(opp_info->grf, 0x38, 0x00020002);
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udelay(1);
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regmap_write(opp_info->grf, 0x38, 0x00020000);
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}
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if (opp_info->cci_grf)
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regmap_write(opp_info->cci_grf, 0x54, 0x001c0000 | (rm << 2));
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opp_info->current_rm = rm;
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return 0;
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}
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static int rk3588_get_soc_info(struct device *dev, struct device_node *np,
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int *bin, int *process)
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{
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int ret = 0;
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u8 value = 0;
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if (!bin)
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return 0;
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if (of_property_match_string(np, "nvmem-cell-names",
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"specification_serial_number") >= 0) {
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ret = rockchip_nvmem_cell_read_u8(np,
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"specification_serial_number",
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&value);
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if (ret) {
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dev_err(dev,
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"Failed to get specification_serial_number\n");
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return ret;
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}
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/* RK3588M */
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if (value == 0xd)
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*bin = 1;
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/* RK3588J */
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else if (value == 0xa)
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*bin = 2;
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}
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if (*bin < 0)
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*bin = 0;
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dev_info(dev, "bin=%d\n", *bin);
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return ret;
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}
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static int rk3588_change_length(struct device *dev, struct device_node *np,
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struct rockchip_opp_info *opp_info)
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{
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struct clk *clk;
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unsigned long old_rate;
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unsigned int low_len_sel;
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u32 opp_flag = 0;
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int ret = 0;
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if (opp_info->volt_sel < 0)
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return 0;
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clk = clk_get(dev, NULL);
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if (IS_ERR(clk)) {
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dev_warn(dev, "failed to get cpu clk\n");
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return PTR_ERR(clk);
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}
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/* RK3588 low speed grade should change to low length */
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if (of_property_read_u32(np, "rockchip,pvtm-low-len-sel",
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&low_len_sel))
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goto out;
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if (opp_info->volt_sel > low_len_sel)
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goto out;
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opp_flag = OPP_LENGTH_LOW;
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old_rate = clk_get_rate(clk);
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ret = clk_set_rate(clk, old_rate | opp_flag);
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if (ret) {
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dev_err(dev, "failed to change length\n");
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goto out;
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}
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clk_set_rate(clk, old_rate);
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out:
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clk_put(clk);
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return ret;
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}
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static int rk3588_set_supported_hw(struct device *dev, struct device_node *np,
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struct rockchip_opp_info *opp_info)
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{
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int bin = opp_info->bin;
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if (!of_property_read_bool(np, "rockchip,supported-hw"))
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return 0;
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if (bin < 0)
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bin = 0;
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/* SoC Version */
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opp_info->supported_hw[0] = BIT(bin);
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/* Speed Grade */
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opp_info->supported_hw[1] = BIT(opp_info->volt_sel);
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return 0;
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}
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static int rk3588_set_soc_info(struct device *dev, struct device_node *np,
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struct rockchip_opp_info *opp_info)
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{
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rk3588_change_length(dev, np, opp_info);
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rk3588_set_supported_hw(dev, np, opp_info);
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return 0;
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}
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static int rk3588_cpu_set_read_margin(struct device *dev,
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struct rockchip_opp_info *opp_info,
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u32 rm)
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{
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if (!opp_info->volt_rm_tbl)
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return 0;
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if (rm == opp_info->current_rm || rm == UINT_MAX)
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return 0;
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dev_dbg(dev, "set rm to %d\n", rm);
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if (opp_info->grf) {
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regmap_write(opp_info->grf, 0x20, 0x001c0000 | (rm << 2));
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regmap_write(opp_info->grf, 0x28, 0x003c0000 | (rm << 2));
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regmap_write(opp_info->grf, 0x2c, 0x003c0000 | (rm << 2));
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regmap_write(opp_info->grf, 0x30, 0x00200020);
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udelay(1);
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regmap_write(opp_info->grf, 0x30, 0x00200000);
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}
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if (opp_info->dsu_grf) {
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regmap_write(opp_info->dsu_grf, 0x20, 0x001c0000 | (rm << 2));
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regmap_write(opp_info->dsu_grf, 0x28, 0x003c0000 | (rm << 2));
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regmap_write(opp_info->dsu_grf, 0x2c, 0x003c0000 | (rm << 2));
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regmap_write(opp_info->dsu_grf, 0x30, 0x001c0000 | (rm << 2));
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regmap_write(opp_info->dsu_grf, 0x38, 0x001c0000 | (rm << 2));
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regmap_write(opp_info->dsu_grf, 0x18, 0x40004000);
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udelay(1);
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regmap_write(opp_info->dsu_grf, 0x18, 0x40000000);
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}
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opp_info->current_rm = rm;
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return 0;
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}
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static int cpu_opp_config_regulators(struct device *dev,
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struct dev_pm_opp *old_opp,
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struct dev_pm_opp *new_opp,
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struct regulator **regulators,
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unsigned int count)
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{
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struct cluster_info *cluster;
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cluster = rockchip_cluster_info_lookup(dev->id);
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if (!cluster)
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return -EINVAL;
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return rockchip_opp_config_regulators(dev, old_opp, new_opp, regulators,
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count, &cluster->opp_info);
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}
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static int rv1126_get_soc_info(struct device *dev, struct device_node *np,
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int *bin, int *process)
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{
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int ret = 0;
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u8 value = 0;
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if (of_property_match_string(np, "nvmem-cell-names", "performance") >= 0) {
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ret = rockchip_nvmem_cell_read_u8(np, "performance", &value);
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if (ret) {
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dev_err(dev, "Failed to get soc performance value\n");
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return ret;
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}
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if (value == 0x1)
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*bin = 1;
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else
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*bin = 0;
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}
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if (*bin >= 0)
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dev_info(dev, "bin=%d\n", *bin);
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return ret;
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}
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static const struct rockchip_opp_data px30_cpu_opp_data = {
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.get_soc_info = px30_get_soc_info,
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};
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static const struct rockchip_opp_data rk3288_cpu_opp_data = {
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.get_soc_info = rk3288_get_soc_info,
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};
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static const struct rockchip_opp_data rk3399_cpu_opp_data = {
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.get_soc_info = rk3399_get_soc_info,
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};
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static const struct rockchip_opp_data rk3588_cpu_opp_data = {
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.get_soc_info = rk3588_get_soc_info,
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.set_soc_info = rk3588_set_soc_info,
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.set_read_margin = rk3588_cpu_set_read_margin,
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.config_regulators = cpu_opp_config_regulators,
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};
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static const struct rockchip_opp_data rk3576_cpu_opp_data = {
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.set_read_margin = rk3576_cpu_set_read_margin,
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.set_soc_info = rockchip_opp_set_low_length,
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.config_regulators = cpu_opp_config_regulators,
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};
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static const struct rockchip_opp_data rv1126_cpu_opp_data = {
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.get_soc_info = rv1126_get_soc_info,
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};
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static const struct of_device_id rockchip_cpufreq_of_match[] = {
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{
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.compatible = "rockchip,px30",
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.data = (void *)&px30_cpu_opp_data,
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},
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{
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.compatible = "rockchip,rk3288",
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.data = (void *)&rk3288_cpu_opp_data,
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},
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{
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.compatible = "rockchip,rk3288w",
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.data = (void *)&rk3288_cpu_opp_data,
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},
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{
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.compatible = "rockchip,rk3326",
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.data = (void *)&px30_cpu_opp_data,
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},
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{
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.compatible = "rockchip,rk3399",
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.data = (void *)&rk3399_cpu_opp_data,
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},
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{
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.compatible = "rockchip,rk3576",
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.data = (void *)&rk3576_cpu_opp_data,
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},
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{
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.compatible = "rockchip,rk3588",
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.data = (void *)&rk3588_cpu_opp_data,
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},
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{
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.compatible = "rockchip,rv1109",
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.data = (void *)&rv1126_cpu_opp_data,
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},
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{
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.compatible = "rockchip,rv1126",
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.data = (void *)&rv1126_cpu_opp_data,
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},
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{},
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};
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static struct cluster_info *rockchip_cluster_info_lookup(int cpu)
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{
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struct cluster_info *cluster;
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list_for_each_entry(cluster, &cluster_info_list, list_head) {
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if (cpumask_test_cpu(cpu, &cluster->cpus))
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return cluster;
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}
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return NULL;
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}
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static int rockchip_cpufreq_cluster_init(int cpu, struct cluster_info *cluster)
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{
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struct rockchip_opp_info *opp_info = &cluster->opp_info;
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struct device_node *np;
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struct device *dev;
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char *reg_name;
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int ret = 0;
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u32 freq = 0;
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dev = get_cpu_device(cpu);
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if (!dev)
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return -ENODEV;
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np = of_parse_phandle(dev->of_node, "operating-points-v2", 0);
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if (!np) {
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dev_warn(dev, "OPP-v2 not supported\n");
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return -ENOENT;
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}
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ret = dev_pm_opp_of_get_sharing_cpus(dev, &cluster->cpus);
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if (ret) {
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dev_err(dev, "Failed to get sharing cpus\n");
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of_node_put(np);
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return ret;
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}
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if (of_property_read_bool(np, "rockchip,opp-shared-dsu") ||
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of_property_read_bool(np, "rockchip,opp-shared-cci"))
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cluster->is_opp_shared_cpu_bus = true;
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of_property_read_u32(np, "rockchip,cpu-freq-percent",
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&cluster->cpu_freq_percent);
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if (!of_property_read_u32(np, "rockchip,idle-threshold-freq", &freq))
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cluster->idle_threshold_freq = freq;
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of_node_put(np);
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if (of_find_property(dev->of_node, "cpu-supply", NULL))
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reg_name = "cpu";
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else if (of_find_property(dev->of_node, "cpu0-supply", NULL))
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reg_name = "cpu0";
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else
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return -ENOENT;
|
|
rockchip_get_opp_data(rockchip_cpufreq_of_match, opp_info);
|
|
ret = rockchip_init_opp_info(dev, opp_info, NULL, reg_name);
|
|
if (ret)
|
|
dev_err(dev, "failed to init opp info\n");
|
|
|
|
return ret;
|
|
}
|
|
|
|
int rockchip_cpufreq_adjust_table(struct device *dev)
|
|
{
|
|
struct cluster_info *cluster;
|
|
|
|
cluster = rockchip_cluster_info_lookup(dev->id);
|
|
if (!cluster)
|
|
return -EINVAL;
|
|
|
|
return rockchip_adjust_opp_table(dev, &cluster->opp_info);
|
|
}
|
|
EXPORT_SYMBOL_GPL(rockchip_cpufreq_adjust_table);
|
|
|
|
int rockchip_cpufreq_opp_set_rate(struct device *dev, unsigned long target_freq)
|
|
{
|
|
struct cluster_info *cluster;
|
|
struct dev_pm_opp *opp;
|
|
struct rockchip_opp_info *opp_info;
|
|
struct dev_pm_opp_supply supplies[2] = {0};
|
|
unsigned long freq;
|
|
int ret = 0;
|
|
|
|
cluster = rockchip_cluster_info_lookup(dev->id);
|
|
if (!cluster)
|
|
return -EINVAL;
|
|
opp_info = &cluster->opp_info;
|
|
|
|
rockchip_opp_dvfs_lock(opp_info);
|
|
ret = dev_pm_opp_set_rate(dev, target_freq);
|
|
if (!ret) {
|
|
cluster->rate = freq = target_freq;
|
|
opp = dev_pm_opp_find_freq_ceil(dev, &freq);
|
|
if (!IS_ERR(opp)) {
|
|
dev_pm_opp_get_supplies(opp, supplies);
|
|
cluster->volt = supplies[0].u_volt;
|
|
if (opp_info->regulator_count > 1)
|
|
cluster->mem_volt = supplies[1].u_volt;
|
|
dev_pm_opp_put(opp);
|
|
}
|
|
}
|
|
rockchip_opp_dvfs_unlock(opp_info);
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(rockchip_cpufreq_opp_set_rate);
|
|
|
|
static int rockchip_cpufreq_suspend(struct cpufreq_policy *policy)
|
|
{
|
|
int ret = 0;
|
|
|
|
ret = cpufreq_generic_suspend(policy);
|
|
if (!ret)
|
|
rockchip_monitor_suspend_low_temp_adjust(policy->cpu);
|
|
|
|
return ret;
|
|
}
|
|
|
|
int rockchip_cpufreq_online(int cpu)
|
|
{
|
|
struct cluster_info *cluster;
|
|
struct rockchip_opp_info *opp_info;
|
|
|
|
cluster = rockchip_cluster_info_lookup(cpu);
|
|
if (!cluster)
|
|
return -EINVAL;
|
|
opp_info = &cluster->opp_info;
|
|
|
|
opp_info->is_runtime_active = true;
|
|
if (opp_info->data && opp_info->data->set_read_margin)
|
|
opp_info->data->set_read_margin(opp_info->dev, opp_info,
|
|
opp_info->target_rm);
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(rockchip_cpufreq_online);
|
|
|
|
int rockchip_cpufreq_offline(int cpu)
|
|
{
|
|
struct cluster_info *cluster;
|
|
struct rockchip_opp_info *opp_info;
|
|
|
|
cluster = rockchip_cluster_info_lookup(cpu);
|
|
if (!cluster)
|
|
return -EINVAL;
|
|
opp_info = &cluster->opp_info;
|
|
|
|
opp_info->is_runtime_active = false;
|
|
opp_info->current_rm = UINT_MAX;
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(rockchip_cpufreq_offline);
|
|
|
|
static int rockchip_cpufreq_add_monitor(struct cluster_info *cluster,
|
|
struct cpufreq_policy *policy)
|
|
{
|
|
struct device *dev = cluster->opp_info.dev;
|
|
struct monitor_dev_profile *mdevp = NULL;
|
|
struct monitor_dev_info *mdev_info = NULL;
|
|
|
|
mdevp = kzalloc(sizeof(*mdevp), GFP_KERNEL);
|
|
if (!mdevp)
|
|
return -ENOMEM;
|
|
|
|
mdevp->type = MONITOR_TYPE_CPU;
|
|
mdevp->low_temp_adjust = rockchip_monitor_cpu_low_temp_adjust;
|
|
mdevp->high_temp_adjust = rockchip_monitor_cpu_high_temp_adjust;
|
|
mdevp->check_rate_volt = rockchip_monitor_check_rate_volt;
|
|
mdevp->data = (void *)policy;
|
|
mdevp->opp_info = &cluster->opp_info;
|
|
cpumask_copy(&mdevp->allowed_cpus, policy->cpus);
|
|
mdev_info = rockchip_system_monitor_register(dev, mdevp);
|
|
if (IS_ERR(mdev_info)) {
|
|
kfree(mdevp);
|
|
dev_err(dev, "failed to register system monitor\n");
|
|
return -EINVAL;
|
|
}
|
|
mdev_info->devp = mdevp;
|
|
cluster->mdev_info = mdev_info;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rockchip_cpufreq_remove_monitor(struct cluster_info *cluster)
|
|
{
|
|
if (cluster->mdev_info) {
|
|
kfree(cluster->mdev_info->devp);
|
|
rockchip_system_monitor_unregister(cluster->mdev_info);
|
|
cluster->mdev_info = NULL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rockchip_cpufreq_remove_bus_qos(struct cluster_info *cluster)
|
|
{
|
|
struct cluster_info *ci;
|
|
|
|
if (!cluster->is_opp_shared_cpu_bus)
|
|
return 0;
|
|
|
|
list_for_each_entry(ci, &cluster_info_list, list_head) {
|
|
if (ci->is_opp_shared_cpu_bus)
|
|
continue;
|
|
if (freq_qos_request_active(&ci->bus_qos_req))
|
|
freq_qos_remove_request(&ci->bus_qos_req);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rockchip_cpufreq_add_bus_qos_req(struct cluster_info *cluster,
|
|
struct cpufreq_policy *policy)
|
|
{
|
|
struct device *dev = cluster->opp_info.dev;
|
|
struct cluster_info *ci;
|
|
int ret;
|
|
|
|
if (!cluster->is_opp_shared_cpu_bus)
|
|
return 0;
|
|
|
|
list_for_each_entry(ci, &cluster_info_list, list_head) {
|
|
if (ci->is_opp_shared_cpu_bus)
|
|
continue;
|
|
ret = freq_qos_add_request(&policy->constraints,
|
|
&ci->bus_qos_req,
|
|
FREQ_QOS_MIN,
|
|
FREQ_QOS_MIN_DEFAULT_VALUE);
|
|
if (ret < 0) {
|
|
dev_err(dev, "failed to add cpu bus freq constraint\n");
|
|
goto error;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
|
|
error:
|
|
rockchip_cpufreq_remove_bus_qos(cluster);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int rockchip_cpufreq_notifier(struct notifier_block *nb,
|
|
unsigned long event, void *data)
|
|
{
|
|
struct cpufreq_policy *policy = data;
|
|
struct cluster_info *cluster;
|
|
|
|
cluster = rockchip_cluster_info_lookup(policy->cpu);
|
|
if (!cluster)
|
|
return NOTIFY_BAD;
|
|
|
|
if (event == CPUFREQ_CREATE_POLICY) {
|
|
if (rockchip_cpufreq_add_monitor(cluster, policy))
|
|
return NOTIFY_BAD;
|
|
if (rockchip_cpufreq_add_bus_qos_req(cluster, policy))
|
|
return NOTIFY_BAD;
|
|
} else if (event == CPUFREQ_REMOVE_POLICY) {
|
|
rockchip_cpufreq_remove_monitor(cluster);
|
|
rockchip_cpufreq_remove_bus_qos(cluster);
|
|
}
|
|
|
|
return NOTIFY_OK;
|
|
}
|
|
|
|
static struct notifier_block rockchip_cpufreq_notifier_block = {
|
|
.notifier_call = rockchip_cpufreq_notifier,
|
|
};
|
|
|
|
#ifdef MODULE
|
|
static struct pm_qos_request idle_pm_qos;
|
|
static int idle_disable_refcnt;
|
|
static DEFINE_MUTEX(idle_disable_lock);
|
|
|
|
static int rockchip_cpufreq_idle_state_disable(struct cpumask *cpumask,
|
|
int index, bool disable)
|
|
{
|
|
mutex_lock(&idle_disable_lock);
|
|
|
|
if (disable) {
|
|
if (idle_disable_refcnt == 0)
|
|
cpu_latency_qos_update_request(&idle_pm_qos, 0);
|
|
idle_disable_refcnt++;
|
|
} else {
|
|
if (--idle_disable_refcnt == 0)
|
|
cpu_latency_qos_update_request(&idle_pm_qos,
|
|
PM_QOS_DEFAULT_VALUE);
|
|
}
|
|
|
|
mutex_unlock(&idle_disable_lock);
|
|
|
|
return 0;
|
|
}
|
|
#else
|
|
static int rockchip_cpufreq_idle_state_disable(struct cpumask *cpumask,
|
|
int index, bool disable)
|
|
{
|
|
unsigned int cpu;
|
|
|
|
for_each_cpu(cpu, cpumask) {
|
|
struct cpuidle_device *dev = per_cpu(cpuidle_devices, cpu);
|
|
struct cpuidle_driver *drv = cpuidle_get_cpu_driver(dev);
|
|
|
|
if (!dev || !drv)
|
|
continue;
|
|
if (index >= drv->state_count)
|
|
continue;
|
|
cpuidle_driver_state_disabled(drv, index, disable);
|
|
}
|
|
|
|
if (disable) {
|
|
preempt_disable();
|
|
for_each_cpu(cpu, cpumask) {
|
|
if (cpu != smp_processor_id() && cpu_online(cpu))
|
|
wake_up_if_idle(cpu);
|
|
}
|
|
preempt_enable();
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
#define cpu_to_bus_freq(freq) ((freq) * 4 / 5)
|
|
|
|
static int rockchip_cpufreq_update_bus_req(struct cluster_info *cluster,
|
|
unsigned int freq)
|
|
{
|
|
struct device *dev = cluster->opp_info.dev;
|
|
unsigned int bus_freq = 0;
|
|
|
|
if (cluster->is_opp_shared_cpu_bus ||
|
|
!freq_qos_request_active(&cluster->bus_qos_req))
|
|
return 0;
|
|
|
|
if (cluster->cpu_freq_percent)
|
|
bus_freq = rounddown(freq * cluster->cpu_freq_percent / 100, 100000);
|
|
else
|
|
bus_freq = rounddown(cpu_to_bus_freq(freq), 100000);
|
|
|
|
dev_dbg(dev, "cpu to bus: %u -> %u\n", freq, bus_freq);
|
|
|
|
return freq_qos_update_request(&cluster->bus_qos_req, bus_freq);
|
|
}
|
|
|
|
static int rockchip_cpufreq_transition_notifier(struct notifier_block *nb,
|
|
unsigned long event, void *data)
|
|
{
|
|
struct cpufreq_freqs *freqs = data;
|
|
struct cpufreq_policy *policy = freqs->policy;
|
|
struct cluster_info *cluster;
|
|
|
|
cluster = rockchip_cluster_info_lookup(policy->cpu);
|
|
if (!cluster)
|
|
return NOTIFY_BAD;
|
|
|
|
if (event == CPUFREQ_PRECHANGE) {
|
|
if (cluster->idle_threshold_freq &&
|
|
freqs->new >= cluster->idle_threshold_freq &&
|
|
!cluster->is_idle_disabled) {
|
|
rockchip_cpufreq_idle_state_disable(policy->cpus, 1,
|
|
true);
|
|
cluster->is_idle_disabled = true;
|
|
}
|
|
} else if (event == CPUFREQ_POSTCHANGE) {
|
|
if (cluster->idle_threshold_freq &&
|
|
freqs->new < cluster->idle_threshold_freq &&
|
|
cluster->is_idle_disabled) {
|
|
rockchip_cpufreq_idle_state_disable(policy->cpus, 1,
|
|
false);
|
|
cluster->is_idle_disabled = false;
|
|
}
|
|
rockchip_cpufreq_update_bus_req(cluster, freqs->new);
|
|
}
|
|
|
|
return NOTIFY_OK;
|
|
}
|
|
|
|
static struct notifier_block rockchip_cpufreq_transition_notifier_block = {
|
|
.notifier_call = rockchip_cpufreq_transition_notifier,
|
|
};
|
|
|
|
static int rockchip_cpufreq_panic_notifier(struct notifier_block *nb,
|
|
unsigned long v, void *p)
|
|
{
|
|
struct cluster_info *ci;
|
|
struct rockchip_opp_info *opp_info;
|
|
|
|
list_for_each_entry(ci, &cluster_info_list, list_head) {
|
|
opp_info = &ci->opp_info;
|
|
|
|
if (opp_info->regulator_count > 1)
|
|
dev_info(opp_info->dev,
|
|
"cur_freq: %lu Hz, volt_vdd: %lu uV, volt_mem: %lu uV\n",
|
|
ci->rate, ci->volt, ci->mem_volt);
|
|
else
|
|
dev_info(opp_info->dev, "cur_freq: %lu Hz, volt: %lu uV\n",
|
|
ci->rate, ci->volt);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct notifier_block rockchip_cpufreq_panic_notifier_block = {
|
|
.notifier_call = rockchip_cpufreq_panic_notifier,
|
|
};
|
|
|
|
static int __init rockchip_cpufreq_driver_init(void)
|
|
{
|
|
struct cluster_info *cluster, *pos;
|
|
struct cpufreq_dt_platform_data pdata = {0};
|
|
int cpu, ret;
|
|
bool is_opp_shared_cpu_bus = false;
|
|
|
|
for_each_possible_cpu(cpu) {
|
|
cluster = rockchip_cluster_info_lookup(cpu);
|
|
if (cluster)
|
|
continue;
|
|
|
|
cluster = kzalloc(sizeof(*cluster), GFP_KERNEL);
|
|
if (!cluster) {
|
|
ret = -ENOMEM;
|
|
goto release_cluster_info;
|
|
}
|
|
|
|
ret = rockchip_cpufreq_cluster_init(cpu, cluster);
|
|
if (ret) {
|
|
pr_err("Failed to initialize dvfs info cpu%d\n", cpu);
|
|
goto release_cluster_info;
|
|
}
|
|
list_add(&cluster->list_head, &cluster_info_list);
|
|
if (cluster->is_opp_shared_cpu_bus)
|
|
is_opp_shared_cpu_bus = true;
|
|
}
|
|
|
|
pdata.have_governor_per_policy = true;
|
|
pdata.suspend = rockchip_cpufreq_suspend;
|
|
|
|
ret = cpufreq_register_notifier(&rockchip_cpufreq_notifier_block,
|
|
CPUFREQ_POLICY_NOTIFIER);
|
|
if (ret) {
|
|
pr_err("failed to register cpufreq notifier\n");
|
|
goto release_cluster_info;
|
|
}
|
|
|
|
if (is_opp_shared_cpu_bus) {
|
|
ret = cpufreq_register_notifier(&rockchip_cpufreq_transition_notifier_block,
|
|
CPUFREQ_TRANSITION_NOTIFIER);
|
|
if (ret) {
|
|
cpufreq_unregister_notifier(&rockchip_cpufreq_notifier_block,
|
|
CPUFREQ_POLICY_NOTIFIER);
|
|
pr_err("failed to register cpufreq notifier\n");
|
|
goto release_cluster_info;
|
|
}
|
|
#ifdef MODULE
|
|
cpu_latency_qos_add_request(&idle_pm_qos, PM_QOS_DEFAULT_VALUE);
|
|
#endif
|
|
}
|
|
|
|
ret = atomic_notifier_chain_register(&panic_notifier_list,
|
|
&rockchip_cpufreq_panic_notifier_block);
|
|
if (ret)
|
|
pr_err("failed to register cpufreq panic notifier\n");
|
|
|
|
return PTR_ERR_OR_ZERO(platform_device_register_data(NULL, "cpufreq-dt",
|
|
-1, (void *)&pdata,
|
|
sizeof(struct cpufreq_dt_platform_data)));
|
|
|
|
release_cluster_info:
|
|
list_for_each_entry_safe(cluster, pos, &cluster_info_list, list_head) {
|
|
list_del(&cluster->list_head);
|
|
kfree(cluster);
|
|
}
|
|
return ret;
|
|
}
|
|
module_init(rockchip_cpufreq_driver_init);
|
|
|
|
MODULE_AUTHOR("Finley Xiao <finley.xiao@rock-chips.com>");
|
|
MODULE_DESCRIPTION("Rockchip cpufreq driver");
|
|
MODULE_LICENSE("GPL v2");
|