401 lines
11 KiB
C
401 lines
11 KiB
C
/*
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* Copyright (c) 2017 Rockchip Electronics Co., Ltd.
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*
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* Base on code in drivers/clk/clk-composite.c.
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* See clk-composite.c for further copyright information.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "clk-regmap.h"
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struct clk_regmap_composite {
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struct device *dev;
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struct clk_hw hw;
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struct clk_ops ops;
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struct clk_hw *mux_hw;
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struct clk_hw *rate_hw;
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struct clk_hw *gate_hw;
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const struct clk_ops *mux_ops;
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const struct clk_ops *rate_ops;
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const struct clk_ops *gate_ops;
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};
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#define to_clk_regmap_composite(_hw) \
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container_of(_hw, struct clk_regmap_composite, hw)
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static u8 clk_regmap_composite_get_parent(struct clk_hw *hw)
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{
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struct clk_regmap_composite *composite = to_clk_regmap_composite(hw);
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const struct clk_ops *mux_ops = composite->mux_ops;
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struct clk_hw *mux_hw = composite->mux_hw;
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__clk_hw_set_clk(mux_hw, hw);
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return mux_ops->get_parent(mux_hw);
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}
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static int clk_regmap_composite_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clk_regmap_composite *composite = to_clk_regmap_composite(hw);
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const struct clk_ops *mux_ops = composite->mux_ops;
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struct clk_hw *mux_hw = composite->mux_hw;
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__clk_hw_set_clk(mux_hw, hw);
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return mux_ops->set_parent(mux_hw, index);
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}
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static unsigned long clk_regmap_composite_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_regmap_composite *composite = to_clk_regmap_composite(hw);
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const struct clk_ops *rate_ops = composite->rate_ops;
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struct clk_hw *rate_hw = composite->rate_hw;
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__clk_hw_set_clk(rate_hw, hw);
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return rate_ops->recalc_rate(rate_hw, parent_rate);
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}
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static int clk_regmap_composite_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct clk_regmap_composite *composite = to_clk_regmap_composite(hw);
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const struct clk_ops *rate_ops = composite->rate_ops;
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const struct clk_ops *mux_ops = composite->mux_ops;
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struct clk_hw *rate_hw = composite->rate_hw;
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struct clk_hw *mux_hw = composite->mux_hw;
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struct clk_hw *parent;
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unsigned long parent_rate;
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long tmp_rate, best_rate = 0;
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unsigned long rate_diff;
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unsigned long best_rate_diff = ULONG_MAX;
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long rate;
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unsigned int i;
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if (rate_hw && rate_ops && rate_ops->determine_rate) {
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__clk_hw_set_clk(rate_hw, hw);
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return rate_ops->determine_rate(rate_hw, req);
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} else if (rate_hw && rate_ops && rate_ops->round_rate &&
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mux_hw && mux_ops && mux_ops->set_parent) {
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req->best_parent_hw = NULL;
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if (clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT) {
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parent = clk_hw_get_parent(mux_hw);
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req->best_parent_hw = parent;
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req->best_parent_rate = clk_hw_get_rate(parent);
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rate = rate_ops->round_rate(rate_hw, req->rate,
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&req->best_parent_rate);
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if (rate < 0)
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return rate;
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req->rate = rate;
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return 0;
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}
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for (i = 0; i < clk_hw_get_num_parents(mux_hw); i++) {
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parent = clk_hw_get_parent_by_index(mux_hw, i);
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if (!parent)
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continue;
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parent_rate = clk_hw_get_rate(parent);
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tmp_rate = rate_ops->round_rate(rate_hw, req->rate,
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&parent_rate);
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if (tmp_rate < 0)
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continue;
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rate_diff = abs(req->rate - tmp_rate);
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if (!rate_diff || !req->best_parent_hw ||
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best_rate_diff > rate_diff) {
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req->best_parent_hw = parent;
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req->best_parent_rate = parent_rate;
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best_rate_diff = rate_diff;
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best_rate = tmp_rate;
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}
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if (!rate_diff)
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return 0;
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}
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req->rate = best_rate;
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return 0;
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} else if (mux_hw && mux_ops && mux_ops->determine_rate) {
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__clk_hw_set_clk(mux_hw, hw);
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return mux_ops->determine_rate(mux_hw, req);
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} else {
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return -EINVAL;
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}
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return 0;
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}
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static long clk_regmap_composite_round_rate(struct clk_hw *hw,
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unsigned long rate,
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unsigned long *prate)
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{
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struct clk_regmap_composite *composite = to_clk_regmap_composite(hw);
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const struct clk_ops *rate_ops = composite->rate_ops;
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struct clk_hw *rate_hw = composite->rate_hw;
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__clk_hw_set_clk(rate_hw, hw);
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return rate_ops->round_rate(rate_hw, rate, prate);
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}
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static int clk_regmap_composite_set_rate(struct clk_hw *hw,
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unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_regmap_composite *composite = to_clk_regmap_composite(hw);
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const struct clk_ops *rate_ops = composite->rate_ops;
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struct clk_hw *rate_hw = composite->rate_hw;
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__clk_hw_set_clk(rate_hw, hw);
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return rate_ops->set_rate(rate_hw, rate, parent_rate);
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}
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static int clk_regmap_composite_is_prepared(struct clk_hw *hw)
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{
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struct clk_regmap_composite *composite = to_clk_regmap_composite(hw);
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const struct clk_ops *gate_ops = composite->gate_ops;
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struct clk_hw *gate_hw = composite->gate_hw;
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__clk_hw_set_clk(gate_hw, hw);
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return gate_ops->is_prepared(gate_hw);
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}
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static int clk_regmap_composite_prepare(struct clk_hw *hw)
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{
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struct clk_regmap_composite *composite = to_clk_regmap_composite(hw);
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const struct clk_ops *gate_ops = composite->gate_ops;
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struct clk_hw *gate_hw = composite->gate_hw;
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__clk_hw_set_clk(gate_hw, hw);
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return gate_ops->prepare(gate_hw);
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}
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static void clk_regmap_composite_unprepare(struct clk_hw *hw)
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{
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struct clk_regmap_composite *composite = to_clk_regmap_composite(hw);
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const struct clk_ops *gate_ops = composite->gate_ops;
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struct clk_hw *gate_hw = composite->gate_hw;
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__clk_hw_set_clk(gate_hw, hw);
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gate_ops->unprepare(gate_hw);
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}
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struct clk *
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devm_clk_regmap_register_composite(struct device *dev, const char *name,
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const char *const *parent_names,
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u8 num_parents, struct regmap *regmap,
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u32 mux_reg, u8 mux_shift, u8 mux_width,
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u32 div_reg, u8 div_shift, u8 div_width,
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u8 div_flags,
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u32 gate_reg, u8 gate_shift,
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unsigned long flags)
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{
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struct clk_regmap_gate *gate = NULL;
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struct clk_regmap_mux *mux = NULL;
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struct clk_regmap_divider *div = NULL;
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struct clk_regmap_fractional_divider *fd = NULL;
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const struct clk_ops *mux_ops = NULL, *div_ops = NULL, *gate_ops = NULL;
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const struct clk_ops *fd_ops = NULL;
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struct clk_hw *mux_hw = NULL, *div_hw = NULL, *gate_hw = NULL;
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struct clk_hw *fd_hw = NULL;
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struct clk *clk;
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struct clk_init_data init = {};
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struct clk_regmap_composite *composite;
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struct clk_ops *clk_composite_ops;
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if (num_parents > 1) {
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mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
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if (!mux)
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return ERR_PTR(-ENOMEM);
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mux->dev = dev;
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mux->regmap = regmap;
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mux->reg = mux_reg;
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mux->shift = mux_shift;
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mux->mask = BIT(mux_width) - 1;
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mux_ops = &clk_regmap_mux_ops;
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mux_hw = &mux->hw;
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}
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if (gate_reg > 0) {
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gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL);
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if (!gate)
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return ERR_PTR(-ENOMEM);
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gate->dev = dev;
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gate->regmap = regmap;
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gate->reg = gate_reg;
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gate->shift = gate_shift;
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gate_ops = &clk_regmap_gate_ops;
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gate_hw = &gate->hw;
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}
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if (div_reg > 0) {
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if (div_flags & CLK_DIVIDER_HIWORD_MASK) {
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div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
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if (!div)
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return ERR_PTR(-ENOMEM);
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div->dev = dev;
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div->regmap = regmap;
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div->reg = div_reg;
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div->shift = div_shift;
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div->width = div_width;
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div_ops = &clk_regmap_divider_ops;
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div_hw = &div->hw;
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} else {
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fd = devm_kzalloc(dev, sizeof(*fd), GFP_KERNEL);
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if (!fd)
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return ERR_PTR(-ENOMEM);
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fd->dev = dev;
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fd->regmap = regmap;
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fd->reg = div_reg;
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fd->mshift = 16;
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fd->mwidth = 16;
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fd->mmask = GENMASK(fd->mwidth - 1, 0) << fd->mshift;
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fd->nshift = 0;
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fd->nwidth = 16;
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fd->nmask = GENMASK(fd->nwidth - 1, 0) << fd->nshift;
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fd_ops = &clk_regmap_fractional_divider_ops;
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fd_hw = &fd->hw;
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}
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}
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composite = devm_kzalloc(dev, sizeof(*composite), GFP_KERNEL);
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if (!composite)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.flags = flags;
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init.parent_names = parent_names;
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init.num_parents = num_parents;
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clk_composite_ops = &composite->ops;
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if (mux_hw && mux_ops) {
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if (!mux_ops->get_parent)
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return ERR_PTR(-EINVAL);
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composite->mux_hw = mux_hw;
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composite->mux_ops = mux_ops;
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clk_composite_ops->get_parent =
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clk_regmap_composite_get_parent;
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if (mux_ops->set_parent)
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clk_composite_ops->set_parent =
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clk_regmap_composite_set_parent;
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if (mux_ops->determine_rate)
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clk_composite_ops->determine_rate =
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clk_regmap_composite_determine_rate;
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}
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if (div_hw && div_ops) {
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if (!div_ops->recalc_rate)
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return ERR_PTR(-EINVAL);
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clk_composite_ops->recalc_rate =
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clk_regmap_composite_recalc_rate;
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if (div_ops->determine_rate)
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clk_composite_ops->determine_rate =
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clk_regmap_composite_determine_rate;
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else if (div_ops->round_rate)
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clk_composite_ops->round_rate =
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clk_regmap_composite_round_rate;
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/* .set_rate requires either .round_rate or .determine_rate */
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if (div_ops->set_rate) {
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if (div_ops->determine_rate || div_ops->round_rate)
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clk_composite_ops->set_rate =
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clk_regmap_composite_set_rate;
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else
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WARN(1, "missing round_rate op\n");
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}
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composite->rate_hw = div_hw;
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composite->rate_ops = div_ops;
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}
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if (fd_hw && fd_ops) {
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if (!fd_ops->recalc_rate)
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return ERR_PTR(-EINVAL);
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clk_composite_ops->recalc_rate =
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clk_regmap_composite_recalc_rate;
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if (fd_ops->determine_rate)
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clk_composite_ops->determine_rate =
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clk_regmap_composite_determine_rate;
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else if (fd_ops->round_rate)
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clk_composite_ops->round_rate =
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clk_regmap_composite_round_rate;
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/* .set_rate requires either .round_rate or .determine_rate */
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if (fd_ops->set_rate) {
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if (fd_ops->determine_rate || fd_ops->round_rate)
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clk_composite_ops->set_rate =
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clk_regmap_composite_set_rate;
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else
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WARN(1, "missing round_rate op\n");
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}
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composite->rate_hw = fd_hw;
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composite->rate_ops = fd_ops;
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}
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if (gate_hw && gate_ops) {
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if (!gate_ops->is_prepared || !gate_ops->prepare ||
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!gate_ops->unprepare)
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return ERR_PTR(-EINVAL);
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composite->gate_hw = gate_hw;
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composite->gate_ops = gate_ops;
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clk_composite_ops->is_prepared =
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clk_regmap_composite_is_prepared;
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clk_composite_ops->prepare = clk_regmap_composite_prepare;
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clk_composite_ops->unprepare = clk_regmap_composite_unprepare;
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}
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init.ops = clk_composite_ops;
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composite->dev = dev;
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composite->hw.init = &init;
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clk = devm_clk_register(dev, &composite->hw);
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if (IS_ERR(clk))
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return clk;
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if (composite->mux_hw)
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composite->mux_hw->clk = clk;
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if (composite->rate_hw)
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composite->rate_hw->clk = clk;
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if (composite->gate_hw)
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composite->gate_hw->clk = clk;
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return clk;
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}
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EXPORT_SYMBOL_GPL(devm_clk_regmap_register_composite);
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