281 lines
6.9 KiB
C
281 lines
6.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* arch/arm/mach-mv78xx0/pcie.c
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*
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* PCIe functions for Marvell MV78xx0 SoCs
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/mbus.h>
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#include <video/vga.h>
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#include <asm/irq.h>
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#include <asm/mach/pci.h>
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#include <plat/pcie.h>
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#include "mv78xx0.h"
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#include "common.h"
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#define MV78XX0_MBUS_PCIE_MEM_TARGET(port, lane) ((port) ? 8 : 4)
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#define MV78XX0_MBUS_PCIE_MEM_ATTR(port, lane) (0xf8 & ~(0x10 << (lane)))
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#define MV78XX0_MBUS_PCIE_IO_TARGET(port, lane) ((port) ? 8 : 4)
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#define MV78XX0_MBUS_PCIE_IO_ATTR(port, lane) (0xf0 & ~(0x10 << (lane)))
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struct pcie_port {
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u8 maj;
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u8 min;
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u8 root_bus_nr;
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void __iomem *base;
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spinlock_t conf_lock;
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char mem_space_name[20];
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struct resource res;
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};
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static struct pcie_port pcie_port[8];
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static int num_pcie_ports;
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static struct resource pcie_io_space;
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void __init mv78xx0_pcie_id(u32 *dev, u32 *rev)
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{
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*dev = orion_pcie_dev_id(PCIE00_VIRT_BASE);
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*rev = orion_pcie_rev(PCIE00_VIRT_BASE);
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}
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u32 pcie_port_size[8] = {
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0,
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0x30000000,
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0x10000000,
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0x10000000,
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0x08000000,
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0x08000000,
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0x08000000,
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0x04000000,
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};
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static void __init mv78xx0_pcie_preinit(void)
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{
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int i;
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u32 size_each;
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u32 start;
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pcie_io_space.name = "PCIe I/O Space";
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pcie_io_space.start = MV78XX0_PCIE_IO_PHYS_BASE(0);
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pcie_io_space.end =
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MV78XX0_PCIE_IO_PHYS_BASE(0) + MV78XX0_PCIE_IO_SIZE * 8 - 1;
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pcie_io_space.flags = IORESOURCE_MEM;
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if (request_resource(&iomem_resource, &pcie_io_space))
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panic("can't allocate PCIe I/O space");
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if (num_pcie_ports > 7)
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panic("invalid number of PCIe ports");
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size_each = pcie_port_size[num_pcie_ports];
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start = MV78XX0_PCIE_MEM_PHYS_BASE;
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for (i = 0; i < num_pcie_ports; i++) {
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struct pcie_port *pp = pcie_port + i;
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snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
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"PCIe %d.%d MEM", pp->maj, pp->min);
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pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
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pp->res.name = pp->mem_space_name;
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pp->res.flags = IORESOURCE_MEM;
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pp->res.start = start;
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pp->res.end = start + size_each - 1;
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start += size_each;
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if (request_resource(&iomem_resource, &pp->res))
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panic("can't allocate PCIe MEM sub-space");
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mvebu_mbus_add_window_by_id(MV78XX0_MBUS_PCIE_MEM_TARGET(pp->maj, pp->min),
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MV78XX0_MBUS_PCIE_MEM_ATTR(pp->maj, pp->min),
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pp->res.start, resource_size(&pp->res));
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mvebu_mbus_add_window_remap_by_id(MV78XX0_MBUS_PCIE_IO_TARGET(pp->maj, pp->min),
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MV78XX0_MBUS_PCIE_IO_ATTR(pp->maj, pp->min),
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i * SZ_64K, SZ_64K, 0);
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}
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}
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static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys)
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{
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struct pcie_port *pp;
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struct resource realio;
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if (nr >= num_pcie_ports)
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return 0;
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pp = &pcie_port[nr];
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sys->private_data = pp;
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pp->root_bus_nr = sys->busnr;
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/*
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* Generic PCIe unit setup.
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*/
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orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
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orion_pcie_setup(pp->base);
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realio.start = nr * SZ_64K;
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realio.end = realio.start + SZ_64K - 1;
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pci_remap_iospace(&realio, MV78XX0_PCIE_IO_PHYS_BASE(nr));
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pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
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return 1;
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}
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static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
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{
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/*
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* Don't go out when trying to access nonexisting devices
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* on the local bus.
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*/
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if (bus == pp->root_bus_nr && dev > 1)
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return 0;
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return 1;
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}
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static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
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int size, u32 *val)
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{
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struct pci_sys_data *sys = bus->sysdata;
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struct pcie_port *pp = sys->private_data;
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unsigned long flags;
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int ret;
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if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
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*val = 0xffffffff;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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spin_lock_irqsave(&pp->conf_lock, flags);
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ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
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spin_unlock_irqrestore(&pp->conf_lock, flags);
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return ret;
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}
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static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
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int where, int size, u32 val)
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{
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struct pci_sys_data *sys = bus->sysdata;
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struct pcie_port *pp = sys->private_data;
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unsigned long flags;
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int ret;
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if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
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return PCIBIOS_DEVICE_NOT_FOUND;
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spin_lock_irqsave(&pp->conf_lock, flags);
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ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
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spin_unlock_irqrestore(&pp->conf_lock, flags);
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return ret;
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}
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static struct pci_ops pcie_ops = {
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.read = pcie_rd_conf,
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.write = pcie_wr_conf,
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};
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/*
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* The root complex has a hardwired class of PCI_CLASS_MEMORY_OTHER, when it
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* is operating as a root complex this needs to be switched to
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* PCI_CLASS_BRIDGE_HOST or Linux will errantly try to process the BAR's on
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* the device. Decoding setup is handled by the orion code.
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*/
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static void rc_pci_fixup(struct pci_dev *dev)
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{
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if (dev->bus->parent == NULL && dev->devfn == 0) {
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int i;
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dev->class &= 0xff;
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dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
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for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
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dev->resource[i].start = 0;
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dev->resource[i].end = 0;
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dev->resource[i].flags = 0;
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}
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
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static int __init mv78xx0_pcie_scan_bus(int nr, struct pci_host_bridge *bridge)
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{
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struct pci_sys_data *sys = pci_host_bridge_priv(bridge);
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if (nr >= num_pcie_ports) {
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BUG();
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return -EINVAL;
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}
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list_splice_init(&sys->resources, &bridge->windows);
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bridge->dev.parent = NULL;
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bridge->sysdata = sys;
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bridge->busnr = sys->busnr;
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bridge->ops = &pcie_ops;
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return pci_scan_root_bus_bridge(bridge);
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}
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static int __init mv78xx0_pcie_map_irq(const struct pci_dev *dev, u8 slot,
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u8 pin)
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{
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struct pci_sys_data *sys = dev->bus->sysdata;
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struct pcie_port *pp = sys->private_data;
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return IRQ_MV78XX0_PCIE_00 + (pp->maj << 2) + pp->min;
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}
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static struct hw_pci mv78xx0_pci __initdata = {
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.nr_controllers = 8,
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.preinit = mv78xx0_pcie_preinit,
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.setup = mv78xx0_pcie_setup,
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.scan = mv78xx0_pcie_scan_bus,
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.map_irq = mv78xx0_pcie_map_irq,
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};
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static void __init add_pcie_port(int maj, int min, void __iomem *base)
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{
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printk(KERN_INFO "MV78xx0 PCIe port %d.%d: ", maj, min);
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if (orion_pcie_link_up(base)) {
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struct pcie_port *pp = &pcie_port[num_pcie_ports++];
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printk("link up\n");
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pp->maj = maj;
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pp->min = min;
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pp->root_bus_nr = -1;
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pp->base = base;
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spin_lock_init(&pp->conf_lock);
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memset(&pp->res, 0, sizeof(pp->res));
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} else {
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printk("link down, ignoring\n");
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}
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}
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void __init mv78xx0_pcie_init(int init_port0, int init_port1)
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{
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vga_base = MV78XX0_PCIE_MEM_PHYS_BASE;
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if (init_port0) {
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add_pcie_port(0, 0, PCIE00_VIRT_BASE);
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if (!orion_pcie_x4_mode(PCIE00_VIRT_BASE)) {
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add_pcie_port(0, 1, PCIE01_VIRT_BASE);
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add_pcie_port(0, 2, PCIE02_VIRT_BASE);
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add_pcie_port(0, 3, PCIE03_VIRT_BASE);
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}
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}
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if (init_port1) {
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add_pcie_port(1, 0, PCIE10_VIRT_BASE);
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if (!orion_pcie_x4_mode((void __iomem *)PCIE10_VIRT_BASE)) {
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add_pcie_port(1, 1, PCIE11_VIRT_BASE);
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add_pcie_port(1, 2, PCIE12_VIRT_BASE);
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add_pcie_port(1, 3, PCIE13_VIRT_BASE);
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}
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}
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pci_common_init(&mv78xx0_pci);
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}
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