// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
 */

#include <dt-bindings/display/media-bus-format.h>

/ {
	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		linux,cma {
			compatible = "shared-dma-pool";
			inactive;
			reusable;
			size = <0x1000000>;
			linux,cma-default;
		};
	};
};

&display_subsystem {
	status = "okay";
};

&i2c0 {
	clock-frequency = <400000>;
	status = "okay";

	sii9022: sii9022@39 {
		compatible = "sil,sii9022";
		reg = <0x39>;
		pinctrl-names = "default";
		pinctrl-0 = <&sii902x_hdmi_int>;
		interrupt-parent = <&gpio1>;
		interrupts = <RK_PB1 IRQ_TYPE_LEVEL_HIGH>;
		reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
		enable-gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
		bus-format = <MEDIA_BUS_FMT_RGB666_1X18>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;

				sii9022_in_rgb: endpoint {
					remote-endpoint = <&rgb_out_sii9022>;
				};
			};
		};
	};
};

&pinctrl {
	sii902x {
		sii902x_hdmi_int: sii902x-hdmi-int {
			rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
		};
	};
};

&rgb {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&lcd_pins>;

	ports {
		port@1 {
			reg = <1>;
			#address-cells = <1>;
			#size-cells = <0>;

			rgb_out_sii9022: endpoint@0 {
				reg = <0>;
				remote-endpoint = <&sii9022_in_rgb>;
			};
		};
	};
};

&rgb_in_vop {
	status = "okay";
};

/*
 * The pins of sdmmc1 and lcd are multiplexed
 */
&sdio {
	status = "disabled";
};

&sdio_pwrseq {
	status = "disabled";
};

&vop {
	status = "okay";
};