/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2023 Rockchip Electronics Co., Ltd. * * Author: Joseph Chen */ #ifndef _CRU_RKX111_H #include "cru_rkx110.h" // RXCRU_SOFTRST_CON02(Offset:0x408) #define RKX111_SRST_DRESETN_VICAP_CSI_LS 0x0000002E // RXCRU_SOFTRST_CON05(Offset:0x414) #define RKX111_SRST_RESETN_D_DSI_0_REC_RKLINK_TX 0x00000056 #define RKX111_SRST_RESETN_D_DSI_1_REC_RKLINK_TX 0x00000057 // RXCRU_SOFTRST_CON06(Offset:0x418) #define RKX111_SRST_RESETN_D_LVDS0_PATTERN_GEN 0x00000066 #define RKX111_SRST_RESETN_D_LVDS1_PATTERN_GEN 0x00000067 // RXCRU_SOFTRST_CON11(Offset:0x42C) #define RKX111_SRST_PRESETN_LBIST_ADA_RX 0x000000B1 // RXCRU_GATE_CON02(Offset:0x308) #define RKX111_DCLK_RX_PRE_200M_GATE 0x0000002D #define RKX111_DCLK_VICAP_CSI_LS_GATE 0x0000002E // RXCRU_GATE_CON04(Offset:0x310) #define RKX111_CLK_D_DSI_0_RKLINK_TX_PRE_GATE 0x00000044 #define RKX111_CLK_D_DSI_1_RKLINK_TX_PRE_GATE 0x00000045 #define RKX111_CLK_D_LVDS0_RKLINK_TX_GATE 0x00000047 #define RKX111_CLK_D_LVDS0_RKLINK_TX_PRE_GATE 0x00000048 #define RKX111_CLK_D_LVDS1_RKLINK_TX_GATE 0x00000049 #define RKX111_CLK_D_LVDS1_RKLINK_TX_PRE_GATE 0x0000004A #define RKX111_DCLK_D_DSI_0_REC_GATE 0x0000004D #define RKX111_DCLK_D_DSI_1_REC_GATE 0x0000004E // RXCRU_GATE_CON05(Offset:0x314) #define RKX111_DCLK_D_DSI_0_REC_RKLINK_TX_GATE 0x00000056 #define RKX111_DCLK_D_DSI_1_REC_RKLINK_TX_GATE 0x00000057 #define RKX111_CLK_D_DSI_0_RKLINK_TX_GATE 0x00000058 #define RKX111_CLK_D_DSI_1_RKLINK_TX_GATE 0x00000059 // RXCRU_GATE_CON06(Offset:0x318) #define RKX111_CLK_D_LVDS0_PATTERN_GEN_GATE 0x00000066 #define RKX111_CLK_D_LVDS1_PATTERN_GEN_GATE 0x00000067 // RXCRU_GATE_CON11(Offset:0x32C) #define RKX111_PCLK_LBIST_ADA_RX_GATE 0x000000B1 // RXCRU_CLKSEL_CON05(Offset:0x114) #define RKX111_DCLK_D_DSI_0_REC_DIV 0x08000005 #define RKX111_DCLK_D_DSI_0_REC_SEL 0x020E0005 #define RKX111_DCLK_D_DSI_0_REC_SEL_CLK_RXPLL_MUX 0U #define RKX111_DCLK_D_DSI_0_REC_SEL_CLK_CPLL_MUX 1U #define RKX111_DCLK_D_DSI_0_REC_SEL_XIN_OSC0_FUNC 2U // RXCRU_CLKSEL_CON06(Offset:0x118) #define RKX111_DCLK_D_DSI_1_REC_DIV 0x08000006 #define RKX111_DCLK_D_DSI_1_REC_SEL 0x020E0006 #define RKX111_DCLK_D_DSI_1_REC_SEL_CLK_RXPLL_MUX 0U #define RKX111_DCLK_D_DSI_1_REC_SEL_CLK_CPLL_MUX 1U #define RKX111_DCLK_D_DSI_1_REC_SEL_XIN_OSC0_FUNC 2U // RXCRU_CLKSEL_CON13(Offset:0x134) #define RKX111_CLK_D_LVDS0_PATTERN_GEN_DIV 0x0800000D #define RKX111_CLK_D_LVDS0_PATTERN_GEN_SEL 0x020E000D #define RKX111_CLK_D_LVDS0_PATTERN_GEN_SEL_CLK_RXPLL_MUX 0U #define RKX111_CLK_D_LVDS0_PATTERN_GEN_SEL_CLK_CPLL_MUX 1U #define RKX111_CLK_D_LVDS0_PATTERN_GEN_SEL_XIN_OSC0_FUNC 2U // RXCRU_CLKSEL_CON14(Offset:0x138) #define RKX111_CLK_D_LVDS1_PATTERN_GEN_DIV 0x0800000E #define RKX111_CLK_D_LVDS1_PATTERN_GEN_SEL 0x020E000E #define RKX111_CLK_D_LVDS1_PATTERN_GEN_SEL_CLK_RXPLL_MUX 0U #define RKX111_CLK_D_LVDS1_PATTERN_GEN_SEL_CLK_CPLL_MUX 1U #define RKX111_CLK_D_LVDS1_PATTERN_GEN_SEL_XIN_OSC0_FUNC 2U // RXCRU_CLKSEL_CON16(Offset:0x140) #define RKX111_DCLK_RX_PRE_200M_DIV 0x06000010 #define RKX111_DCLK_RX_PRE_200M_SEL 0x02060010 #define RKX111_DCLK_RX_PRE_200M_SEL_CLK_RXPLL_MUX 0U #define RKX111_DCLK_RX_PRE_200M_SEL_CLK_CPLL_MUX 1U #define RKX111_DCLK_RX_PRE_200M_SEL_XIN_OSC0_FUNC 2U // RXCRU_CLKSEL_CON17(Offset:0x144) #define RKX111_CLK_D_DSI_0_RKLINK_TX_SEL 0x010C0011 #define RKX111_CLK_D_DSI_0_RKLINK_TX_SEL_CLK_D_DSI_0_RKLINK_TX_PRE 0U #define RKX111_CLK_D_DSI_0_RKLINK_TX_SEL_CLK_D_DSI_0_PATTERN_GEN 1U #define RKX111_CLK_D_DSI_1_RKLINK_TX_SEL 0x010D0011 #define RKX111_CLK_D_DSI_1_RKLINK_TX_SEL_CLK_D_DSI_1_RKLINK_TX_PRE 0U #define RKX111_CLK_D_DSI_1_RKLINK_TX_SEL_CLK_D_DSI_1_PATTERN_GEN 1U #define RKX111_CLK_D_LVDS0_RKLINK_TX_SEL 0x010E0011 #define RKX111_CLK_D_LVDS0_RKLINK_TX_SEL_CLK_D_LVDS0_RKLINK_TX_PRE 0U #define RKX111_CLK_D_LVDS0_RKLINK_TX_SEL_CLK_D_LVDS0_PATTERN_GEN 1U #define RKX111_CLK_D_LVDS1_RKLINK_TX_SEL 0x010F0011 #define RKX111_CLK_D_LVDS1_RKLINK_TX_SEL_CLK_D_LVDS1_RKLINK_TX_PRE 0U #define RKX111_CLK_D_LVDS1_RKLINK_TX_SEL_CLK_D_LVDS1_PATTERN_GEN 1U /* COMPOSITE */ #define RKX111_CPS_DCLK_RX_PRE_200M COMPOSITE_CLK(RKX111_DCLK_RX_PRE_200M_SEL, RKX111_DCLK_RX_PRE_200M_DIV) /* lvds_pattern_gen => lvds_rklink */ #define RKX111_CPS_CLK_D_LVDS0_PATTERN_GEN COMPOSITE_CLK(RKX111_CLK_D_LVDS0_PATTERN_GEN_SEL, RKX111_CLK_D_LVDS0_PATTERN_GEN_DIV) #define RKX111_CPS_CLK_D_LVDS1_PATTERN_GEN COMPOSITE_CLK(RKX111_CLK_D_LVDS1_PATTERN_GEN_SEL, RKX111_CLK_D_LVDS1_PATTERN_GEN_DIV) #define RKX111_CPS_CLK_D_LVDS0_RKLINK_TX COMPOSITE_CLK(RKX111_CLK_D_LVDS0_RKLINK_TX_SEL, 0) #define RKX111_CPS_CLK_D_LVDS1_RKLINK_TX COMPOSITE_CLK(RKX111_CLK_D_LVDS1_RKLINK_TX_SEL, 0) /* dsi_rec => dsi_rklink */ #define RKX111_CPS_DCLK_D_DSI_0_REC COMPOSITE_CLK(RKX111_DCLK_D_DSI_0_REC_SEL, RKX111_DCLK_D_DSI_0_REC_DIV) #define RKX111_CPS_DCLK_D_DSI_1_REC COMPOSITE_CLK(RKX111_DCLK_D_DSI_1_REC_SEL, RKX111_DCLK_D_DSI_1_REC_DIV) #define RKX111_CPS_CLK_D_DSI_0_RKLINK_TX COMPOSITE_CLK(RKX111_CLK_D_DSI_0_RKLINK_TX_SEL, 0) #define RKX111_CPS_CLK_D_DSI_1_RKLINK_TX COMPOSITE_CLK(RKX111_CLK_D_DSI_1_RKLINK_TX_SEL, 0) #endif