// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2024 Rockchip Electronics Co., Ltd. * */ / { dp2lvds_backlight0: dp2lvds_backlight0 { compatible = "pwm-backlight"; brightness-levels = < 0 20 20 21 21 22 22 23 23 24 24 25 25 26 26 27 27 28 28 29 29 30 30 31 31 32 32 33 33 34 34 35 35 36 36 37 37 38 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 >; default-brightness-level = <200>; }; dp2lvds_backlight1: dp2lvds_backlight1 { compatible = "pwm-backlight"; brightness-levels = < 0 20 20 21 21 22 22 23 23 24 24 25 25 26 26 27 27 28 28 29 29 30 30 31 31 32 32 33 33 34 34 35 35 36 36 37 37 38 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 >; default-brightness-level = <200>; }; edp2lvds_backlight0: edp2lvds_backlight0 { compatible = "pwm-backlight"; brightness-levels = < 0 20 20 21 21 22 22 23 23 24 24 25 25 26 26 27 27 28 28 29 29 30 30 31 31 32 32 33 33 34 34 35 35 36 36 37 37 38 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 >; default-brightness-level = <200>; }; dp_mst_sim: dp-mst-sim { compatible = "rockchip,dp-mst-sim"; }; }; &backlight { pwms = <&pwm1_6ch_1 0 25000 0>; //pinctrl-names = "default"; //pinctrl-0 = <&bl0_enable_pin>; //enable-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; status = "okay"; }; &combphy0_ps { status = "okay"; }; &combphy1_psu { status = "okay"; }; &dp { //split-mode; force-hpd; //pinctrl-names = "default"; //pinctrl-0 = <&i2c5_serdes_hpd_pins>; //hpd-gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_HIGH>; rockchip,mst-fixed-ports = <0 1 2>; rockchip,mst-sim = <&dp_mst_sim>; status = "okay"; }; &dp_mst_sim { mst-dp0 { display-timings { clock-frequency = <594000000>; hactive = <3840>; vactive = <2160>; hfront-porch = <176>; hsync-len = <88>; hback-porch = <296>; vfront-porch = <8>; vsync-len = <10>; vback-porch = <72>; hsync-active = <0>; vsync-active = <0>; de-active = <0>; pixelclk-active = <0>; }; }; mst-dp1 { display-timings { clock-frequency = <297000000>; hactive = <2560>; vactive = <1440>; hfront-porch = <100>; hsync-len = <20>; hback-porch = <200>; vfront-porch = <15>; vsync-len = <2>; vback-porch = <15>; hsync-active = <0>; vsync-active = <0>; de-active = <0>; pixelclk-active = <0>; }; }; }; &dp0 { status = "okay"; ports { port@2 { reg = <2>; dp0_out_i2c5_max96745: endpoint { link-frequencies = /bits/ 64 <5400000000>; remote-endpoint = <&i2c5_max96745_from_dp0>; }; }; }; }; &dp0_in_vp0 { status = "disabled"; }; &dp0_in_vp1 { status = "disabled"; }; &dp0_in_vp2 { status = "okay"; }; &dp2lvds_backlight0 { pwms = <&pwm2_8ch_0 0 25000 0>; //pinctrl-names = "default"; //pinctrl-0 = <&bl2_enable_pin>; //enable-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; status = "okay"; }; &dp1 { status = "okay"; ports { port@2 { reg = <2>; dp1_out_i2c5_max96745: endpoint { link-frequencies = /bits/ 64 <5400000000>; remote-endpoint = <&i2c5_max96745_from_dp1>; }; }; }; }; &dp1_in_vp0 { status = "okay"; }; &dp1_in_vp1 { status = "disabled"; }; &dp1_in_vp2 { status = "disabled"; }; &dp2lvds_backlight1 { pwms = <&pwm2_8ch_5 0 25000 0>; //pinctrl-names = "default"; //pinctrl-0 = <&bl4_enable_pin>; //enable-gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; status = "okay"; }; /* * mipi_dcphy needs to be enabled * when dsi is enabled */ &dsi { status = "okay"; ports { #address-cells = <1>; #size-cells = <0>; port@1 { reg = <1>; dsi_out_i2c8_max96789: endpoint { remote-endpoint = <&i2c8_max96789_from_dsi>; }; }; }; }; &dsi_in_vp0 { status = "disabled"; }; &dsi_in_vp1 { status = "okay"; }; &dsi_in_vp2 { status = "disabled"; }; #if 0 &edp { //split-mode; force-hpd; status = "okay"; ports { port@1 { reg = <1>; edp_out_i2c2_max96745: endpoint { remote-endpoint = <&i2c2_max96745_from_edp>; }; }; }; }; &edp_in_vp0 { status = "okay"; }; &edp_in_vp1 { status = "disabled"; }; &edp_in_vp2 { status = "disabled"; }; &edp2lvds_backlight0 { pwms = <&pwm2_8ch_5 0 25000 0>; //pinctrl-names = "default"; //pinctrl-0 = <&bl4_enable_pin>; //enable-gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; status = "okay"; }; #endif &hdmi { status = "disabled"; }; &hdptxphy { status = "okay"; }; &hdptxphy_hdmi { status = "disabled"; }; &i2c8 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&i2c8m2_xfer>; clock-frequency = <400000>; i2c8_max96789: i2c8-max96789@42 { compatible = "maxim,max96789"; reg = <0x42>; pinctrl-names = "default"; pinctrl-0 = <&i2c8_serdes_pins>; lock-gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; sel-mipi; id-serdes-bridge-split = <0x01>; status = "okay"; serdes-init-sequence = [ //Independent 11_07_17-56 Using MAX96789/91/F (GMSL-1/2) //Disable Video pipe 0002 0003 //Address Value of I2C SRC_A 0042 008a //Address Value of I2C DST_A 0043 008a //Address Value of I2C SRC_B 0044 008c //Address Value of I2C DST_B 0045 008c //Set Stream for DSI Port A && assign pipeX 0053 0010 //Set Stream for DSI Port B && assign pipeY 0057 0021 //Clock Select, X for portA, Y/Z for PortB 0308 0076 //Start DSI Port 0311 0061 //Set Port A Lane Mapping 0332 004E //Set Port B Lane Mapping 0333 00E4 //Set GMSL type 0004 00F2 //Number of Lanes 0331 0033 //Set phy_config 0330 0006 //Set soft_dtx_en 031C 0098 //Set soft_dtx 0321 0024 //Set soft_dty_en 031D 0098 //Set soft_dty_ 0322 0024 //Init Default 0326 00E4 //HSYNC_WIDTH_L 0385 0038 //VSYNC_WIDTH_L 0386 0008 //HSYNC_WIDTH_H/VSYNC_WIDTH_H 0387 0000 //VFP_L 03A5 00C8 //VBP_H 03A7 0000 //VFP_H/VBP_L 03A6 0020 //VRES_L 03A8 00D0 //VRES_H 03A9 0002 //HFP_L 03AA 0038 //HBP_H 03AC 0002 //HFP_H/HBP_L 03AB 0000 //HRES_L 03AD 0080 //HRES_H 03AE 0007 //Disable FIFO/DESKEW_EN 03A4 00C0 //HSYNC_WIDTH_L 0395 0038 //VSYNC_WIDTH_L 0396 0008 //HSYNC_WIDTH_H/VSYNC_WIDTH_H 0397 0000 //VFP_L 03B1 00C8 //VBP_H 03B3 0000 //VFP_H/VBP_L 03B2 0020 //VRES_L 03B4 00D0 //VRES_H 03B5 0002 //HFP_L 03B6 0038 //HBP_H 03B8 0002 //HFP_H/HBP_L 03B7 0000 //HRES_L 03B9 0080 //HRES_H 03BA 0007 //Disable FIFO/DESKEW_EN 03B0 00C0 //Turn on video pipe 0002 0033 //Enable splitter mode reset one shot 0010 0023 ffff f000 //0xf000 ms delay ]; i2c8_max96789_pinctrl: i2c8-max96789-pinctrl { compatible = "maxim,max96789-pinctrl"; pinctrl-names = "default","sleep"; pinctrl-0 = <&i2c8_max96789_pinctrl_pins>; pinctrl-1 = <&i2c8_max96789_pinctrl_pins>; status = "okay"; i2c8_max96789_pinctrl_pins: pinctrl-pins { i2c { groups = "MAX96789_I2C"; function = "MAX96789_I2C"; }; lcd-bl-pwm { pins = "MAX96789_MFP7"; function = "SER_TXID4_TO_DES"; }; tp-int { pins = "MAX96789_MFP8"; function = "DES_RXID8_TO_SER"; }; lcd-bl-pwm-split { pins = "MAX96789_MFP16"; function = "SER_TXID4_TO_DES"; }; tp-int-split { pins = "MAX96789_MFP14"; function = "DES_RXID14_TO_SER"; }; }; i2c8_max96789_gpio: i2c8-max96789-gpio { compatible = "maxim,max96789-gpio"; status = "okay"; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&i2c8_max96789_pinctrl 0 160 20>; }; }; i2c8_max96789_bridge: i2c8-max96789-bridge { compatible = "maxim,max96789-bridge"; status = "okay"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; i2c8_max96789_from_dsi: endpoint { remote-endpoint = <&dsi_out_i2c8_max96789>; }; }; port@1 { reg = <1>; i2c8_max96789_out_i2c8_max96752: endpoint { remote-endpoint = <&i2c8_max96752_from_i2c8_max96789>; }; }; }; }; }; i2c8_max96752: i2c8-max96752@4a { compatible = "maxim,max96752"; reg = <0x4a>; //reg-hw = <0x4a>; id-serdes-panel-split = <0x01>; link = <0x01>; status = "okay"; serdes-init-sequence = [ /*max96752 dual oLDI output*/ 0002 0043 0073 0031 007b 0031 007d 0038 //Address Value of I2C SRC_A 0042 008a //Address Value of I2C DST_A 0043 0090 0050 0000 01ce 004e 01ea 0004 ]; i2c8_max96752_pinctrl: i2c8-max96752-pinctrl { compatible = "maxim,max96752-pinctrl"; pinctrl-names = "default","init","sleep"; pinctrl-0 = <&i2c8_max96752_panel_pins>; pinctrl-1 = <&i2c8_max96752_panel_pins>; pinctrl-2 = <&i2c8_max96752_panel_sleep_pins>; status = "okay"; i2c8_max96752_panel_pins: panel-pins { lcd-rst-pin { pins = "MAX96752_GPIO10"; function = "DES_TXID10_OUTPUT_HIGH"; }; tp-rst { pins = "MAX96752_GPIO5"; function = "DES_TXID5_OUTPUT_HIGH"; }; lcd-bias-en { pins = "MAX96752_GPIO7"; function = "DES_TXID7_OUTPUT_HIGH"; }; lcd-vdd-en { pins = "MAX96752_GPIO6"; function = "DES_TXID6_OUTPUT_HIGH"; }; tp-int { pins = "MAX96752_GPIO2"; function = "DES_TXID8_TO_SER"; }; 40ms-delay { pins = "MAX96752_GPIO15"; function = "DELAY_40MS"; }; lcd-pwr-on { pins = "MAX96752_GPIO3"; function = "DES_TXID3_OUTPUT_HIGH"; }; lcd-bl-pwm { pins = "MAX96752_GPIO4"; function = "SER_TO_DES_RXID4"; }; }; i2c8_max96752_panel_sleep_pins: panel-sleep-pins { lcd-rst-pin { pins = "MAX96752_GPIO10"; function = "DES_TXID10_OUTPUT_LOW"; }; tp-rst { pins = "MAX96752_GPIO5"; function = "DES_TXID5_OUTPUT_LOW"; }; lcd-pwr-on { pins = "MAX96752_GPIO3"; function = "DES_TXID3_OUTPUT_LOW"; }; }; i2c8_max96752_gpio: i2c8-max96752-gpio { compatible = "maxim,max96752-gpio"; status = "okay"; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&i2c8_max96752_pinctrl 0 180 15>; }; }; i2c8_max96752_panel: i2c8-max96752-panel { compatible = "maxim,max96752-panel"; status = "okay"; backlight = <&backlight>; panel-size= <346 194>; panel-timing { clock-frequency = <115000000>; hactive = <1920>; vactive = <720>; hfront-porch = <56>; hsync-len = <32>; hback-porch = <56>; vfront-porch = <200>; vsync-len = <2>; vback-porch = <8>; hsync-active = <0>; vsync-active = <0>; de-active = <0>; pixelclk-active = <0>; }; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; i2c8_max96752_from_i2c8_max96789: endpoint { remote-endpoint = <&i2c8_max96789_out_i2c8_max96752>; }; }; }; }; }; himax@45 { compatible = "himax,hxcommon"; reg = <0x45>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&touch_gpio_dsi>; pinctrl-1 = <&touch_gpio_dsi>; himax,location = "himax-touch-dsi"; himax,irq-gpio = <&gpio3 RK_PA3 IRQ_TYPE_EDGE_FALLING>; himax,rst-gpio = <&i2c8_max96752_gpio 5 GPIO_ACTIVE_LOW>; himax,panel-coords = <0 1920 0 720>; himax,display-coords = <0 1920 0 720>; status = "okay"; }; }; &i2c5 { pinctrl-names = "default"; pinctrl-0 = <&i2c5m3_xfer>; clock-frequency = <400000>; status = "okay"; i2c5_max96745: i2c5-max96745@42 { compatible = "maxim,max96745"; reg = <0x42>; pinctrl-names = "default"; pinctrl-0 = <&i2c5_serdes_pins>; lock-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; #address-cells = <1>; #size-cells = <0>; id-serdes-bridge-split = <0x02>; status = "okay"; serdes-init-sequence = [ //Set pclks to run continuously 6421 000F //Enable MST mode on GM03 - DEBUG 7F11 0005 //Configure GM03 DP_RX Payload IDs //Set video payload ID 2 for video output port 0 on GM03 7904 0001 //Set video payload ID 1 for video output port 1 on GM03 7908 0002 //Turn off video 6420 0010 //Disable MST_VS0_DTG_ENABLE 7A14 0000 //Disable MST_VS1_DTG_ENABLE 7B14 0000 //Disable LINK_ENABLE 7000 0000 //Reset DPRX core (VIDEO_INPUT_RESET) 7054 0001 //delay 100 ffff f000 //Set MAX_LINK_RATE to 5.4Gb/s 7074 0014 //Set MAX_LINK_COUNT to 4 7070 0004 //delay 100 ffff f000 // VID_LINK_SEL_X of SER will be written 01 0100 0061 // VID_LINK_SEL_Y of SER will be written 01 0110 0063 //Enable LINK_ENABLE 7000 0001 //delay 1000 ffff f000 //Disable MSA reset 7A18 0005 7B18 0005 7C18 0005 7D18 0005 //Adjust VS0_DMA_HSYNC 7A28 00FF 7A2A 00FF //Adjust VS0_DMA_VSYNC 7A24 00FF 7A27 000F //Adjust VS1_DMA_HSYNC 7B28 00FF 7B2A 00FF //Adjust VS1_DMA_VSYNC 7B24 00FF 7B27 000F //Enable MST_VS0_DTG_ENABLE 7A14 0001 //Enable MST_VS1_DTG_ENABLE 7B14 0001 //Enable VS0_Enable 7A00 0001 //Enable VS1_Enable 7B00 0001 //300M 6424 00aa 6425 00aa //Turn on video 6420 0013 //Turn off video 6420 0010 //Turn on video 6420 0013 ]; i2c5_max96745_pinctrl: i2c5-max96745-pinctrl { compatible = "maxim,max96745-pinctrl"; pinctrl-names = "default"; pinctrl-0 = <&i2c5_max96745_pinctrl_pins>; status = "okay"; i2c5_max96745_pinctrl_pins: pinctrl-pins { i2c { groups = "MAX96745_I2C"; function = "MAX96745_I2C"; }; lcd-bl-pwm { pins = "MAX96745_MFP0"; function = "SER_TXID4_TO_DES_LINKA"; }; tp-int { pins = "MAX96745_MFP1"; function = "DES_RXID1_TO_SER_LINKA"; }; lcd-bl-pwm-split { pins = "MAX96745_MFP2"; function = "SER_TXID4_TO_DES_LINKB"; }; tp-int-split { pins = "MAX96745_MFP4"; function = "DES_RXID1_TO_SER_LINKB"; }; }; i2c5_max96745_gpio: i2c5-max96745-gpio { compatible = "maxim,max96745-gpio"; status = "okay"; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&i2c5_max96745_pinctrl 0 220 25>; }; }; i2c5_max96745_bridge: i2c5-max96745-bridge { compatible = "maxim,max96745-bridge"; status = "okay"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; i2c5_max96745_from_dp0: endpoint { remote-endpoint = <&dp0_out_i2c5_max96745>; }; }; port@1 { reg = <1>; i2c5_max96745_out_i2c5_max96752: endpoint { remote-endpoint = <&i2c5_max96752_from_i2c5_max96745>; }; }; }; }; i2c5_max96745_bridge_split: i2c5-max96745-bridge-split { compatible = "maxim,max96745-bridge-split"; status = "okay"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; i2c5_max96745_from_dp1: endpoint { remote-endpoint = <&dp1_out_i2c5_max96745>; }; }; port@1 { reg = <1>; i2c5_max96745_out_i2c5_max96752_split: endpoint { remote-endpoint = <&i2c5_max96752_split_from_i2c5_max96745>; }; }; }; }; }; i2c5_max96752: i2c5-max96752@4a { compatible = "maxim,max96752"; reg = <0x4a>; #address-cells = <1>; #size-cells = <0>; id-serdes-panel-split = <0x02>; link = <0x01>; status = "okay"; serdes-init-sequence = [ /*max96752 dual oLDI output*/ 0002 0043 0073 0031 007b 0031 007d 0038 //Address Value of I2C SRC_A 0042 008a //Address Value of I2C DST_A 0043 0090 0050 0000 01ce 004e 01ea 0004 ]; i2c5_max96752_pinctrl: i2c5-max96752-pinctrl { compatible = "maxim,max96752-pinctrl"; status = "okay"; pinctrl-names = "default","init","sleep"; pinctrl-0 = <&i2c5_max96752_panel_pins>; pinctrl-1 = <&i2c5_max96752_panel_pins>; pinctrl-2 = <&i2c5_max96752_panel_sleep_pins>; i2c5_max96752_panel_pins: panel-pins { lcd-rst-pin { pins = "MAX96752_GPIO10"; function = "DES_TXID10_OUTPUT_HIGH"; }; tp-rst { pins = "MAX96752_GPIO5"; function = "DES_TXID5_OUTPUT_HIGH"; }; tp-int { pins = "MAX96752_GPIO2"; function = "DES_TXID1_TO_SER"; }; 40ms-delay { pins = "MAX96752_GPIO15"; function = "DELAY_40MS"; }; lcd-pwr-on { pins = "MAX96752_GPIO3"; function = "DES_TXID3_OUTPUT_HIGH"; }; lcd-bl-pwm { pins = "MAX96752_GPIO4"; function = "SER_TO_DES_RXID4"; }; lcd_bias_en { pins = "MAX96752_GPIO7"; function = "DES_TXID7_OUTPUT_HIGH"; }; lcd_vdd_en { pins = "MAX96752_GPIO6"; function = "DES_TXID6_OUTPUT_HIGH"; }; }; i2c5_max96752_panel_sleep_pins: panel-sleep-pins { lcd-rst-pin { pins = "MAX96752_GPIO10"; function = "DES_TXID10_OUTPUT_LOW"; }; tp-rst { pins = "MAX96752_GPIO5"; function = "DES_TXID5_OUTPUT_LOW"; }; lcd-pwr-on { pins = "MAX96752_GPIO3"; function = "DES_TXID3_OUTPUT_LOW"; }; }; i2c5_max96752_gpio: i2c5-max96752-gpio { compatible = "maxim,max96752-gpio"; status = "okay"; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&i2c5_max96752_pinctrl 0 250 15>; }; }; i2c5_max96752_panel: i2c5-max96752-panel { compatible = "maxim,max96752-panel"; status = "okay"; backlight = <&dp2lvds_backlight0>; panel-size= <346 194>; panel-timing { clock-frequency = <148500000>; hactive = <1920>; vactive = <1080>; hfront-porch = <140>; hsync-len = <40>; hback-porch = <100>; vfront-porch = <15>; vsync-len = <20>; vback-porch = <10>; hsync-active = <0>; vsync-active = <0>; de-active = <0>; pixelclk-active = <0>; }; port { i2c5_max96752_from_i2c5_max96745: endpoint { remote-endpoint = <&i2c5_max96745_out_i2c5_max96752>; }; }; }; }; i2c5_max96752_split: i2c5-max96752-split@4b { compatible = "maxim,max96752"; reg = <0x4b>; reg-hw = <0x4a>; #address-cells = <1>; #size-cells = <0>; id-serdes-panel-split = <0x02>; link = <0x02>; status = "okay"; serdes-init-sequence = [ /*max96752 dual oLDI output*/ 0002 0043 0073 0032 007b 0032 007d 0038 //Address Value of I2C SRC_A 0042 008c //Address Value of I2C DST_A 0043 0090 0050 0001 01ce 004e 01ea 0004 ]; i2c5_max96752_split_pinctrl: i2c5-max96752-split-pinctrl { compatible = "maxim,max96752-pinctrl"; status = "okay"; pinctrl-names = "default","init","sleep"; pinctrl-0 = <&i2c5_max96752_split_panel_pins>; pinctrl-1 = <&i2c5_max96752_split_panel_pins>; pinctrl-2 = <&i2c5_max96752_split_panel_sleep_pins>; i2c5_max96752_split_panel_pins: panel-pins { lcd-rst-pin { pins = "MAX96752_GPIO10"; function = "DES_TXID10_OUTPUT_HIGH"; }; tp-rst { pins = "MAX96752_GPIO5"; function = "DES_TXID5_OUTPUT_HIGH"; }; tp-int { pins = "MAX96752_GPIO2"; function = "DES_TXID1_TO_SER"; }; 40ms-delay { pins = "MAX96752_GPIO15"; function = "DELAY_40MS"; }; lcd-pwr-on { pins = "MAX96752_GPIO3"; function = "DES_TXID3_OUTPUT_HIGH"; }; lcd-bl-pwm { pins = "MAX96752_GPIO4"; function = "SER_TO_DES_RXID4"; }; lcd_bias_en { pins = "MAX96752_GPIO7"; function = "DES_TXID7_OUTPUT_HIGH"; }; lcd_vdd_en { pins = "MAX96752_GPIO6"; function = "DES_TXID6_OUTPUT_HIGH"; }; }; i2c5_max96752_split_panel_sleep_pins: panel-sleep-pins { lcd-rst-pin { pins = "MAX96752_GPIO10"; function = "DES_TXID10_OUTPUT_LOW"; }; tp-rst { pins = "MAX96752_GPIO5"; function = "DES_TXID5_OUTPUT_LOW"; }; lcd-pwr-on { pins = "MAX96752_GPIO3"; function = "DES_TXID3_OUTPUT_LOW"; }; }; i2c5_max96752_split_gpio: i2c5-max96752-split-gpio { compatible = "maxim,max96752-gpio"; status = "okay"; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&i2c5_max96752_split_pinctrl 0 305 15>; }; }; i2c5_max96752_split_panel: i2c5-max96752-split-panel { compatible = "maxim,max96752-panel-split"; status = "okay"; backlight = <&dp2lvds_backlight1>; panel-size= <346 194>; panel-timing { clock-frequency = <115000000>; hactive = <1920>; vactive = <720>; hfront-porch = <56>; hsync-len = <32>; hback-porch = <56>; vfront-porch = <200>; vsync-len = <2>; vback-porch = <8>; hsync-active = <0>; vsync-active = <0>; de-active = <0>; pixelclk-active = <0>; }; port { i2c5_max96752_split_from_i2c5_max96745: endpoint { remote-endpoint = <&i2c5_max96745_out_i2c5_max96752_split>; }; }; }; }; ilitek@41 { compatible = "ilitek,ili251x"; reg = <0x41>; interrupt-parent = <&gpio2>; interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&touch_gpio_dp>; //reset-gpio = <&gpio0 RK_PD1 GPIO_ACTIVE_LOW>; ilitek,name = "ilitek_i2c"; status = "okay"; }; himax_split@46 { compatible = "himax,hxcommon"; reg = <0x46>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&touch_gpio_edp>; pinctrl-1 = <&touch_gpio_edp>; himax,location = "himax-touch-edp"; himax,irq-gpio = <&gpio4 RK_PC1 IRQ_TYPE_EDGE_FALLING>; himax,rst-gpio = <&i2c5_max96752_split_gpio 5 GPIO_ACTIVE_LOW>; himax,panel-coords = <0 1920 0 720>; himax,display-coords = <0 1920 0 720>; status = "okay"; }; }; &mipidcphy0 { status = "okay"; }; &pinctrl { serdes { /*EDP*/ i2c2_serdes_pins: i2c2-serdes-pins { rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>,/*lock*/ <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;/*err*/ }; /*DP*/ i2c5_serdes_pins: i2c5-serdes-pins { rockchip,pins = <2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>,/*err*/ <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;/*lock*/ }; /*DSI*/ i2c8_serdes_pins: i2c8-serdes-pins { rockchip,pins = <2 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>,/*err*/ <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;/*lock*/ }; }; }; /* dsi->serdes->lvds_panel */ &pwm1_6ch_1 { status = "okay"; pinctrl-0 = <&pwm1m0_ch1>; }; /* dp->serdes->lvds_panel */ &pwm2_8ch_0 { pinctrl-0 = <&pwm2m2_ch0>; status = "okay"; }; /* edp->serdes->lvds_panel */ &pwm2_8ch_5 { pinctrl-0 = <&pwm2m1_ch5>; status = "okay"; }; &route_dp0 { status = "disabled"; connect = <&vp2_out_dp0>; logo,uboot = "logo2.bmp"; logo,kernel = "logo2.bmp"; }; &route_dsi { status = "okay"; connect = <&vp1_out_dsi>; logo,uboot = "logo1.bmp"; logo,kernel = "logo1.bmp"; }; &route_edp { status = "disabled"; connect = <&vp0_out_edp>; logo,uboot = "logo2.bmp"; logo,kernel = "logo2.bmp"; }; &usbdp_phy { rockchip,dp-lane-mux = <0 1 2 3>; status = "okay"; }; &usbdp_phy_dp { status = "okay"; }; &usbdp_phy_u3 { maximum-speed = "high-speed"; status = "okay"; }; &vop { assigned-clocks = <&cru PLL_VPLL>; assigned-clock-rates = <1150000000>; }; //dsi &vp1 { assigned-clocks = <&cru DCLK_VP1_SRC>; assigned-clock-parents = <&cru PLL_VPLL>; }; //dp1 &vp0 { assigned-clocks = <&cru DCLK_VP0_SRC>; assigned-clock-parents = <&cru PLL_VPLL>; };