// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
 *
 */

/dts-v1/;

#include <dt-bindings/display/media-bus-format.h>
#include "rk3576.dtsi"
#include "rk3576-cpu-swap.dtsi"
#include "rk3576-evb2.dtsi"
#include "rk3576-evb2-rk628-bt1120-to-hdmi.dtsi"
#include "rk3576-evb2-rk628-hdmi2csi.dtsi"
#include "rk3576-linux.dtsi"

/ {
	model = "Rockchip RK3576 EVB2 V10 NVR Board";
	compatible = "rockchip,rk3576-nvr-v10", "rockchip,rk3576";
};

&cluster0_opp_table {
	/delete-node/ opp-408000000;
	/delete-node/ opp-600000000;
	/delete-node/ opp-816000000;
	/delete-node/ opp-1008000000;
	/delete-node/ opp-1200000000;
	/delete-node/ opp-1416000000;
	/delete-node/ opp-2208000000;
};

&cluster1_opp_table {
	/delete-node/ opp-408000000;
	/delete-node/ opp-600000000;
	/delete-node/ opp-816000000;
	/delete-node/ opp-1008000000;
	/delete-node/ opp-1200000000;
	/delete-node/ opp-1416000000;
	/delete-node/ opp-2304000000;
};

&display_subsystem {
	/delete-property/ clkcks;
	/delete-property/ clocks-names;
};

&dmc {
	status = "okay";
	center-supply = <&vdd_ddr_s0>;
	mem-supply = <&vdd_logic_s0>;
	system-status-level = <
		/* system status	freq level */
		SYS_STATUS_NORMAL	DMC_FREQ_LEVEL_HIGH
		SYS_STATUS_REBOOT	DMC_FREQ_LEVEL_HIGH
		SYS_STATUS_SUSPEND	DMC_FREQ_LEVEL_LOW
		SYS_STATUS_VIDEO_4K	DMC_FREQ_LEVEL_MID_HIGH
		SYS_STATUS_VIDEO_4K_10B	DMC_FREQ_LEVEL_MID_HIGH
		SYS_STATUS_VIDEO_SVEP	DMC_FREQ_LEVEL_MID_HIGH
		SYS_STATUS_BOOST	DMC_FREQ_LEVEL_HIGH
		SYS_STATUS_ISP		DMC_FREQ_LEVEL_HIGH
		SYS_STATUS_PERFORMANCE	DMC_FREQ_LEVEL_HIGH
		SYS_STATUS_DUALVIEW	DMC_FREQ_LEVEL_HIGH
		SYS_STATUS_HDMIRX	DMC_FREQ_LEVEL_HIGH
		SYS_STATUS_DEEP_SUSPEND	DMC_FREQ_LEVEL_HIGH
	>;
	auto-freq-en = <0>;
};

&dp0_in_vp0 {
	status = "okay";
};

&dp0_in_vp1 {
	status = "okay";
};

&dp0_in_vp2 {
	status = "okay";
};

&hdmi_in_vp0 {
	status = "okay";
};

&hdmi_in_vp1 {
	status = "okay";
};

&hdmi_in_vp2 {
	status = "okay";
};

&npu_opp_table {
	/delete-node/ opp-1000000000;
};

&rgb_in_vp1 {
	status = "okay";
};

&rgb_in_vp2 {
	status = "okay";
};

&route_dp0 {
	status = "okay";
	connect = <&vp0_out_dp0>;
	force-output;

	force_timing {
		clock-frequency = <65000000>;
		hactive = <1024>;
		vactive = <768>;
		hfront-porch = <24>;
		hsync-len = <136>;
		hback-porch = <160>;
		vfront-porch = <3>;
		vsync-len = <6>;
		vback-porch = <29>;
		hsync-active = <0>;
		vsync-active = <0>;
		de-active = <0>;
		pixelclk-active = <0>;
	};
};

&route_hdmi {
	status = "okay";
	connect = <&vp0_out_hdmi>;
	force-output;

	force_timing {
		clock-frequency = <65000000>;
		hactive = <1024>;
		vactive = <768>;
		hfront-porch = <24>;
		hsync-len = <136>;
		hback-porch = <160>;
		vfront-porch = <3>;
		vsync-len = <6>;
		vback-porch = <29>;
		hsync-active = <0>;
		vsync-active = <0>;
		de-active = <0>;
		pixelclk-active = <0>;
	};
};

&route_rgb {
	status = "okay";
	connect = <&vp1_out_rgb>;

	force-bus-format = <MEDIA_BUS_FMT_YUYV8_1X16>;
	force-output;

	force_timing {
		clock-frequency = <65000000>;
		hactive = <1024>;
		vactive = <768>;
		hfront-porch = <24>;
		hsync-len = <136>;
		hback-porch = <160>;
		vfront-porch = <3>;
		vsync-len = <6>;
		vback-porch = <29>;
		hsync-active = <1>;
		vsync-active = <1>;
		de-active = <0>;
		pixelclk-active = <0>;
	};
};

&rk628d {
	display-timings {
		src-timing {
			clock-frequency = <65000000>;
			hactive = <1024>;
			vactive = <768>;
			hfront-porch = <24>;
			hsync-len = <136>;
			hback-porch = <160>;
			vfront-porch = <3>;
			vsync-len = <6>;
			vback-porch = <29>;
			hsync-active = <1>;
			vsync-active = <1>;
			de-active = <0>;
			pixelclk-active = <0>;
		};

		dst-timing {
			clock-frequency = <65000000>;
			hactive = <1024>;
			vactive = <768>;
			hfront-porch = <24>;
			hsync-len = <136>;
			hback-porch = <160>;
			vfront-porch = <3>;
			vsync-len = <6>;
			vback-porch = <29>;
			hsync-active = <0>;
			vsync-active = <0>;
			de-active = <0>;
			pixelclk-active = <0>;
		};
	};
};

&rkisp_vir0_sditf {
	status = "okay";
};

&rkvpss {
	status = "okay";
};

&rkvpss_mmu {
	status = "okay";
};

&rkvpss_vir0 {
	status = "okay";
};

&vp0 {
	assigned-clocks = <&cru DCLK_VP0_SRC>;
	assigned-clock-parents = <&cru PLL_VPLL>;
};

&vp1 {
	assigned-clocks = <&cru DCLK_VP1_SRC>;
	assigned-clock-parents = <&cru PLL_VPLL>;
};

&vp2 {
	assigned-clocks = <&cru DCLK_VP2_SRC>;
	assigned-clock-parents = <&cru PLL_GPLL>;
};