// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
 *
 */

/ {
	rk628f_dc: rk628f-dc {
		compatible = "rockchip,dummy-codec";
		#sound-dai-cells = <0>;
	};

	rkvtunnel: rkvtunnel {
		compatible = "rockchip,video-tunnel";
		status = "okay";
	};

	hdmiin-sound {
		compatible = "simple-audio-card";
		simple-audio-card,format = "i2s";
		simple-audio-card,name = "rockchip,hdmiin";
		simple-audio-card,bitclock-master = <&dailink0_master>;
		simple-audio-card,frame-master = <&dailink0_master>;
		status = "okay";
		simple-audio-card,cpu {
			sound-dai = <&sai4>;
		};
		dailink0_master: simple-audio-card,codec {
			sound-dai = <&rk628f_dc>;
		};
	};

	//vcc_mipicsi1: vcc-mipicsi1-regulator {
	//	compatible = "regulator-fixed";
	//	gpio = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
	//	pinctrl-names = "default";
	//	pinctrl-0 = <&mipicsi1_pwr>;
	//	regulator-name = "vcc_mipicsi1";
	//	enable-active-high;
	//};	
};

&csi2_dphy0 {
	status = "okay";

	ports {
		#address-cells = <1>;
		#size-cells = <0>;
		port@0 {
			reg = <0>;
			#address-cells = <1>;
			#size-cells = <0>;

			hdmi_mipi_in: endpoint@1 {
				reg = <1>;
				remote-endpoint = <&hdmiin_out>;
				data-lanes = <1 2 3 4>;
			};
		};
		port@1 {
			reg = <1>;
			#address-cells = <1>;
			#size-cells = <0>;

			csidphy0_out: endpoint@0 {
				reg = <0>;
				remote-endpoint = <&mipi1_csi2_input>;
			};
		};
	};
};

&csi2_dphy0_hw {
	status = "okay";
};

&csi2_dphy1_hw {
	status = "okay";
};

&i2c5 {
	status = "okay";
	pinctrl-0 = <&i2c5m3_xfer>;
	clock-frequency = <100000>;
	//clock-frequency = <400000>;

	rk628_csi: rk628_csi@51 {
		reg = <0x51>;
		compatible = "rockchip,rk628-csi-v4l2";
		status = "okay";
		//clocks = <&cru REF_CLK0_OUT_PLL>;
		//clock-names = "xvclk";		
		pinctrl-names = "default";
		//pinctrl-0 = <&rk628_hdmiin_pin &ref_clk0_clk0>;
		pinctrl-0 = <&rk628_hdmiin_pin>;
		power-domains = <&power RK3576_PD_VI>;
		interrupt-parent = <&gpio4>;
		interrupts = <RK_PA0 IRQ_TYPE_EDGE_RISING>;
		enable-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
		reset-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
		plugin-det-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
		continues-clk = <1>;

		rockchip,camera-module-index = <0>;
		rockchip,camera-module-facing = "back";
		rockchip,camera-module-name = "HDMI-MIPI1";
		rockchip,camera-module-lens-name = "RK628-CSI";

		multi-dev-info {
			dev-idx-l = <1>;
			dev-idx-r = <3>;
			combine-idx = <1>;
			pixel-offset = <0>;
			dev-num = <2>;
		};

		port {
			hdmiin_out: endpoint {
				remote-endpoint = <&hdmi_mipi_in>;
				data-lanes = <1 2 3 4>;
			};
		};
	};
};

&mipi1_csi2 {
	status = "okay";

	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
			reg = <0>;
			#address-cells = <1>;
			#size-cells = <0>;

			mipi1_csi2_input: endpoint@1 {
				reg = <1>;
				remote-endpoint = <&csidphy0_out>;
			};
		};

		port@1 {
			reg = <1>;
			#address-cells = <1>;
			#size-cells = <0>;

			mipi1_csi2_output: endpoint@0 {
				reg = <0>;
				remote-endpoint = <&cif_mipi_in1>;
			};
		};
	};
};

&rkcif {
	status = "okay";
};

&rkcif_mipi_lvds1 {
	status = "okay";

	port {
		cif_mipi_in1: endpoint {
			remote-endpoint = <&mipi1_csi2_output>;
		};
	};
};

&rkcif_mmu {
	status = "okay";
};

&sai4 {
	pinctrl-names = "default";
	pinctrl-0 = <&sai4m0_lrck
		     &sai4m0_sclk
		     &sai4m0_sdi>;
	status = "okay";
};

&pinctrl {
	hdmiin {
		//mipicsi1_pwr: mipicsi1-pwr {
		//	rockchip,pins =
		//		/* 628H camera power en */
		//		<3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
		//};

		rk628_hdmiin_pin: rk628-hdmiin-pin {
			rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>,
					<2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>,
					<3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>,
					<3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};
};