// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2023 Rockchip Electronics Co., Ltd. * */ #include #include "rk3562-evb1-lp4x-v10.dtsi" #include "rk3562-android.dtsi" #include "rk3562-rk817.dtsi" / { model = "Rockchip RK3562 EVB1 LP4X V10 Board + RK EVB SPI+RGB PANLE DISPLAY Ext Board"; compatible = "rockchip,rk3562-evb1-lp4x-v10-rgb-k350c4516t", "rockchip,rk3562"; spi_gpio: spi-gpio { compatible = "spi-gpio"; #address-cells = <0x1>; #size-cells = <0x0>; pinctrl-names = "default"; pinctrl-0 = <&spi_gpio_pins>; spi-delay-us = <10>; status = "okay"; sck-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; miso-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; mosi-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; cs-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; num-chipselects = <1>; /* * 320x480 RGB/MCU screen K350C4516T */ panel: panel { compatible = "simple-panel-spi"; reg = <0>; bus-format = ; backlight = <&backlight>; enable-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>; enable-delay-ms = <20>; reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; reset-delay-ms = <10>; prepare-delay-ms = <20>; unprepare-delay-ms = <20>; disable-delay-ms = <20>; init-delay-ms = <10>; width-mm = <217>; height-mm = <136>; rockchip,cmd-type = "spi"; status = "okay"; // type:0 is cmd, 1 is data panel-init-sequence = [ /* type delay num val1 val2 val3 */ 00 00 01 e0 01 00 01 00 01 00 01 07 01 00 01 0f 01 00 01 0d 01 00 01 1b 01 00 01 0a 01 00 01 3c 01 00 01 78 01 00 01 4a 01 00 01 07 01 00 01 0e 01 00 01 09 01 00 01 1b 01 00 01 1e 01 00 01 0f 00 00 01 e1 01 00 01 00 01 00 01 22 01 00 01 24 01 00 01 06 01 00 01 12 01 00 01 07 01 00 01 36 01 00 01 47 01 00 01 47 01 00 01 06 01 00 01 0a 01 00 01 07 01 00 01 30 01 00 01 37 01 00 01 0f 00 00 01 c0 01 00 01 10 01 00 01 10 00 00 01 c1 01 00 01 41 00 00 01 c5 01 00 01 00 01 00 01 22 01 00 01 80 00 00 01 36 01 00 01 48 00 00 01 3a 01 00 01 66 /* * interface pixel format: * 66 for RGB666(18bit) */ 00 00 01 b0 01 00 01 00 00 00 01 b1 01 00 01 a0 /* * frame rate control: * a0 (60hz) for RGB666(18bit) */ 01 00 01 11 00 00 01 b4 01 00 01 02 00 00 01 B6 01 00 01 32 /* * display function control: * 32 for RGB * 02 for MCU */ 01 00 01 02 00 00 01 b7 01 00 01 c6 00 00 01 be 01 00 01 00 01 00 01 04 00 00 01 e9 01 00 01 00 00 00 01 f7 01 00 01 a9 01 00 01 51 01 00 01 2c 01 00 01 82 00 78 01 11 00 00 01 29 ]; panel-exit-sequence = [ //type delay num val1 val2 val3 00 0a 01 28 00 78 01 10 ]; display-timings { native-mode = <&kd050fwfba002_timing>; kd050fwfba002_timing: timing0 { /* * 10453500 for RGB666(18bit) */ clock-frequency = <10453500>; hactive = <320>; vactive = <480>; hback-porch = <10>; hfront-porch = <5>; vback-porch = <10>; vfront-porch = <5>; hsync-len = <10>; vsync-len = <10>; hsync-active = <0>; vsync-active = <0>; de-active = <0>; pixelclk-active = <1>; }; }; port { panel_in_rgb: endpoint { remote-endpoint = <&rgb_out_panel>; }; }; }; }; }; &backlight { status = "okay"; pwms = <&pwm9 0 25000 0>; }; &dsi { status = "disabled"; }; &dsi_in_vp0 { status = "disabled"; }; /* * The pins of gmac0/pcie2x1 and rgb are multiplexed */ &gmac0 { status = "disabled"; }; &pcie2x1 { status = "disabled"; }; &pinctrl { spi_gpio { spi_gpio_pins: spi-gpio-pins { rockchip,pins = /* spi sdo */ <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>, /* spi sdi */ <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>, /* spi scl */ <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, /* spi cs */ <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; &pwm9 { status = "okay"; }; &rgb { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&rgb666_pins>; ports { rgb_out: port@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; rgb_out_panel: endpoint@0 { reg = <0>; remote-endpoint = <&panel_in_rgb>; }; }; }; }; &rgb_in_vp0 { status = "okay"; }; &route_rgb { status = "okay"; connect = <&vp0_out_rgb>; }; /* * The pins of sai0/vcc_mipicsi0 and rgb are multiplexed */ &sai0 { status = "disabled"; }; &vcc_mipicsi0 { status = "disabled"; }; &video_phy { status = "disabled"; }; &vop { status = "okay"; };