/dts-v1/;
/plugin/;

#include <dt-bindings/clock/rk3588-cru.h>
#include <dt-bindings/power/rk3588-power.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>

/ {
	
	fragment@0 {
		target = <&i2c4>;

		__overlay__ {
			status = "okay";
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c4m1_xfer>;
			
			ov13850_1: ov13850_1@10 {
                status = "okay";
                compatible = "ovti,ov13850";
                reg = <0x10>;
                clocks = <&cru CLK_MIPI_CAMARAOUT_M2>;
                clock-names = "xvclk";
                pinctrl-names = "default";
                pinctrl-0 = <&mipim0_camera2_clk>;
                rockchip,grf = <&sys_grf>;
                pwdn-gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
                reset-gpios = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>;
                rockchip,camera-module-index = <1>;
                rockchip,camera-module-facing = "back";
                rockchip,camera-module-name = "ZC-OV13850R2A-V1";
                rockchip,camera-module-lens-name = "Largan-50064B31";
                port {
                    ov13850_out1: endpoint {
                        remote-endpoint = <&mipidphy3_in_ucam3>;
                        data-lanes = <1 2 3 4>;
                    };
                };
            };
		};
	};

	fragment@1 {
		target = <&csi2_dphy1_hw>;

		__overlay__ {
			status = "okay";
		};
	};

	fragment@2 {
		target = <&csi2_dphy3>;

		__overlay__ {
			status = "okay";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					#address-cells = <1>;
					#size-cells = <0>;

					mipidphy3_in_ucam3: endpoint@1 {
						reg = <1>;
						remote-endpoint = <&ov13850_out1>;
						data-lanes = <1 2 3 4>;
					};

				};

				port@1 {
					reg = <1>;
					#address-cells = <1>;
					#size-cells = <0>;

					csidphy3_out: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&mipi4_csi2_input>;
					};
				};
			};
		};
	};

	fragment@3 {
		target = <&mipi4_csi2>;

		__overlay__ {
			status = "okay";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					#address-cells = <1>;
					#size-cells = <0>;

					mipi4_csi2_input: endpoint@1 {
						reg = <1>;
						remote-endpoint = <&csidphy3_out>;
					};
				};

				port@1 {
					reg = <1>;
					#address-cells = <1>;
					#size-cells = <0>;

					mipi4_csi2_output: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&cif_mipi_in4>;
					};
				};
			};
	    };
	};

	fragment@4 {
		target = <&rkcif>;

		__overlay__ {
			status = "okay";
		};
	};

	fragment@5 {
		target = <&rkcif_mipi_lvds4>;

		__overlay__ {
			status = "okay";

			port {
				cif_mipi_in4: endpoint {
					remote-endpoint = <&mipi4_csi2_output>;
				};
			};
		};
	};

	fragment@6 {
		target = <&rkcif_mipi_lvds4_sditf>;

		__overlay__ {
			status = "okay";

			port {
				mipi4_lvds_sditf: endpoint {
					remote-endpoint = <&isp1_vir1>;
				};
			};

		};
	};

	fragment@7 {
		target = <&rkcif_mmu>;

		__overlay__ {
			status = "okay";
		};
	};

	fragment@8 {
		target = <&rkisp1>;

		__overlay__ {
			status = "okay";
		};
	};

	fragment@9 {
		target = <&isp1_mmu>;

		__overlay__ {
			status = "okay";
		};
	};

	fragment@10 {
		target = <&rkisp1_vir1>;

		__overlay__ {
			status = "okay";

			port {
				#address-cells = <1>;
				#size-cells = <0>;

				isp1_vir1: endpoint@0 {
					reg = <0>;
					remote-endpoint = <&mipi4_lvds_sditf>;
				};
			};
		};
	};
	
};