/* SPDX-License-Identifier: GPL-2.0
 * aw882xx_pid_2308_reg.h
 *
 * Copyright (c) 2020 AWINIC Technology CO., LTD
 *
 * Author: Nick Li <liweilei@awinic.com.cn>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 */

#ifndef __AW882XX_PID_2308_REG_H__
#define __AW882XX_PID_2308_REG_H__

#define AW_PID_2308_MONITOR_FILE	"aw882xx_pid_2308_monitor.bin"

/* registers list */
#define AW_PID_2308_ID_REG			(0x00)
#define AW_PID_2308_SYSST_REG			(0x01)
#define AW_PID_2308_SYSINT_REG			(0x02)
#define AW_PID_2308_SYSINTM_REG			(0x03)
#define AW_PID_2308_SYSCTRL_REG			(0x04)
#define AW_PID_2308_SYSCTRL2_REG		(0x05)
#define AW_PID_2308_I2SCTRL1_REG		(0x06)
#define AW_PID_2308_I2SCTRL2_REG		(0x07)
#define AW_PID_2308_I2SCTRL3_REG		(0x08)
#define AW_PID_2308_DACCFG1_REG			(0x09)
#define AW_PID_2308_DACCFG2_REG			(0x0A)
#define AW_PID_2308_DACCFG3_REG			(0x0B)
#define AW_PID_2308_DACCFG4_REG			(0x0C)
#define AW_PID_2308_DACCFG5_REG			(0x0D)
#define AW_PID_2308_DACCFG6_REG			(0x0E)
#define AW_PID_2308_DACCFG7_REG			(0x0F)
#define AW_PID_2308_DACCFG8_REG			(0x10)
#define AW_PID_2308_PWMCTRL1_REG		(0x11)
#define AW_PID_2308_PWMCTRL2_REG		(0x12)
#define AW_PID_2308_I2SCFG1_REG			(0x13)
#define AW_PID_2308_MPDCFG5_REG			(0x14)
#define AW_PID_2308_BOPCTRL1_REG		(0x15)
#define AW_PID_2308_BOPCTRL2_REG		(0x16)
#define AW_PID_2308_BOPCTRL3_REG		(0x17)
#define AW_PID_2308_BOPCTRL4_REG		(0x18)
#define AW_PID_2308_BOPCTRL5_REG		(0x19)
#define AW_PID_2308_BOPCTRL6_REG		(0x1A)
#define AW_PID_2308_BOPCTRL7_REG		(0x1B)
#define AW_PID_2308_BOPCTRL8_REG		(0x1C)
#define AW_PID_2308_BOPCTRL9_REG		(0x1D)
#define AW_PID_2308_BOPCTRL10_REG		(0x1E)
#define AW_PID_2308_DBGCTRL_REG			(0x1F)
#define AW_PID_2308_DACST_REG			(0x20)
#define AW_PID_2308_VBAT_REG			(0x21)
#define AW_PID_2308_TEMP_REG			(0x22)
#define AW_PID_2308_PVDD_REG			(0x23)
#define AW_PID_2308_ISNDAT_REG			(0x24)
#define AW_PID_2308_VSNDAT_REG			(0x25)
#define AW_PID_2308_I2SINT_REG			(0x26)
#define AW_PID_2308_I2SCAPCNT_REG		(0x27)
#define AW_PID_2308_TESTDET_REG			(0x28)
#define AW_PID_2308_ANASTA1_REG			(0x29)
#define AW_PID_2308_ANASTA2_REG			(0x2A)
#define AW_PID_2308_ANASTA3_REG			(0x2B)
#define AW_PID_2308_ANASTA4_REG			(0x2C)
#define AW_PID_2308_ANASTA5_REG			(0x2D)
#define AW_PID_2308_TESTOUT_REG			(0x2E)
#define AW_PID_2308_DC_DOUT_REG			(0x2F)
#define AW_PID_2308_DSMCFG1_REG			(0x30)
#define AW_PID_2308_DSMCFG2_REG			(0x31)
#define AW_PID_2308_DSMCFG3_REG			(0x32)
#define AW_PID_2308_DSMCFG4_REG			(0x33)
#define AW_PID_2308_DSMCFG5_REG			(0x34)
#define AW_PID_2308_DSMCFG6_REG			(0x35)
#define AW_PID_2308_DSMCFG7_REG			(0x36)
#define AW_PID_2308_DSMCFG8_REG			(0x37)
#define AW_PID_2308_TESTIN_REG			(0x38)
#define AW_PID_2308_DETCTRL1_REG		(0x3A)
#define AW_PID_2308_DETCTRL2_REG		(0x3B)
#define AW_PID_2308_MPDCFG1_REG			(0x3C)
#define AW_PID_2308_MPDCFG2_REG			(0x3D)
#define AW_PID_2308_MPDCFG3_REG			(0x3E)
#define AW_PID_2308_MPDCFG4_REG			(0x3F)
#define AW_PID_2308_ISNTM1_REG			(0x50)
#define AW_PID_2308_ISNCTRL3_REG		(0x51)
#define AW_PID_2308_VSNTM1_REG			(0x52)
#define AW_PID_2308_VSNTM2_REG			(0x53)
#define AW_PID_2308_ISNCTRL1_REG		(0x54)
#define AW_PID_2308_ISNCTRL2_REG		(0x55)
#define AW_PID_2308_PLLCTRL1_REG		(0x56)
#define AW_PID_2308_PLLCTRL2_REG		(0x57)
#define AW_PID_2308_PLLCTRL3_REG		(0x58)
#define AW_PID_2308_PSMCTRL1_REG		(0x59)
#define AW_PID_2308_PSMCTRL2_REG		(0x5A)
#define AW_PID_2308_PSMCTRL3_REG		(0x5B)
#define AW_PID_2308_NGCTRL1_REG			(0x5C)
#define AW_PID_2308_NGCTRL2_REG			(0x5D)
#define AW_PID_2308_NGCTRL3_REG			(0x5E)
#define AW_PID_2308_CPCTRL_REG			(0x5F)
#define AW_PID_2308_BSTCTRL1_REG		(0x60)
#define AW_PID_2308_BSTCTRL2_REG		(0x61)
#define AW_PID_2308_BSTCTRL3_REG		(0x62)
#define AW_PID_2308_BSTCTRL4_REG		(0x63)
#define AW_PID_2308_BSTCTRL5_REG		(0x64)
#define AW_PID_2308_BSTCTRL6_REG		(0x65)
#define AW_PID_2308_BSTCTRL7_REG		(0x66)
#define AW_PID_2308_BSTCTRL8_REG		(0x67)
#define AW_PID_2308_BSTCTRL9_REG		(0x68)
#define AW_PID_2308_CDACTRL1_REG		(0x69)
#define AW_PID_2308_CDACTRL2_REG		(0x6A)
#define AW_PID_2308_CDACTRL3_REG		(0x6B)
#define AW_PID_2308_CDACTRL4_REG		(0x6C)
#define AW_PID_2308_CDACTRL5_REG		(0x6D)
#define AW_PID_2308_TM2_REG			(0x6E)
#define AW_PID_2308_TM_REG			(0x6F)
#define AW_PID_2308_TESTCTRL1_REG		(0x70)
#define AW_PID_2308_TESTCTRL2_REG		(0x71)
#define AW_PID_2308_EFCTRL1_REG			(0x72)
#define AW_PID_2308_EFCTRL2_REG			(0x73)
#define AW_PID_2308_EFWH_REG			(0x74)
#define AW_PID_2308_EFWM2_REG			(0x75)
#define AW_PID_2308_EFWM1_REG			(0x76)
#define AW_PID_2308_EFWL_REG			(0x77)
#define AW_PID_2308_EFRH4_REG			(0x78)
#define AW_PID_2308_EFRH3_REG			(0x79)
#define AW_PID_2308_EFRH2_REG			(0x7A)
#define AW_PID_2308_EFRH1_REG			(0x7B)
#define AW_PID_2308_EFRL4_REG			(0x7C)
#define AW_PID_2308_EFRL3_REG			(0x7D)
#define AW_PID_2308_EFRL2_REG			(0x7E)
#define AW_PID_2308_EFRL1_REG			(0x7F)

/********************************************
 * Register Access
 *******************************************/
#define AW_PID_2308_REG_MAX				(0x80)

#define REG_NONE_ACCESS					(0)
#define REG_RD_ACCESS					(1 << 0)
#define REG_WR_ACCESS					(1 << 1)

const unsigned char aw_pid_2308_reg_access[AW_PID_2308_REG_MAX] = {
	[AW_PID_2308_ID_REG]		= (REG_RD_ACCESS),
	[AW_PID_2308_SYSST_REG]		= (REG_RD_ACCESS),
	[AW_PID_2308_SYSINT_REG]	= (REG_RD_ACCESS),
	[AW_PID_2308_SYSINTM_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_SYSCTRL_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_SYSCTRL2_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_I2SCTRL1_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_I2SCTRL2_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_I2SCTRL3_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_DACCFG1_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_DACCFG2_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_DACCFG3_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_DACCFG4_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_DACCFG5_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_DACCFG6_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_DACCFG7_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_DACCFG8_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_PWMCTRL1_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_PWMCTRL2_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_I2SCFG1_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_MPDCFG5_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_BOPCTRL1_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_BOPCTRL2_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_BOPCTRL3_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_BOPCTRL4_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_BOPCTRL5_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_BOPCTRL6_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_BOPCTRL7_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_BOPCTRL8_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_BOPCTRL9_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_BOPCTRL10_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_DBGCTRL_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_DACST_REG]		= (REG_RD_ACCESS),
	[AW_PID_2308_VBAT_REG]		= (REG_RD_ACCESS),
	[AW_PID_2308_TEMP_REG]		= (REG_RD_ACCESS),
	[AW_PID_2308_PVDD_REG]		= (REG_RD_ACCESS),
	[AW_PID_2308_ISNDAT_REG]	= (REG_RD_ACCESS),
	[AW_PID_2308_VSNDAT_REG]	= (REG_RD_ACCESS),
	[AW_PID_2308_I2SINT_REG]	= (REG_RD_ACCESS),
	[AW_PID_2308_I2SCAPCNT_REG]	= (REG_RD_ACCESS),
	[AW_PID_2308_TESTDET_REG]	= (REG_RD_ACCESS),
	[AW_PID_2308_ANASTA1_REG]	= (REG_RD_ACCESS),
	[AW_PID_2308_ANASTA2_REG]	= (REG_RD_ACCESS),
	[AW_PID_2308_ANASTA3_REG]	= (REG_RD_ACCESS),
	[AW_PID_2308_ANASTA4_REG]	= (REG_RD_ACCESS),
	[AW_PID_2308_ANASTA5_REG]	= (REG_RD_ACCESS),
	[AW_PID_2308_TESTOUT_REG]	= (REG_RD_ACCESS),
	[AW_PID_2308_DC_DOUT_REG]	= (REG_RD_ACCESS),
	[AW_PID_2308_DSMCFG1_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_DSMCFG2_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_DSMCFG3_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_DSMCFG4_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_DSMCFG5_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_DSMCFG6_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_DSMCFG7_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_DSMCFG8_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_TESTIN_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_DETCTRL1_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_DETCTRL2_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_MPDCFG1_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_MPDCFG2_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_MPDCFG3_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_MPDCFG4_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_ISNTM1_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_ISNCTRL3_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_VSNTM1_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_VSNTM2_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_ISNCTRL1_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_ISNCTRL2_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_PLLCTRL1_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_PLLCTRL2_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_PLLCTRL3_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_PSMCTRL1_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_PSMCTRL2_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_PSMCTRL3_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_NGCTRL1_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_NGCTRL2_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_NGCTRL3_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_CPCTRL_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_BSTCTRL1_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_BSTCTRL2_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_BSTCTRL3_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_BSTCTRL4_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_BSTCTRL5_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_BSTCTRL6_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_BSTCTRL7_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_BSTCTRL8_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_BSTCTRL9_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_CDACTRL1_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_CDACTRL2_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_CDACTRL3_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_CDACTRL4_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_CDACTRL5_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_TM2_REG]		= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_TM_REG]		= (REG_NONE_ACCESS),
	[AW_PID_2308_TESTCTRL1_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_TESTCTRL2_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_EFCTRL1_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_EFCTRL2_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_EFWH_REG]		= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_EFWM2_REG]		= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_EFWM1_REG]		= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_EFWL_REG]		= (REG_RD_ACCESS | REG_WR_ACCESS),
	[AW_PID_2308_EFRH4_REG]		= (REG_RD_ACCESS),
	[AW_PID_2308_EFRH3_REG]		= (REG_RD_ACCESS),
	[AW_PID_2308_EFRH2_REG]		= (REG_RD_ACCESS),
	[AW_PID_2308_EFRH1_REG]		= (REG_RD_ACCESS),
	[AW_PID_2308_EFRL4_REG]		= (REG_RD_ACCESS),
	[AW_PID_2308_EFRL3_REG]		= (REG_RD_ACCESS),
	[AW_PID_2308_EFRL2_REG]		= (REG_RD_ACCESS),
	[AW_PID_2308_EFRL1_REG]		= (REG_RD_ACCESS),
};

/********************************************
 * Volume Coefficient
 *******************************************/
#define AW_PID_2308_VOL_STEP		(64)
#define AW_PID_2308_MUTE_VOL		(1023)

/* detail information of registers begin */
/* ID (0x00) detail */
/* IDCODE bit 15:0 (ID 0x00) */
#define AW_PID_2308_IDCODE_START_BIT	(0)
#define AW_PID_2308_IDCODE_BITS_LEN		(16)
#define AW_PID_2308_IDCODE_MASK			\
	(~(((1<<AW_PID_2308_IDCODE_BITS_LEN)-1) << AW_PID_2308_IDCODE_START_BIT))

#define AW_PID_2308_IDCODE_DEFAULT		(0x2308)
#define AW_PID_2308_IDCODE_DEFAULT_VALUE	\
	(AW_PID_2308_IDCODE_DEFAULT << AW_PID_2308_IDCODE_START_BIT)

/* default value of ID (0x00) */
/* #define AW_PID_2308_ID_DEFAULT		(0x2308) */

/* SYSST (0x01) detail */
/* OVP2S bit 15 (SYSST 0x01) */
#define AW_PID_2308_OVP2S_START_BIT		(15)
#define AW_PID_2308_OVP2S_BITS_LEN		(1)
#define AW_PID_2308_OVP2S_MASK			\
	(~(((1<<AW_PID_2308_OVP2S_BITS_LEN)-1) << AW_PID_2308_OVP2S_START_BIT))

#define AW_PID_2308_OVP2S_NORMAL		(0)
#define AW_PID_2308_OVP2S_NORMAL_VALUE	\
	(AW_PID_2308_OVP2S_NORMAL << AW_PID_2308_OVP2S_START_BIT)

#define AW_PID_2308_OVP2S_OVP			(1)
#define AW_PID_2308_OVP2S_OVP_VALUE		\
	(AW_PID_2308_OVP2S_OVP << AW_PID_2308_OVP2S_START_BIT)

#define AW_PID_2308_OVP2S_DEFAULT		(0)
#define AW_PID_2308_OVP2S_DEFAULT_VALUE	\
	(AW_PID_2308_OVP2S_DEFAULT << AW_PID_2308_OVP2S_START_BIT)

/* UVLS bit 14 (SYSST 0x01) */
#define AW_PID_2308_UVLS_START_BIT		(14)
#define AW_PID_2308_UVLS_BITS_LEN		(1)
#define AW_PID_2308_UVLS_MASK			\
	(~(((1<<AW_PID_2308_UVLS_BITS_LEN)-1) << AW_PID_2308_UVLS_START_BIT))

#define AW_PID_2308_UVLS_NORMAL			(0)
#define AW_PID_2308_UVLS_NORMAL_VALUE	\
	(AW_PID_2308_UVLS_NORMAL << AW_PID_2308_UVLS_START_BIT)

#define AW_PID_2308_UVLS_UVLO			(1)
#define AW_PID_2308_UVLS_UVLO_VALUE		\
	(AW_PID_2308_UVLS_UVLO << AW_PID_2308_UVLS_START_BIT)

#define AW_PID_2308_UVLS_DEFAULT		(0)
#define AW_PID_2308_UVLS_DEFAULT_VALUE	\
	(AW_PID_2308_UVLS_DEFAULT << AW_PID_2308_UVLS_START_BIT)

/* ADPS bit 13 (SYSST 0x01) */
#define AW_PID_2308_ADPS_START_BIT		(13)
#define AW_PID_2308_ADPS_BITS_LEN		(1)
#define AW_PID_2308_ADPS_MASK			\
	(~(((1<<AW_PID_2308_ADPS_BITS_LEN)-1) << AW_PID_2308_ADPS_START_BIT))

#define AW_PID_2308_ADPS_PASS_THROUGH	(0)
#define AW_PID_2308_ADPS_PASS_THROUGH_VALUE	\
	(AW_PID_2308_ADPS_PASS_THROUGH << AW_PID_2308_ADPS_START_BIT)

#define AW_PID_2308_ADPS_BOOST			(1)
#define AW_PID_2308_ADPS_BOOST_VALUE	\
	(AW_PID_2308_ADPS_BOOST << AW_PID_2308_ADPS_START_BIT)

#define AW_PID_2308_ADPS_DEFAULT		(0)
#define AW_PID_2308_ADPS_DEFAULT_VALUE	\
	(AW_PID_2308_ADPS_DEFAULT << AW_PID_2308_ADPS_START_BIT)

/* OCPSMS bit 12 (SYSST 0x01) */
#define AW_PID_2308_OCPSMS_START_BIT	(12)
#define AW_PID_2308_OCPSMS_BITS_LEN		(1)
#define AW_PID_2308_OCPSMS_MASK			\
	(~(((1<<AW_PID_2308_OCPSMS_BITS_LEN)-1) << AW_PID_2308_OCPSMS_START_BIT))

#define AW_PID_2308_OCPSMS_NORMAL		(0)
#define AW_PID_2308_OCPSMS_NORMAL_VALUE	\
	(AW_PID_2308_OCPSMS_NORMAL << AW_PID_2308_OCPSMS_START_BIT)

#define AW_PID_2308_OCPSMS_OCPSM		(1)
#define AW_PID_2308_OCPSMS_OCPSM_VALUE	\
	(AW_PID_2308_OCPSMS_OCPSM << AW_PID_2308_OCPSMS_START_BIT)

#define AW_PID_2308_OCPSMS_DEFAULT		(0)
#define AW_PID_2308_OCPSMS_DEFAULT_VALUE	\
	(AW_PID_2308_OCPSMS_DEFAULT << AW_PID_2308_OCPSMS_START_BIT)

/* BSTOCS bit 11 (SYSST 0x01) */
#define AW_PID_2308_BSTOCS_START_BIT	(11)
#define AW_PID_2308_BSTOCS_BITS_LEN		(1)
#define AW_PID_2308_BSTOCS_MASK			\
	(~(((1<<AW_PID_2308_BSTOCS_BITS_LEN)-1) << AW_PID_2308_BSTOCS_START_BIT))

#define AW_PID_2308_BSTOCS_NORMAL		(0)
#define AW_PID_2308_BSTOCS_NORMAL_VALUE	\
	(AW_PID_2308_BSTOCS_NORMAL << AW_PID_2308_BSTOCS_START_BIT)

#define AW_PID_2308_BSTOCS_OVER_CURRENT	(1)
#define AW_PID_2308_BSTOCS_OVER_CURRENT_VALUE	\
	(AW_PID_2308_BSTOCS_OVER_CURRENT << AW_PID_2308_BSTOCS_START_BIT)

#define AW_PID_2308_BSTOCS_DEFAULT		(0)
#define AW_PID_2308_BSTOCS_DEFAULT_VALUE	\
	(AW_PID_2308_BSTOCS_DEFAULT << AW_PID_2308_BSTOCS_START_BIT)

/* OVPS bit 10 (SYSST 0x01) */
#define AW_PID_2308_OVPS_START_BIT		(10)
#define AW_PID_2308_OVPS_BITS_LEN		(1)
#define AW_PID_2308_OVPS_MASK			\
	(~(((1<<AW_PID_2308_OVPS_BITS_LEN)-1) << AW_PID_2308_OVPS_START_BIT))

#define AW_PID_2308_OVPS_NORMAL			(0)
#define AW_PID_2308_OVPS_NORMAL_VALUE	\
	(AW_PID_2308_OVPS_NORMAL << AW_PID_2308_OVPS_START_BIT)

#define AW_PID_2308_OVPS_OVP			(1)
#define AW_PID_2308_OVPS_OVP_VALUE		\
	(AW_PID_2308_OVPS_OVP << AW_PID_2308_OVPS_START_BIT)

#define AW_PID_2308_OVPS_DEFAULT		(0)
#define AW_PID_2308_OVPS_DEFAULT_VALUE	\
	(AW_PID_2308_OVPS_DEFAULT << AW_PID_2308_OVPS_START_BIT)

/* BSTS bit 9 (SYSST 0x01) */
#define AW_PID_2308_BSTS_START_BIT		(9)
#define AW_PID_2308_BSTS_BITS_LEN		(1)
#define AW_PID_2308_BSTS_MASK			\
	(~(((1<<AW_PID_2308_BSTS_BITS_LEN)-1) << AW_PID_2308_BSTS_START_BIT))

#define AW_PID_2308_BSTS_NOT_FINISHED	(0)
#define AW_PID_2308_BSTS_NOT_FINISHED_VALUE	\
	(AW_PID_2308_BSTS_NOT_FINISHED << AW_PID_2308_BSTS_START_BIT)

#define AW_PID_2308_BSTS_FINISHED		(1)
#define AW_PID_2308_BSTS_FINISHED_VALUE	\
	(AW_PID_2308_BSTS_FINISHED << AW_PID_2308_BSTS_START_BIT)

#define AW_PID_2308_BSTS_DEFAULT		(0)
#define AW_PID_2308_BSTS_DEFAULT_VALUE	\
	(AW_PID_2308_BSTS_DEFAULT << AW_PID_2308_BSTS_START_BIT)

/* SWS bit 8 (SYSST 0x01) */
#define AW_PID_2308_SWS_START_BIT		(8)
#define AW_PID_2308_SWS_BITS_LEN		(1)
#define AW_PID_2308_SWS_MASK			\
	(~(((1<<AW_PID_2308_SWS_BITS_LEN)-1) << AW_PID_2308_SWS_START_BIT))

#define AW_PID_2308_SWS_NOT_SWITCHING	(0)
#define AW_PID_2308_SWS_NOT_SWITCHING_VALUE	\
	(AW_PID_2308_SWS_NOT_SWITCHING << AW_PID_2308_SWS_START_BIT)

#define AW_PID_2308_SWS_SWITCHING		(1)
#define AW_PID_2308_SWS_SWITCHING_VALUE	\
	(AW_PID_2308_SWS_SWITCHING << AW_PID_2308_SWS_START_BIT)

#define AW_PID_2308_SWS_DEFAULT			(0)
#define AW_PID_2308_SWS_DEFAULT_VALUE	\
	(AW_PID_2308_SWS_DEFAULT << AW_PID_2308_SWS_START_BIT)

/* ODCS bit 7 (SYSST 0x01) */
#define AW_PID_2308_ODCS_START_BIT		(7)
#define AW_PID_2308_ODCS_BITS_LEN		(1)
#define AW_PID_2308_ODCS_MASK			\
	(~(((1<<AW_PID_2308_ODCS_BITS_LEN)-1) << AW_PID_2308_ODCS_START_BIT))

#define AW_PID_2308_ODCS_NORMAL			(0)
#define AW_PID_2308_ODCS_NORMAL_VALUE	\
	(AW_PID_2308_ODCS_NORMAL << AW_PID_2308_ODCS_START_BIT)

#define AW_PID_2308_ODCS_ODC			(1)
#define AW_PID_2308_ODCS_ODC_VALUE		\
	(AW_PID_2308_ODCS_ODC << AW_PID_2308_ODCS_START_BIT)

#define AW_PID_2308_ODCS_DEFAULT		(0)
#define AW_PID_2308_ODCS_DEFAULT_VALUE	\
	(AW_PID_2308_ODCS_DEFAULT << AW_PID_2308_ODCS_START_BIT)

/* OVPPSMS bit 6 (SYSST 0x01) */
#define AW_PID_2308_OVPPSMS_START_BIT	(6)
#define AW_PID_2308_OVPPSMS_BITS_LEN	(1)
#define AW_PID_2308_OVPPSMS_MASK		\
	(~(((1<<AW_PID_2308_OVPPSMS_BITS_LEN)-1) << AW_PID_2308_OVPPSMS_START_BIT))

#define AW_PID_2308_OVPPSMS_NORMAL		(0)
#define AW_PID_2308_OVPPSMS_NORMAL_VALUE	\
	(AW_PID_2308_OVPPSMS_NORMAL << AW_PID_2308_OVPPSMS_START_BIT)

#define AW_PID_2308_OVPPSMS_OVPPSM		(1)
#define AW_PID_2308_OVPPSMS_OVPPSM_VALUE	\
	(AW_PID_2308_OVPPSMS_OVPPSM << AW_PID_2308_OVPPSMS_START_BIT)

#define AW_PID_2308_OVPPSMS_DEFAULT		(0)
#define AW_PID_2308_OVPPSMS_DEFAULT_VALUE	\
	(AW_PID_2308_OVPPSMS_DEFAULT << AW_PID_2308_OVPPSMS_START_BIT)

/* NOCLKS bit 5 (SYSST 0x01) */
#define AW_PID_2308_NOCLKS_START_BIT	(5)
#define AW_PID_2308_NOCLKS_BITS_LEN		(1)
#define AW_PID_2308_NOCLKS_MASK			\
	(~(((1<<AW_PID_2308_NOCLKS_BITS_LEN)-1) << AW_PID_2308_NOCLKS_START_BIT))

#define AW_PID_2308_NOCLKS_CLOCK_OK		(0)
#define AW_PID_2308_NOCLKS_CLOCK_OK_VALUE	\
	(AW_PID_2308_NOCLKS_CLOCK_OK << AW_PID_2308_NOCLKS_START_BIT)

#define AW_PID_2308_NOCLKS_NO_CLOCK		(1)
#define AW_PID_2308_NOCLKS_NO_CLOCK_VALUE	\
	(AW_PID_2308_NOCLKS_NO_CLOCK << AW_PID_2308_NOCLKS_START_BIT)

#define AW_PID_2308_NOCLKS_DEFAULT		(0)
#define AW_PID_2308_NOCLKS_DEFAULT_VALUE	\
	(AW_PID_2308_NOCLKS_DEFAULT << AW_PID_2308_NOCLKS_START_BIT)

/* CLKS bit 4 (SYSST 0x01) */
#define AW_PID_2308_CLKS_START_BIT		(4)
#define AW_PID_2308_CLKS_BITS_LEN		(1)
#define AW_PID_2308_CLKS_MASK			\
	(~(((1<<AW_PID_2308_CLKS_BITS_LEN)-1) << AW_PID_2308_CLKS_START_BIT))

#define AW_PID_2308_CLKS_NOT_STABLE		(0)
#define AW_PID_2308_CLKS_NOT_STABLE_VALUE	\
	(AW_PID_2308_CLKS_NOT_STABLE << AW_PID_2308_CLKS_START_BIT)

#define AW_PID_2308_CLKS_STABLE			(1)
#define AW_PID_2308_CLKS_STABLE_VALUE	\
	(AW_PID_2308_CLKS_STABLE << AW_PID_2308_CLKS_START_BIT)

#define AW_PID_2308_CLKS_DEFAULT		(0)
#define AW_PID_2308_CLKS_DEFAULT_VALUE	\
	(AW_PID_2308_CLKS_DEFAULT << AW_PID_2308_CLKS_START_BIT)

/* OCDS bit 3 (SYSST 0x01) */
#define AW_PID_2308_OCDS_START_BIT		(3)
#define AW_PID_2308_OCDS_BITS_LEN		(1)
#define AW_PID_2308_OCDS_MASK			\
	(~(((1<<AW_PID_2308_OCDS_BITS_LEN)-1) << AW_PID_2308_OCDS_START_BIT))

#define AW_PID_2308_OCDS_NORMAL			(0)
#define AW_PID_2308_OCDS_NORMAL_VALUE	\
	(AW_PID_2308_OCDS_NORMAL << AW_PID_2308_OCDS_START_BIT)

#define AW_PID_2308_OCDS_OC				(1)
#define AW_PID_2308_OCDS_OC_VALUE		\
	(AW_PID_2308_OCDS_OC << AW_PID_2308_OCDS_START_BIT)

#define AW_PID_2308_OCDS_DEFAULT		(0)
#define AW_PID_2308_OCDS_DEFAULT_VALUE	\
	(AW_PID_2308_OCDS_DEFAULT << AW_PID_2308_OCDS_START_BIT)

/* BROWN_OUTS bit 2 (SYSST 0x01) */
#define AW_PID_2308_BROWN_OUTS_START_BIT	(2)
#define AW_PID_2308_BROWN_OUTS_BITS_LEN	(1)
#define AW_PID_2308_BROWN_OUTS_MASK		\
	(~(((1<<AW_PID_2308_BROWN_OUTS_BITS_LEN)-1) << AW_PID_2308_BROWN_OUTS_START_BIT))

#define AW_PID_2308_BROWN_OUTS_NOT_ACTIVATED	(0)
#define AW_PID_2308_BROWN_OUTS_NOT_ACTIVATED_VALUE	\
	(AW_PID_2308_BROWN_OUTS_NOT_ACTIVATED << AW_PID_2308_BROWN_OUTS_START_BIT)

#define AW_PID_2308_BROWN_OUTS_ACTIVATED	(1)
#define AW_PID_2308_BROWN_OUTS_ACTIVATED_VALUE	\
	(AW_PID_2308_BROWN_OUTS_ACTIVATED << AW_PID_2308_BROWN_OUTS_START_BIT)

#define AW_PID_2308_BROWN_OUTS_DEFAULT	(0)
#define AW_PID_2308_BROWN_OUTS_DEFAULT_VALUE	\
	(AW_PID_2308_BROWN_OUTS_DEFAULT << AW_PID_2308_BROWN_OUTS_START_BIT)

/* OTHS bit 1 (SYSST 0x01) */
#define AW_PID_2308_OTHS_START_BIT		(1)
#define AW_PID_2308_OTHS_BITS_LEN		(1)
#define AW_PID_2308_OTHS_MASK			\
	(~(((1<<AW_PID_2308_OTHS_BITS_LEN)-1) << AW_PID_2308_OTHS_START_BIT))

#define AW_PID_2308_OTHS_NORMAL			(0)
#define AW_PID_2308_OTHS_NORMAL_VALUE	\
	(AW_PID_2308_OTHS_NORMAL << AW_PID_2308_OTHS_START_BIT)

#define AW_PID_2308_OTHS_OT				(1)
#define AW_PID_2308_OTHS_OT_VALUE		\
	(AW_PID_2308_OTHS_OT << AW_PID_2308_OTHS_START_BIT)

#define AW_PID_2308_OTHS_DEFAULT		(0)
#define AW_PID_2308_OTHS_DEFAULT_VALUE	\
	(AW_PID_2308_OTHS_DEFAULT << AW_PID_2308_OTHS_START_BIT)

/* PLLS bit 0 (SYSST 0x01) */
#define AW_PID_2308_PLLS_START_BIT		(0)
#define AW_PID_2308_PLLS_BITS_LEN		(1)
#define AW_PID_2308_PLLS_MASK			\
	(~(((1<<AW_PID_2308_PLLS_BITS_LEN)-1) << AW_PID_2308_PLLS_START_BIT))

#define AW_PID_2308_PLLS_UNLOCKED		(0)
#define AW_PID_2308_PLLS_UNLOCKED_VALUE	\
	(AW_PID_2308_PLLS_UNLOCKED << AW_PID_2308_PLLS_START_BIT)

#define AW_PID_2308_PLLS_LOCKED			(1)
#define AW_PID_2308_PLLS_LOCKED_VALUE	\
	(AW_PID_2308_PLLS_LOCKED << AW_PID_2308_PLLS_START_BIT)

#define AW_PID_2308_PLLS_DEFAULT		(0)
#define AW_PID_2308_PLLS_DEFAULT_VALUE	\
	(AW_PID_2308_PLLS_DEFAULT << AW_PID_2308_PLLS_START_BIT)

#define AW_PID_2308_SYSST_CHECK_MASK \
	(~(AW_PID_2308_UVLS_UVLO_VALUE | \
	AW_PID_2308_BSTOCS_OVER_CURRENT_VALUE | \
	AW_PID_2308_BSTS_FINISHED_VALUE | \
	AW_PID_2308_SWS_SWITCHING_VALUE | \
	AW_PID_2308_NOCLKS_NO_CLOCK_VALUE | \
	AW_PID_2308_CLKS_STABLE_VALUE | \
	AW_PID_2308_OCDS_OC_VALUE | \
	AW_PID_2308_OTHS_OT_VALUE | \
	AW_PID_2308_PLLS_LOCKED_VALUE))

#define AW_PID_2308_NO_SWS_SYSST_CHECK \
	(AW_PID_2308_BSTS_FINISHED_VALUE | \
	AW_PID_2308_CLKS_STABLE_VALUE | \
	AW_PID_2308_PLLS_LOCKED_VALUE)

#define AW_PID_2308_SWS_SYSST_CHECK \
	(AW_PID_2308_BSTS_FINISHED_VALUE | \
	AW_PID_2308_SWS_SWITCHING_VALUE | \
	AW_PID_2308_CLKS_STABLE_VALUE | \
	AW_PID_2308_PLLS_LOCKED_VALUE)

#define AW_PID_2308_IIS_CHECK \
	(AW_PID_2308_CLKS_STABLE_VALUE | \
	AW_PID_2308_PLLS_LOCKED_VALUE)
/* default value of SYSST (0x01) */
/* #define AW_PID_2308_SYSST_DEFAULT		(0x0000) */

/* SYSINT (0x02) detail */
/* OVP2I bit 15 (SYSINT 0x02) */
#define AW_PID_2308_OVP2I_START_BIT		(15)
#define AW_PID_2308_OVP2I_BITS_LEN		(1)
#define AW_PID_2308_OVP2I_MASK			\
	(~(((1<<AW_PID_2308_OVP2I_BITS_LEN)-1) << AW_PID_2308_OVP2I_START_BIT))

#define AW_PID_2308_OVP2I_DEFAULT		(0)
#define AW_PID_2308_OVP2I_DEFAULT_VALUE	\
	(AW_PID_2308_OVP2I_DEFAULT << AW_PID_2308_OVP2I_START_BIT)

/* UVLI bit 14 (SYSINT 0x02) */
#define AW_PID_2308_UVLI_START_BIT		(14)
#define AW_PID_2308_UVLI_BITS_LEN		(1)
#define AW_PID_2308_UVLI_MASK			\
	(~(((1<<AW_PID_2308_UVLI_BITS_LEN)-1) << AW_PID_2308_UVLI_START_BIT))

#define AW_PID_2308_UVLI_DEFAULT		(0)
#define AW_PID_2308_UVLI_DEFAULT_VALUE	\
	(AW_PID_2308_UVLI_DEFAULT << AW_PID_2308_UVLI_START_BIT)

/* ADPI bit 13 (SYSINT 0x02) */
#define AW_PID_2308_ADPI_START_BIT		(13)
#define AW_PID_2308_ADPI_BITS_LEN		(1)
#define AW_PID_2308_ADPI_MASK			\
	(~(((1<<AW_PID_2308_ADPI_BITS_LEN)-1) << AW_PID_2308_ADPI_START_BIT))

#define AW_PID_2308_ADPI_DEFAULT		(0)
#define AW_PID_2308_ADPI_DEFAULT_VALUE	\
	(AW_PID_2308_ADPI_DEFAULT << AW_PID_2308_ADPI_START_BIT)

/* OCPSMI bit 12 (SYSINT 0x02) */
#define AW_PID_2308_OCPSMI_START_BIT	(12)
#define AW_PID_2308_OCPSMI_BITS_LEN		(1)
#define AW_PID_2308_OCPSMI_MASK			\
	(~(((1<<AW_PID_2308_OCPSMI_BITS_LEN)-1) << AW_PID_2308_OCPSMI_START_BIT))

#define AW_PID_2308_OCPSMI_DEFAULT		(0)
#define AW_PID_2308_OCPSMI_DEFAULT_VALUE	\
	(AW_PID_2308_OCPSMI_DEFAULT << AW_PID_2308_OCPSMI_START_BIT)

/* BSTOCI bit 11 (SYSINT 0x02) */
#define AW_PID_2308_BSTOCI_START_BIT	(11)
#define AW_PID_2308_BSTOCI_BITS_LEN		(1)
#define AW_PID_2308_BSTOCI_MASK			\
	(~(((1<<AW_PID_2308_BSTOCI_BITS_LEN)-1) << AW_PID_2308_BSTOCI_START_BIT))

#define AW_PID_2308_BSTOCI_DEFAULT		(0)
#define AW_PID_2308_BSTOCI_DEFAULT_VALUE	\
	(AW_PID_2308_BSTOCI_DEFAULT << AW_PID_2308_BSTOCI_START_BIT)

/* OVPI bit 10 (SYSINT 0x02) */
#define AW_PID_2308_OVPI_START_BIT		(10)
#define AW_PID_2308_OVPI_BITS_LEN		(1)
#define AW_PID_2308_OVPI_MASK			\
	(~(((1<<AW_PID_2308_OVPI_BITS_LEN)-1) << AW_PID_2308_OVPI_START_BIT))

#define AW_PID_2308_OVPI_DEFAULT		(0)
#define AW_PID_2308_OVPI_DEFAULT_VALUE	\
	(AW_PID_2308_OVPI_DEFAULT << AW_PID_2308_OVPI_START_BIT)

/* BSTI bit 9 (SYSINT 0x02) */
#define AW_PID_2308_BSTI_START_BIT		(9)
#define AW_PID_2308_BSTI_BITS_LEN		(1)
#define AW_PID_2308_BSTI_MASK			\
	(~(((1<<AW_PID_2308_BSTI_BITS_LEN)-1) << AW_PID_2308_BSTI_START_BIT))

#define AW_PID_2308_BSTI_DEFAULT		(0)
#define AW_PID_2308_BSTI_DEFAULT_VALUE	\
	(AW_PID_2308_BSTI_DEFAULT << AW_PID_2308_BSTI_START_BIT)

/* SWI bit 8 (SYSINT 0x02) */
#define AW_PID_2308_SWI_START_BIT		(8)
#define AW_PID_2308_SWI_BITS_LEN		(1)
#define AW_PID_2308_SWI_MASK			\
	(~(((1<<AW_PID_2308_SWI_BITS_LEN)-1) << AW_PID_2308_SWI_START_BIT))

#define AW_PID_2308_SWI_DEFAULT			(0)
#define AW_PID_2308_SWI_DEFAULT_VALUE	\
	(AW_PID_2308_SWI_DEFAULT << AW_PID_2308_SWI_START_BIT)

/* ODCI bit 7 (SYSINT 0x02) */
#define AW_PID_2308_ODCI_START_BIT		(7)
#define AW_PID_2308_ODCI_BITS_LEN		(1)
#define AW_PID_2308_ODCI_MASK			\
	(~(((1<<AW_PID_2308_ODCI_BITS_LEN)-1) << AW_PID_2308_ODCI_START_BIT))

#define AW_PID_2308_ODCI_DEFAULT		(0)
#define AW_PID_2308_ODCI_DEFAULT_VALUE	\
	(AW_PID_2308_ODCI_DEFAULT << AW_PID_2308_ODCI_START_BIT)

/* OVPPSMI bit 6 (SYSINT 0x02) */
#define AW_PID_2308_OVPPSMI_START_BIT	(6)
#define AW_PID_2308_OVPPSMI_BITS_LEN	(1)
#define AW_PID_2308_OVPPSMI_MASK		\
	(~(((1<<AW_PID_2308_OVPPSMI_BITS_LEN)-1) << AW_PID_2308_OVPPSMI_START_BIT))

#define AW_PID_2308_OVPPSMI_DEFAULT		(0)
#define AW_PID_2308_OVPPSMI_DEFAULT_VALUE	\
	(AW_PID_2308_OVPPSMI_DEFAULT << AW_PID_2308_OVPPSMI_START_BIT)

/* NOCLKI bit 5 (SYSINT 0x02) */
#define AW_PID_2308_NOCLKI_START_BIT	(5)
#define AW_PID_2308_NOCLKI_BITS_LEN		(1)
#define AW_PID_2308_NOCLKI_MASK			\
	(~(((1<<AW_PID_2308_NOCLKI_BITS_LEN)-1) << AW_PID_2308_NOCLKI_START_BIT))

#define AW_PID_2308_NOCLKI_DEFAULT		(0)
#define AW_PID_2308_NOCLKI_DEFAULT_VALUE	\
	(AW_PID_2308_NOCLKI_DEFAULT << AW_PID_2308_NOCLKI_START_BIT)

/* CLKI bit 4 (SYSINT 0x02) */
#define AW_PID_2308_CLKI_START_BIT		(4)
#define AW_PID_2308_CLKI_BITS_LEN		(1)
#define AW_PID_2308_CLKI_MASK			\
	(~(((1<<AW_PID_2308_CLKI_BITS_LEN)-1) << AW_PID_2308_CLKI_START_BIT))

#define AW_PID_2308_CLKI_DEFAULT		(0)
#define AW_PID_2308_CLKI_DEFAULT_VALUE	\
	(AW_PID_2308_CLKI_DEFAULT << AW_PID_2308_CLKI_START_BIT)

/* OCDI bit 3 (SYSINT 0x02) */
#define AW_PID_2308_OCDI_START_BIT		(3)
#define AW_PID_2308_OCDI_BITS_LEN		(1)
#define AW_PID_2308_OCDI_MASK			\
	(~(((1<<AW_PID_2308_OCDI_BITS_LEN)-1) << AW_PID_2308_OCDI_START_BIT))

#define AW_PID_2308_OCDI_DEFAULT		(0)
#define AW_PID_2308_OCDI_DEFAULT_VALUE	\
	(AW_PID_2308_OCDI_DEFAULT << AW_PID_2308_OCDI_START_BIT)

/* BROWN_OUTI bit 2 (SYSINT 0x02) */
#define AW_PID_2308_BROWN_OUTI_START_BIT	(2)
#define AW_PID_2308_BROWN_OUTI_BITS_LEN	(1)
#define AW_PID_2308_BROWN_OUTI_MASK		\
	(~(((1<<AW_PID_2308_BROWN_OUTI_BITS_LEN)-1) << AW_PID_2308_BROWN_OUTI_START_BIT))

#define AW_PID_2308_BROWN_OUTI_DEFAULT	(0)
#define AW_PID_2308_BROWN_OUTI_DEFAULT_VALUE	\
	(AW_PID_2308_BROWN_OUTI_DEFAULT << AW_PID_2308_BROWN_OUTI_START_BIT)

/* OTHI bit 1 (SYSINT 0x02) */
#define AW_PID_2308_OTHI_START_BIT		(1)
#define AW_PID_2308_OTHI_BITS_LEN		(1)
#define AW_PID_2308_OTHI_MASK			\
	(~(((1<<AW_PID_2308_OTHI_BITS_LEN)-1) << AW_PID_2308_OTHI_START_BIT))

#define AW_PID_2308_OTHI_DEFAULT		(0)
#define AW_PID_2308_OTHI_DEFAULT_VALUE	\
	(AW_PID_2308_OTHI_DEFAULT << AW_PID_2308_OTHI_START_BIT)

/* PLLI bit 0 (SYSINT 0x02) */
#define AW_PID_2308_PLLI_START_BIT		(0)
#define AW_PID_2308_PLLI_BITS_LEN		(1)
#define AW_PID_2308_PLLI_MASK			\
	(~(((1<<AW_PID_2308_PLLI_BITS_LEN)-1) << AW_PID_2308_PLLI_START_BIT))

#define AW_PID_2308_PLLI_DEFAULT		(0)
#define AW_PID_2308_PLLI_DEFAULT_VALUE	\
	(AW_PID_2308_PLLI_DEFAULT << AW_PID_2308_PLLI_START_BIT)

/* default value of SYSINT (0x02) */
/* #define AW_PID_2308_SYSINT_DEFAULT		(0x0000) */

/* SYSINTM (0x03) detail */
/* OVP2M bit 15 (SYSINTM 0x03) */
#define AW_PID_2308_OVP2M_START_BIT		(15)
#define AW_PID_2308_OVP2M_BITS_LEN		(1)
#define AW_PID_2308_OVP2M_MASK			\
	(~(((1<<AW_PID_2308_OVP2M_BITS_LEN)-1) << AW_PID_2308_OVP2M_START_BIT))

#define AW_PID_2308_OVP2M_DEFAULT		(1)
#define AW_PID_2308_OVP2M_DEFAULT_VALUE	\
	(AW_PID_2308_OVP2M_DEFAULT << AW_PID_2308_OVP2M_START_BIT)

/* UVLM bit 14 (SYSINTM 0x03) */
#define AW_PID_2308_UVLM_START_BIT		(14)
#define AW_PID_2308_UVLM_BITS_LEN		(1)
#define AW_PID_2308_UVLM_MASK			\
	(~(((1<<AW_PID_2308_UVLM_BITS_LEN)-1) << AW_PID_2308_UVLM_START_BIT))

#define AW_PID_2308_UVLM_DEFAULT		(1)
#define AW_PID_2308_UVLM_DEFAULT_VALUE	\
	(AW_PID_2308_UVLM_DEFAULT << AW_PID_2308_UVLM_START_BIT)

/* ADPM bit 13 (SYSINTM 0x03) */
#define AW_PID_2308_ADPM_START_BIT		(13)
#define AW_PID_2308_ADPM_BITS_LEN		(1)
#define AW_PID_2308_ADPM_MASK			\
	(~(((1<<AW_PID_2308_ADPM_BITS_LEN)-1) << AW_PID_2308_ADPM_START_BIT))

#define AW_PID_2308_ADPM_DEFAULT		(1)
#define AW_PID_2308_ADPM_DEFAULT_VALUE	\
	(AW_PID_2308_ADPM_DEFAULT << AW_PID_2308_ADPM_START_BIT)

/* OCPSMM bit 12 (SYSINTM 0x03) */
#define AW_PID_2308_OCPSMM_START_BIT	(12)
#define AW_PID_2308_OCPSMM_BITS_LEN		(1)
#define AW_PID_2308_OCPSMM_MASK			\
	(~(((1<<AW_PID_2308_OCPSMM_BITS_LEN)-1) << AW_PID_2308_OCPSMM_START_BIT))

#define AW_PID_2308_OCPSMM_DEFAULT		(1)
#define AW_PID_2308_OCPSMM_DEFAULT_VALUE	\
	(AW_PID_2308_OCPSMM_DEFAULT << AW_PID_2308_OCPSMM_START_BIT)

/* BSTOCM bit 11 (SYSINTM 0x03) */
#define AW_PID_2308_BSTOCM_START_BIT	(11)
#define AW_PID_2308_BSTOCM_BITS_LEN		(1)
#define AW_PID_2308_BSTOCM_MASK			\
	(~(((1<<AW_PID_2308_BSTOCM_BITS_LEN)-1) << AW_PID_2308_BSTOCM_START_BIT))

#define AW_PID_2308_BSTOCM_DEFAULT		(1)
#define AW_PID_2308_BSTOCM_DEFAULT_VALUE	\
	(AW_PID_2308_BSTOCM_DEFAULT << AW_PID_2308_BSTOCM_START_BIT)

/* OVPM bit 10 (SYSINTM 0x03) */
#define AW_PID_2308_OVPM_START_BIT		(10)
#define AW_PID_2308_OVPM_BITS_LEN		(1)
#define AW_PID_2308_OVPM_MASK			\
	(~(((1<<AW_PID_2308_OVPM_BITS_LEN)-1) << AW_PID_2308_OVPM_START_BIT))

#define AW_PID_2308_OVPM_DEFAULT		(1)
#define AW_PID_2308_OVPM_DEFAULT_VALUE	\
	(AW_PID_2308_OVPM_DEFAULT << AW_PID_2308_OVPM_START_BIT)

/* BSTM bit 9 (SYSINTM 0x03) */
#define AW_PID_2308_BSTM_START_BIT		(9)
#define AW_PID_2308_BSTM_BITS_LEN		(1)
#define AW_PID_2308_BSTM_MASK			\
	(~(((1<<AW_PID_2308_BSTM_BITS_LEN)-1) << AW_PID_2308_BSTM_START_BIT))

#define AW_PID_2308_BSTM_DEFAULT		(1)
#define AW_PID_2308_BSTM_DEFAULT_VALUE	\
	(AW_PID_2308_BSTM_DEFAULT << AW_PID_2308_BSTM_START_BIT)

/* SWM bit 8 (SYSINTM 0x03) */
#define AW_PID_2308_SWM_START_BIT		(8)
#define AW_PID_2308_SWM_BITS_LEN		(1)
#define AW_PID_2308_SWM_MASK			\
	(~(((1<<AW_PID_2308_SWM_BITS_LEN)-1) << AW_PID_2308_SWM_START_BIT))

#define AW_PID_2308_SWM_DEFAULT			(1)
#define AW_PID_2308_SWM_DEFAULT_VALUE	\
	(AW_PID_2308_SWM_DEFAULT << AW_PID_2308_SWM_START_BIT)

/* ODCM bit 7 (SYSINTM 0x03) */
#define AW_PID_2308_ODCM_START_BIT		(7)
#define AW_PID_2308_ODCM_BITS_LEN		(1)
#define AW_PID_2308_ODCM_MASK			\
	(~(((1<<AW_PID_2308_ODCM_BITS_LEN)-1) << AW_PID_2308_ODCM_START_BIT))

#define AW_PID_2308_ODCM_DEFAULT		(1)
#define AW_PID_2308_ODCM_DEFAULT_VALUE	\
	(AW_PID_2308_ODCM_DEFAULT << AW_PID_2308_ODCM_START_BIT)

/* OVPPSMM bit 6 (SYSINTM 0x03) */
#define AW_PID_2308_OVPPSMM_START_BIT	(6)
#define AW_PID_2308_OVPPSMM_BITS_LEN	(1)
#define AW_PID_2308_OVPPSMM_MASK		\
	(~(((1<<AW_PID_2308_OVPPSMM_BITS_LEN)-1) << AW_PID_2308_OVPPSMM_START_BIT))

#define AW_PID_2308_OVPPSMM_DEFAULT		(1)
#define AW_PID_2308_OVPPSMM_DEFAULT_VALUE	\
	(AW_PID_2308_OVPPSMM_DEFAULT << AW_PID_2308_OVPPSMM_START_BIT)

/* NOCLKM bit 5 (SYSINTM 0x03) */
#define AW_PID_2308_NOCLKM_START_BIT	(5)
#define AW_PID_2308_NOCLKM_BITS_LEN		(1)
#define AW_PID_2308_NOCLKM_MASK			\
	(~(((1<<AW_PID_2308_NOCLKM_BITS_LEN)-1) << AW_PID_2308_NOCLKM_START_BIT))

#define AW_PID_2308_NOCLKM_DEFAULT		(1)
#define AW_PID_2308_NOCLKM_DEFAULT_VALUE	\
	(AW_PID_2308_NOCLKM_DEFAULT << AW_PID_2308_NOCLKM_START_BIT)

/* CLKM bit 4 (SYSINTM 0x03) */
#define AW_PID_2308_CLKM_START_BIT		(4)
#define AW_PID_2308_CLKM_BITS_LEN		(1)
#define AW_PID_2308_CLKM_MASK			\
	(~(((1<<AW_PID_2308_CLKM_BITS_LEN)-1) << AW_PID_2308_CLKM_START_BIT))

#define AW_PID_2308_CLKM_DEFAULT		(1)
#define AW_PID_2308_CLKM_DEFAULT_VALUE	\
	(AW_PID_2308_CLKM_DEFAULT << AW_PID_2308_CLKM_START_BIT)

/* OCDM bit 3 (SYSINTM 0x03) */
#define AW_PID_2308_OCDM_START_BIT		(3)
#define AW_PID_2308_OCDM_BITS_LEN		(1)
#define AW_PID_2308_OCDM_MASK			\
	(~(((1<<AW_PID_2308_OCDM_BITS_LEN)-1) << AW_PID_2308_OCDM_START_BIT))

#define AW_PID_2308_OCDM_DEFAULT		(1)
#define AW_PID_2308_OCDM_DEFAULT_VALUE	\
	(AW_PID_2308_OCDM_DEFAULT << AW_PID_2308_OCDM_START_BIT)

/* BROWN_OUTM bit 2 (SYSINTM 0x03) */
#define AW_PID_2308_BROWN_OUTM_START_BIT	(2)
#define AW_PID_2308_BROWN_OUTM_BITS_LEN	(1)
#define AW_PID_2308_BROWN_OUTM_MASK		\
	(~(((1<<AW_PID_2308_BROWN_OUTM_BITS_LEN)-1) << AW_PID_2308_BROWN_OUTM_START_BIT))

#define AW_PID_2308_BROWN_OUTM_DEFAULT	(1)
#define AW_PID_2308_BROWN_OUTM_DEFAULT_VALUE	\
	(AW_PID_2308_BROWN_OUTM_DEFAULT << AW_PID_2308_BROWN_OUTM_START_BIT)

/* OTHM bit 1 (SYSINTM 0x03) */
#define AW_PID_2308_OTHM_START_BIT		(1)
#define AW_PID_2308_OTHM_BITS_LEN		(1)
#define AW_PID_2308_OTHM_MASK			\
	(~(((1<<AW_PID_2308_OTHM_BITS_LEN)-1) << AW_PID_2308_OTHM_START_BIT))

#define AW_PID_2308_OTHM_DEFAULT		(1)
#define AW_PID_2308_OTHM_DEFAULT_VALUE	\
	(AW_PID_2308_OTHM_DEFAULT << AW_PID_2308_OTHM_START_BIT)

/* PLLM bit 0 (SYSINTM 0x03) */
#define AW_PID_2308_PLLM_START_BIT		(0)
#define AW_PID_2308_PLLM_BITS_LEN		(1)
#define AW_PID_2308_PLLM_MASK			\
	(~(((1<<AW_PID_2308_PLLM_BITS_LEN)-1) << AW_PID_2308_PLLM_START_BIT))

#define AW_PID_2308_PLLM_DEFAULT		(1)
#define AW_PID_2308_PLLM_DEFAULT_VALUE	\
	(AW_PID_2308_PLLM_DEFAULT << AW_PID_2308_PLLM_START_BIT)

/* default value of SYSINTM (0x03) */
#define AW_PID_2308_SYSINTM_DEFAULT		(0xFFFF)

/* SYSCTRL (0x04) detail */
/* ULS_HMUTE bit 15 (SYSCTRL 0x04) */
#define AW_PID_2308_ULS_HMUTE_START_BIT	(15)
#define AW_PID_2308_ULS_HMUTE_BITS_LEN	(1)
#define AW_PID_2308_ULS_HMUTE_MASK		\
	(~(((1<<AW_PID_2308_ULS_HMUTE_BITS_LEN)-1) << AW_PID_2308_ULS_HMUTE_START_BIT))

#define AW_PID_2308_ULS_HMUTE_NORMAL	(0)
#define AW_PID_2308_ULS_HMUTE_NORMAL_VALUE	\
	(AW_PID_2308_ULS_HMUTE_NORMAL << AW_PID_2308_ULS_HMUTE_START_BIT)

#define AW_PID_2308_ULS_HMUTE_MUTE		(1)
#define AW_PID_2308_ULS_HMUTE_MUTE_VALUE	\
	(AW_PID_2308_ULS_HMUTE_MUTE << AW_PID_2308_ULS_HMUTE_START_BIT)

#define AW_PID_2308_ULS_HMUTE_DEFAULT	(1)
#define AW_PID_2308_ULS_HMUTE_DEFAULT_VALUE	\
	(AW_PID_2308_ULS_HMUTE_DEFAULT << AW_PID_2308_ULS_HMUTE_START_BIT)

/* I2SRXEN bit 14 (SYSCTRL 0x04) */
#define AW_PID_2308_I2SRXEN_START_BIT	(14)
#define AW_PID_2308_I2SRXEN_BITS_LEN	(1)
#define AW_PID_2308_I2SRXEN_MASK		\
	(~(((1<<AW_PID_2308_I2SRXEN_BITS_LEN)-1) << AW_PID_2308_I2SRXEN_START_BIT))

#define AW_PID_2308_I2SRXEN_DISABLE		(0)
#define AW_PID_2308_I2SRXEN_DISABLE_VALUE	\
	(AW_PID_2308_I2SRXEN_DISABLE << AW_PID_2308_I2SRXEN_START_BIT)

#define AW_PID_2308_I2SRXEN_ENABLE		(1)
#define AW_PID_2308_I2SRXEN_ENABLE_VALUE	\
	(AW_PID_2308_I2SRXEN_ENABLE << AW_PID_2308_I2SRXEN_START_BIT)

#define AW_PID_2308_I2SRXEN_DEFAULT		(1)
#define AW_PID_2308_I2SRXEN_DEFAULT_VALUE	\
	(AW_PID_2308_I2SRXEN_DEFAULT << AW_PID_2308_I2SRXEN_START_BIT)

/* I2STXEN bit 13 (SYSCTRL 0x04) */
#define AW_PID_2308_I2STXEN_START_BIT	(13)
#define AW_PID_2308_I2STXEN_BITS_LEN	(1)
#define AW_PID_2308_I2STXEN_MASK		\
	(~(((1<<AW_PID_2308_I2STXEN_BITS_LEN)-1) << AW_PID_2308_I2STXEN_START_BIT))

#define AW_PID_2308_I2STXEN_DISABLE		(0)
#define AW_PID_2308_I2STXEN_DISABLE_VALUE	\
	(AW_PID_2308_I2STXEN_DISABLE << AW_PID_2308_I2STXEN_START_BIT)

#define AW_PID_2308_I2STXEN_ENABLE		(1)
#define AW_PID_2308_I2STXEN_ENABLE_VALUE	\
	(AW_PID_2308_I2STXEN_ENABLE << AW_PID_2308_I2STXEN_START_BIT)

#define AW_PID_2308_I2STXEN_DEFAULT		(0)
#define AW_PID_2308_I2STXEN_DEFAULT_VALUE	\
	(AW_PID_2308_I2STXEN_DEFAULT << AW_PID_2308_I2STXEN_START_BIT)

/* BOP_EN bit 12 (SYSCTRL 0x04) */
#define AW_PID_2308_BOP_EN_START_BIT	(12)
#define AW_PID_2308_BOP_EN_BITS_LEN		(1)
#define AW_PID_2308_BOP_EN_MASK			\
	(~(((1<<AW_PID_2308_BOP_EN_BITS_LEN)-1) << AW_PID_2308_BOP_EN_START_BIT))

#define AW_PID_2308_BOP_EN_DISABLE		(0)
#define AW_PID_2308_BOP_EN_DISABLE_VALUE	\
	(AW_PID_2308_BOP_EN_DISABLE << AW_PID_2308_BOP_EN_START_BIT)

#define AW_PID_2308_BOP_EN_ENABLE		(1)
#define AW_PID_2308_BOP_EN_ENABLE_VALUE	\
	(AW_PID_2308_BOP_EN_ENABLE << AW_PID_2308_BOP_EN_START_BIT)

#define AW_PID_2308_BOP_EN_DEFAULT		(0)
#define AW_PID_2308_BOP_EN_DEFAULT_VALUE	\
	(AW_PID_2308_BOP_EN_DEFAULT << AW_PID_2308_BOP_EN_START_BIT)

/* RMSE bit 11 (SYSCTRL 0x04) */
#define AW_PID_2308_RMSE_START_BIT		(11)
#define AW_PID_2308_RMSE_BITS_LEN		(1)
#define AW_PID_2308_RMSE_MASK			\
	(~(((1<<AW_PID_2308_RMSE_BITS_LEN)-1) << AW_PID_2308_RMSE_START_BIT))

#define AW_PID_2308_RMSE_PEAK_AGC		(0)
#define AW_PID_2308_RMSE_PEAK_AGC_VALUE	\
	(AW_PID_2308_RMSE_PEAK_AGC << AW_PID_2308_RMSE_START_BIT)

#define AW_PID_2308_RMSE_RMS_AGC		(1)
#define AW_PID_2308_RMSE_RMS_AGC_VALUE	\
	(AW_PID_2308_RMSE_RMS_AGC << AW_PID_2308_RMSE_START_BIT)

#define AW_PID_2308_RMSE_DEFAULT		(0)
#define AW_PID_2308_RMSE_DEFAULT_VALUE	\
	(AW_PID_2308_RMSE_DEFAULT << AW_PID_2308_RMSE_START_BIT)

/* HAGCE bit 10 (SYSCTRL 0x04) */
#define AW_PID_2308_HAGCE_START_BIT		(10)
#define AW_PID_2308_HAGCE_BITS_LEN		(1)
#define AW_PID_2308_HAGCE_MASK			\
	(~(((1<<AW_PID_2308_HAGCE_BITS_LEN)-1) << AW_PID_2308_HAGCE_START_BIT))

#define AW_PID_2308_HAGCE_DISABLE		(0)
#define AW_PID_2308_HAGCE_DISABLE_VALUE	\
	(AW_PID_2308_HAGCE_DISABLE << AW_PID_2308_HAGCE_START_BIT)

#define AW_PID_2308_HAGCE_ENABLE		(1)
#define AW_PID_2308_HAGCE_ENABLE_VALUE	\
	(AW_PID_2308_HAGCE_ENABLE << AW_PID_2308_HAGCE_START_BIT)

#define AW_PID_2308_HAGCE_DEFAULT		(0)
#define AW_PID_2308_HAGCE_DEFAULT_VALUE	\
	(AW_PID_2308_HAGCE_DEFAULT << AW_PID_2308_HAGCE_START_BIT)

/* HDCCE bit 9 (SYSCTRL 0x04) */
#define AW_PID_2308_HDCCE_START_BIT		(9)
#define AW_PID_2308_HDCCE_BITS_LEN		(1)
#define AW_PID_2308_HDCCE_MASK			\
	(~(((1<<AW_PID_2308_HDCCE_BITS_LEN)-1) << AW_PID_2308_HDCCE_START_BIT))

#define AW_PID_2308_HDCCE_DISABLE		(0)
#define AW_PID_2308_HDCCE_DISABLE_VALUE	\
	(AW_PID_2308_HDCCE_DISABLE << AW_PID_2308_HDCCE_START_BIT)

#define AW_PID_2308_HDCCE_ENABLE		(1)
#define AW_PID_2308_HDCCE_ENABLE_VALUE	\
	(AW_PID_2308_HDCCE_ENABLE << AW_PID_2308_HDCCE_START_BIT)

#define AW_PID_2308_HDCCE_DEFAULT		(1)
#define AW_PID_2308_HDCCE_DEFAULT_VALUE	\
	(AW_PID_2308_HDCCE_DEFAULT << AW_PID_2308_HDCCE_START_BIT)

/* HMUTE bit 8 (SYSCTRL 0x04) */
#define AW_PID_2308_HMUTE_START_BIT		(8)
#define AW_PID_2308_HMUTE_BITS_LEN		(1)
#define AW_PID_2308_HMUTE_MASK			\
	(~(((1<<AW_PID_2308_HMUTE_BITS_LEN)-1) << AW_PID_2308_HMUTE_START_BIT))

#define AW_PID_2308_HMUTE_DISABLE		(0)
#define AW_PID_2308_HMUTE_DISABLE_VALUE	\
	(AW_PID_2308_HMUTE_DISABLE << AW_PID_2308_HMUTE_START_BIT)

#define AW_PID_2308_HMUTE_ENABLE		(1)
#define AW_PID_2308_HMUTE_ENABLE_VALUE	\
	(AW_PID_2308_HMUTE_ENABLE << AW_PID_2308_HMUTE_START_BIT)

#define AW_PID_2308_HMUTE_DEFAULT		(1)
#define AW_PID_2308_HMUTE_DEFAULT_VALUE	\
	(AW_PID_2308_HMUTE_DEFAULT << AW_PID_2308_HMUTE_START_BIT)

/* RCV_MODE bit 7 (SYSCTRL 0x04) */
#define AW_PID_2308_RCV_MODE_START_BIT	(7)
#define AW_PID_2308_RCV_MODE_BITS_LEN	(1)
#define AW_PID_2308_RCV_MODE_MASK		\
	(~(((1<<AW_PID_2308_RCV_MODE_BITS_LEN)-1) << AW_PID_2308_RCV_MODE_START_BIT))

#define AW_PID_2308_RCV_MODE_SPEAKER	(0)
#define AW_PID_2308_RCV_MODE_SPEAKER_VALUE	\
	(AW_PID_2308_RCV_MODE_SPEAKER << AW_PID_2308_RCV_MODE_START_BIT)

#define AW_PID_2308_RCV_MODE_RECEIVER	(1)
#define AW_PID_2308_RCV_MODE_RECEIVER_VALUE	\
	(AW_PID_2308_RCV_MODE_RECEIVER << AW_PID_2308_RCV_MODE_START_BIT)

#define AW_PID_2308_RCV_MODE_DEFAULT	(0)
#define AW_PID_2308_RCV_MODE_DEFAULT_VALUE	\
	(AW_PID_2308_RCV_MODE_DEFAULT << AW_PID_2308_RCV_MODE_START_BIT)

/* I2SEN bit 6 (SYSCTRL 0x04) */
#define AW_PID_2308_I2SEN_START_BIT		(6)
#define AW_PID_2308_I2SEN_BITS_LEN		(1)
#define AW_PID_2308_I2SEN_MASK			\
	(~(((1<<AW_PID_2308_I2SEN_BITS_LEN)-1) << AW_PID_2308_I2SEN_START_BIT))

#define AW_PID_2308_I2SEN_DISABLE		(0)
#define AW_PID_2308_I2SEN_DISABLE_VALUE	\
	(AW_PID_2308_I2SEN_DISABLE << AW_PID_2308_I2SEN_START_BIT)

#define AW_PID_2308_I2SEN_ENABLE		(1)
#define AW_PID_2308_I2SEN_ENABLE_VALUE	\
	(AW_PID_2308_I2SEN_ENABLE << AW_PID_2308_I2SEN_START_BIT)

#define AW_PID_2308_I2SEN_DEFAULT		(0)
#define AW_PID_2308_I2SEN_DEFAULT_VALUE	\
	(AW_PID_2308_I2SEN_DEFAULT << AW_PID_2308_I2SEN_START_BIT)

/* WSINV bit 5 (SYSCTRL 0x04) */
#define AW_PID_2308_WSINV_START_BIT		(5)
#define AW_PID_2308_WSINV_BITS_LEN		(1)
#define AW_PID_2308_WSINV_MASK			\
	(~(((1<<AW_PID_2308_WSINV_BITS_LEN)-1) << AW_PID_2308_WSINV_START_BIT))

#define AW_PID_2308_WSINV_NOT_SWITCH	(0)
#define AW_PID_2308_WSINV_NOT_SWITCH_VALUE	\
	(AW_PID_2308_WSINV_NOT_SWITCH << AW_PID_2308_WSINV_START_BIT)

#define AW_PID_2308_WSINV_SWITCH		(1)
#define AW_PID_2308_WSINV_SWITCH_VALUE	\
	(AW_PID_2308_WSINV_SWITCH << AW_PID_2308_WSINV_START_BIT)

#define AW_PID_2308_WSINV_DEFAULT		(0)
#define AW_PID_2308_WSINV_DEFAULT_VALUE	\
	(AW_PID_2308_WSINV_DEFAULT << AW_PID_2308_WSINV_START_BIT)

/* BCKINV bit 4 (SYSCTRL 0x04) */
#define AW_PID_2308_BCKINV_START_BIT	(4)
#define AW_PID_2308_BCKINV_BITS_LEN		(1)
#define AW_PID_2308_BCKINV_MASK			\
	(~(((1<<AW_PID_2308_BCKINV_BITS_LEN)-1) << AW_PID_2308_BCKINV_START_BIT))

#define AW_PID_2308_BCKINV_NOT_INVERT	(0)
#define AW_PID_2308_BCKINV_NOT_INVERT_VALUE	\
	(AW_PID_2308_BCKINV_NOT_INVERT << AW_PID_2308_BCKINV_START_BIT)

#define AW_PID_2308_BCKINV_INVERTED		(1)
#define AW_PID_2308_BCKINV_INVERTED_VALUE	\
	(AW_PID_2308_BCKINV_INVERTED << AW_PID_2308_BCKINV_START_BIT)

#define AW_PID_2308_BCKINV_DEFAULT		(0)
#define AW_PID_2308_BCKINV_DEFAULT_VALUE	\
	(AW_PID_2308_BCKINV_DEFAULT << AW_PID_2308_BCKINV_START_BIT)

/* IPLL bit 3 (SYSCTRL 0x04) */
#define AW_PID_2308_IPLL_START_BIT		(3)
#define AW_PID_2308_IPLL_BITS_LEN		(1)
#define AW_PID_2308_IPLL_MASK			\
	(~(((1<<AW_PID_2308_IPLL_BITS_LEN)-1) << AW_PID_2308_IPLL_START_BIT))

#define AW_PID_2308_IPLL_BCK			(0)
#define AW_PID_2308_IPLL_BCK_VALUE		\
	(AW_PID_2308_IPLL_BCK << AW_PID_2308_IPLL_START_BIT)

#define AW_PID_2308_IPLL_WCK			(1)
#define AW_PID_2308_IPLL_WCK_VALUE		\
	(AW_PID_2308_IPLL_WCK << AW_PID_2308_IPLL_START_BIT)

#define AW_PID_2308_IPLL_DEFAULT		(0)
#define AW_PID_2308_IPLL_DEFAULT_VALUE	\
	(AW_PID_2308_IPLL_DEFAULT << AW_PID_2308_IPLL_START_BIT)

/* AMPPD bit 1 (SYSCTRL 0x04) */
#define AW_PID_2308_AMPPD_START_BIT		(1)
#define AW_PID_2308_AMPPD_BITS_LEN		(1)
#define AW_PID_2308_AMPPD_MASK			\
	(~(((1<<AW_PID_2308_AMPPD_BITS_LEN)-1) << AW_PID_2308_AMPPD_START_BIT))

#define AW_PID_2308_AMPPD_WORKING		(0)
#define AW_PID_2308_AMPPD_WORKING_VALUE	\
	(AW_PID_2308_AMPPD_WORKING << AW_PID_2308_AMPPD_START_BIT)

#define AW_PID_2308_AMPPD_POWER_DOWN	(1)
#define AW_PID_2308_AMPPD_POWER_DOWN_VALUE	\
	(AW_PID_2308_AMPPD_POWER_DOWN << AW_PID_2308_AMPPD_START_BIT)

#define AW_PID_2308_AMPPD_DEFAULT		(1)
#define AW_PID_2308_AMPPD_DEFAULT_VALUE	\
	(AW_PID_2308_AMPPD_DEFAULT << AW_PID_2308_AMPPD_START_BIT)

/* PWDN bit 0 (SYSCTRL 0x04) */
#define AW_PID_2308_PWDN_START_BIT		(0)
#define AW_PID_2308_PWDN_BITS_LEN		(1)
#define AW_PID_2308_PWDN_MASK			\
	(~(((1<<AW_PID_2308_PWDN_BITS_LEN)-1) << AW_PID_2308_PWDN_START_BIT))

#define AW_PID_2308_PWDN_WORKING		(0)
#define AW_PID_2308_PWDN_WORKING_VALUE	\
	(AW_PID_2308_PWDN_WORKING << AW_PID_2308_PWDN_START_BIT)

#define AW_PID_2308_PWDN_POWER_DOWN		(1)
#define AW_PID_2308_PWDN_POWER_DOWN_VALUE	\
	(AW_PID_2308_PWDN_POWER_DOWN << AW_PID_2308_PWDN_START_BIT)

#define AW_PID_2308_PWDN_DEFAULT		(1)
#define AW_PID_2308_PWDN_DEFAULT_VALUE	\
	(AW_PID_2308_PWDN_DEFAULT << AW_PID_2308_PWDN_START_BIT)

/* default value of SYSCTRL (0x04) */
/* #define AW_PID_2308_SYSCTRL_DEFAULT		(0xC303) */

/* SYSCTRL2 (0x05) detail */
/* EN_MPD bit 15 (SYSCTRL2 0x05) */
#define AW_PID_2308_EN_MPD_START_BIT	(15)
#define AW_PID_2308_EN_MPD_BITS_LEN		(1)
#define AW_PID_2308_EN_MPD_MASK			\
	(~(((1<<AW_PID_2308_EN_MPD_BITS_LEN)-1) << AW_PID_2308_EN_MPD_START_BIT))

#define AW_PID_2308_EN_MPD_DISABLE		(0)
#define AW_PID_2308_EN_MPD_DISABLE_VALUE	\
	(AW_PID_2308_EN_MPD_DISABLE << AW_PID_2308_EN_MPD_START_BIT)

#define AW_PID_2308_EN_MPD_ENABLE		(1)
#define AW_PID_2308_EN_MPD_ENABLE_VALUE	\
	(AW_PID_2308_EN_MPD_ENABLE << AW_PID_2308_EN_MPD_START_BIT)

#define AW_PID_2308_EN_MPD_DEFAULT		(1)
#define AW_PID_2308_EN_MPD_DEFAULT_VALUE	\
	(AW_PID_2308_EN_MPD_DEFAULT << AW_PID_2308_EN_MPD_START_BIT)

/* PSM_EN bit 14 (SYSCTRL2 0x05) */
#define AW_PID_2308_PSM_EN_START_BIT	(14)
#define AW_PID_2308_PSM_EN_BITS_LEN		(1)
#define AW_PID_2308_PSM_EN_MASK			\
	(~(((1<<AW_PID_2308_PSM_EN_BITS_LEN)-1) << AW_PID_2308_PSM_EN_START_BIT))

#define AW_PID_2308_PSM_EN_ENABLE		(1)
#define AW_PID_2308_PSM_EN_ENABLE_VALUE	\
	(AW_PID_2308_PSM_EN_ENABLE << AW_PID_2308_PSM_EN_START_BIT)

#define AW_PID_2308_PSM_EN_DISABLE		(0)
#define AW_PID_2308_PSM_EN_DISABLE_VALUE	\
	(AW_PID_2308_PSM_EN_DISABLE << AW_PID_2308_PSM_EN_START_BIT)

#define AW_PID_2308_PSM_EN_DEFAULT		(1)
#define AW_PID_2308_PSM_EN_DEFAULT_VALUE	\
	(AW_PID_2308_PSM_EN_DEFAULT << AW_PID_2308_PSM_EN_START_BIT)

/* INTMODE bit 13 (SYSCTRL2 0x05) */
#define AW_PID_2308_INTMODE_START_BIT	(13)
#define AW_PID_2308_INTMODE_BITS_LEN	(1)
#define AW_PID_2308_INTMODE_MASK		\
	(~(((1<<AW_PID_2308_INTMODE_BITS_LEN)-1) << AW_PID_2308_INTMODE_START_BIT))

#define AW_PID_2308_INTMODE_OPENMINUSDRAIN	(0)
#define AW_PID_2308_INTMODE_OPENMINUSDRAIN_VALUE	\
	(AW_PID_2308_INTMODE_OPENMINUSDRAIN << AW_PID_2308_INTMODE_START_BIT)

#define AW_PID_2308_INTMODE_PUSHPULL	(1)
#define AW_PID_2308_INTMODE_PUSHPULL_VALUE	\
	(AW_PID_2308_INTMODE_PUSHPULL << AW_PID_2308_INTMODE_START_BIT)

#define AW_PID_2308_INTMODE_DEFAULT		(0)
#define AW_PID_2308_INTMODE_DEFAULT_VALUE	\
	(AW_PID_2308_INTMODE_DEFAULT << AW_PID_2308_INTMODE_START_BIT)

/* INTN bit 12 (SYSCTRL2 0x05) */
#define AW_PID_2308_INTN_START_BIT		(12)
#define AW_PID_2308_INTN_BITS_LEN		(1)
#define AW_PID_2308_INTN_MASK			\
	(~(((1<<AW_PID_2308_INTN_BITS_LEN)-1) << AW_PID_2308_INTN_START_BIT))

#define AW_PID_2308_INTN_SYSINT			(0)
#define AW_PID_2308_INTN_SYSINT_VALUE	\
	(AW_PID_2308_INTN_SYSINT << AW_PID_2308_INTN_START_BIT)

#define AW_PID_2308_INTN_SYSST			(1)
#define AW_PID_2308_INTN_SYSST_VALUE	\
	(AW_PID_2308_INTN_SYSST << AW_PID_2308_INTN_START_BIT)

#define AW_PID_2308_INTN_DEFAULT		(0)
#define AW_PID_2308_INTN_DEFAULT_VALUE	\
	(AW_PID_2308_INTN_DEFAULT << AW_PID_2308_INTN_START_BIT)

/* VOL_ADD bit 11:10 (SYSCTRL2 0x05) */
#define AW_PID_2308_VOL_ADD_START_BIT	(10)
#define AW_PID_2308_VOL_ADD_BITS_LEN	(2)
#define AW_PID_2308_VOL_ADD_MASK		\
	(~(((1<<AW_PID_2308_VOL_ADD_BITS_LEN)-1) << AW_PID_2308_VOL_ADD_START_BIT))

#define AW_PID_2308_VOL_ADD_0DB			(0)
#define AW_PID_2308_VOL_ADD_0DB_VALUE	\
	(AW_PID_2308_VOL_ADD_0DB << AW_PID_2308_VOL_ADD_START_BIT)

#define AW_PID_2308_VOL_ADD_6DB			(1)
#define AW_PID_2308_VOL_ADD_6DB_VALUE	\
	(AW_PID_2308_VOL_ADD_6DB << AW_PID_2308_VOL_ADD_START_BIT)

#define AW_PID_2308_VOL_ADD_12DB		(2)
#define AW_PID_2308_VOL_ADD_12DB_VALUE	\
	(AW_PID_2308_VOL_ADD_12DB << AW_PID_2308_VOL_ADD_START_BIT)

#define AW_PID_2308_VOL_ADD_DEFAULT		(0)
#define AW_PID_2308_VOL_ADD_DEFAULT_VALUE	\
	(AW_PID_2308_VOL_ADD_DEFAULT << AW_PID_2308_VOL_ADD_START_BIT)

/* VOL bit 9:0 (SYSCTRL2 0x05) */
#define AW_PID_2308_VOL_START_BIT		(0)
#define AW_PID_2308_VOL_BITS_LEN		(10)
#define AW_PID_2308_VOL_MASK			\
	(~(((1<<AW_PID_2308_VOL_BITS_LEN)-1) << AW_PID_2308_VOL_START_BIT))

#define AW_PID_2308_VOL_DEFAULT			(0)
#define AW_PID_2308_VOL_DEFAULT_VALUE	\
	(AW_PID_2308_VOL_DEFAULT << AW_PID_2308_VOL_START_BIT)

/* default value of SYSCTRL2 (0x05) */
/* #define AW_PID_2308_SYSCTRL2_DEFAULT		(0xC000) */

/* I2SCTRL1 (0x06) detail */
/* TX_EDGE bit 15 (I2SCTRL1 0x06) */
#define AW_PID_2308_TX_EDGE_START_BIT	(15)
#define AW_PID_2308_TX_EDGE_BITS_LEN	(1)
#define AW_PID_2308_TX_EDGE_MASK		\
	(~(((1<<AW_PID_2308_TX_EDGE_BITS_LEN)-1) << AW_PID_2308_TX_EDGE_START_BIT))

#define AW_PID_2308_TX_EDGE_NEGEDGE		(0)
#define AW_PID_2308_TX_EDGE_NEGEDGE_VALUE	\
	(AW_PID_2308_TX_EDGE_NEGEDGE << AW_PID_2308_TX_EDGE_START_BIT)

#define AW_PID_2308_TX_EDGE_POSEDGE		(1)
#define AW_PID_2308_TX_EDGE_POSEDGE_VALUE	\
	(AW_PID_2308_TX_EDGE_POSEDGE << AW_PID_2308_TX_EDGE_START_BIT)

#define AW_PID_2308_TX_EDGE_DEFAULT		(0)
#define AW_PID_2308_TX_EDGE_DEFAULT_VALUE	\
	(AW_PID_2308_TX_EDGE_DEFAULT << AW_PID_2308_TX_EDGE_START_BIT)

/* CFSEL bit 14:12 (I2SCTRL1 0x06) */
#define AW_PID_2308_CFSEL_START_BIT		(12)
#define AW_PID_2308_CFSEL_BITS_LEN		(3)
#define AW_PID_2308_CFSEL_MASK			\
	(~(((1<<AW_PID_2308_CFSEL_BITS_LEN)-1) << AW_PID_2308_CFSEL_START_BIT))

#define AW_PID_2308_CFSEL_HAGC			(0)
#define AW_PID_2308_CFSEL_HAGC_VALUE	\
	(AW_PID_2308_CFSEL_HAGC << AW_PID_2308_CFSEL_START_BIT)

#define AW_PID_2308_CFSEL_ORTESTDET		(1)
#define AW_PID_2308_CFSEL_ORTESTDET_VALUE	\
	(AW_PID_2308_CFSEL_ORTESTDET << AW_PID_2308_CFSEL_START_BIT)

#define AW_PID_2308_CFSEL_IVBTTXDOUT	(2)
#define AW_PID_2308_CFSEL_IVBTTXDOUT_VALUE	\
	(AW_PID_2308_CFSEL_IVBTTXDOUT << AW_PID_2308_CFSEL_START_BIT)

#define AW_PID_2308_CFSEL_IVTXDOUT		(3)
#define AW_PID_2308_CFSEL_IVTXDOUT_VALUE	\
	(AW_PID_2308_CFSEL_IVTXDOUT << AW_PID_2308_CFSEL_START_BIT)

#define AW_PID_2308_CFSEL_DACINTERPOUT	(4)
#define AW_PID_2308_CFSEL_DACINTERPOUT_VALUE	\
	(AW_PID_2308_CFSEL_DACINTERPOUT << AW_PID_2308_CFSEL_START_BIT)

#define AW_PID_2308_CFSEL_IVBTDOUT24K	(5)
#define AW_PID_2308_CFSEL_IVBTDOUT24K_VALUE	\
	(AW_PID_2308_CFSEL_IVBTDOUT24K << AW_PID_2308_CFSEL_START_BIT)

#define AW_PID_2308_CFSEL_IVTXDOUTSYNC	(6)
#define AW_PID_2308_CFSEL_IVTXDOUTSYNC_VALUE	\
	(AW_PID_2308_CFSEL_IVTXDOUTSYNC << AW_PID_2308_CFSEL_START_BIT)

#define AW_PID_2308_CFSEL_OTHERS_IISDSMOUT	(others)
#define AW_PID_2308_CFSEL_OTHERS_IISDSMOUT_VALUE	\
	(AW_PID_2308_CFSEL_OTHERS_IISDSMOUT << AW_PID_2308_CFSEL_START_BIT)

#define AW_PID_2308_CFSEL_DEFAULT		(0)
#define AW_PID_2308_CFSEL_DEFAULT_VALUE	\
	(AW_PID_2308_CFSEL_DEFAULT << AW_PID_2308_CFSEL_START_BIT)

/* CHSEL bit 11:10 (I2SCTRL1 0x06) */
#define AW_PID_2308_CHSEL_START_BIT		(10)
#define AW_PID_2308_CHSEL_BITS_LEN		(2)
#define AW_PID_2308_CHSEL_MASK			\
	(~(((1<<AW_PID_2308_CHSEL_BITS_LEN)-1) << AW_PID_2308_CHSEL_START_BIT))

#define AW_PID_2308_CHSEL_RESERVED		(0)
#define AW_PID_2308_CHSEL_RESERVED_VALUE	\
	(AW_PID_2308_CHSEL_RESERVED << AW_PID_2308_CHSEL_START_BIT)

#define AW_PID_2308_CHSEL_LEFT			(1)
#define AW_PID_2308_CHSEL_LEFT_VALUE	\
	(AW_PID_2308_CHSEL_LEFT << AW_PID_2308_CHSEL_START_BIT)

#define AW_PID_2308_CHSEL_RIGHT			(2)
#define AW_PID_2308_CHSEL_RIGHT_VALUE	\
	(AW_PID_2308_CHSEL_RIGHT << AW_PID_2308_CHSEL_START_BIT)

#define AW_PID_2308_CHSEL_MONO			(3)
#define AW_PID_2308_CHSEL_MONO_VALUE	\
	(AW_PID_2308_CHSEL_MONO << AW_PID_2308_CHSEL_START_BIT)

#define AW_PID_2308_CHSEL_DEFAULT		(1)
#define AW_PID_2308_CHSEL_DEFAULT_VALUE	\
	(AW_PID_2308_CHSEL_DEFAULT << AW_PID_2308_CHSEL_START_BIT)

/* I2SMD bit 9:8 (I2SCTRL1 0x06) */
#define AW_PID_2308_I2SMD_START_BIT		(8)
#define AW_PID_2308_I2SMD_BITS_LEN		(2)
#define AW_PID_2308_I2SMD_MASK			\
	(~(((1<<AW_PID_2308_I2SMD_BITS_LEN)-1) << AW_PID_2308_I2SMD_START_BIT))

#define AW_PID_2308_I2SMD_PHILIP_STANDARD	(0)
#define AW_PID_2308_I2SMD_PHILIP_STANDARD_VALUE	\
	(AW_PID_2308_I2SMD_PHILIP_STANDARD << AW_PID_2308_I2SMD_START_BIT)

#define AW_PID_2308_I2SMD_MSB_JUSTIFIED	(1)
#define AW_PID_2308_I2SMD_MSB_JUSTIFIED_VALUE	\
	(AW_PID_2308_I2SMD_MSB_JUSTIFIED << AW_PID_2308_I2SMD_START_BIT)

#define AW_PID_2308_I2SMD_LSB_JUSTIFIED	(2)
#define AW_PID_2308_I2SMD_LSB_JUSTIFIED_VALUE	\
	(AW_PID_2308_I2SMD_LSB_JUSTIFIED << AW_PID_2308_I2SMD_START_BIT)

#define AW_PID_2308_I2SMD_RESERVED		(3)
#define AW_PID_2308_I2SMD_RESERVED_VALUE	\
	(AW_PID_2308_I2SMD_RESERVED << AW_PID_2308_I2SMD_START_BIT)

#define AW_PID_2308_I2SMD_DEFAULT		(0)
#define AW_PID_2308_I2SMD_DEFAULT_VALUE	\
	(AW_PID_2308_I2SMD_DEFAULT << AW_PID_2308_I2SMD_START_BIT)

/* I2SFS bit 7:6 (I2SCTRL1 0x06) */
#define AW_PID_2308_I2SFS_START_BIT		(6)
#define AW_PID_2308_I2SFS_BITS_LEN		(2)
#define AW_PID_2308_I2SFS_MASK			\
	(~(((1<<AW_PID_2308_I2SFS_BITS_LEN)-1) << AW_PID_2308_I2SFS_START_BIT))

#define AW_PID_2308_I2SFS_16_BITS		(0)
#define AW_PID_2308_I2SFS_16_BITS_VALUE	\
	(AW_PID_2308_I2SFS_16_BITS << AW_PID_2308_I2SFS_START_BIT)

#define AW_PID_2308_I2SFS_20_BITS		(1)
#define AW_PID_2308_I2SFS_20_BITS_VALUE	\
	(AW_PID_2308_I2SFS_20_BITS << AW_PID_2308_I2SFS_START_BIT)

#define AW_PID_2308_I2SFS_24_BITS		(2)
#define AW_PID_2308_I2SFS_24_BITS_VALUE	\
	(AW_PID_2308_I2SFS_24_BITS << AW_PID_2308_I2SFS_START_BIT)

#define AW_PID_2308_I2SFS_32_BITS		(3)
#define AW_PID_2308_I2SFS_32_BITS_VALUE	\
	(AW_PID_2308_I2SFS_32_BITS << AW_PID_2308_I2SFS_START_BIT)

#define AW_PID_2308_I2SFS_DEFAULT		(3)
#define AW_PID_2308_I2SFS_DEFAULT_VALUE	\
	(AW_PID_2308_I2SFS_DEFAULT << AW_PID_2308_I2SFS_START_BIT)

/* I2SBCK bit 5:4 (I2SCTRL1 0x06) */
#define AW_PID_2308_I2SBCK_START_BIT	(4)
#define AW_PID_2308_I2SBCK_BITS_LEN		(2)
#define AW_PID_2308_I2SBCK_MASK			\
	(~(((1<<AW_PID_2308_I2SBCK_BITS_LEN)-1) << AW_PID_2308_I2SBCK_START_BIT))

#define AW_PID_2308_I2SBCK_32FS			(0)
#define AW_PID_2308_I2SBCK_32FS_VALUE	\
	(AW_PID_2308_I2SBCK_32FS << AW_PID_2308_I2SBCK_START_BIT)

#define AW_PID_2308_I2SBCK_48FS			(1)
#define AW_PID_2308_I2SBCK_48FS_VALUE	\
	(AW_PID_2308_I2SBCK_48FS << AW_PID_2308_I2SBCK_START_BIT)

#define AW_PID_2308_I2SBCK_64FS			(2)
#define AW_PID_2308_I2SBCK_64FS_VALUE	\
	(AW_PID_2308_I2SBCK_64FS << AW_PID_2308_I2SBCK_START_BIT)

#define AW_PID_2308_I2SBCK_RESERVED		(3)
#define AW_PID_2308_I2SBCK_RESERVED_VALUE	\
	(AW_PID_2308_I2SBCK_RESERVED << AW_PID_2308_I2SBCK_START_BIT)

#define AW_PID_2308_I2SBCK_DEFAULT		(2)
#define AW_PID_2308_I2SBCK_DEFAULT_VALUE	\
	(AW_PID_2308_I2SBCK_DEFAULT << AW_PID_2308_I2SBCK_START_BIT)

/* I2SSR bit 3:0 (I2SCTRL1 0x06) */
#define AW_PID_2308_I2SSR_START_BIT		(0)
#define AW_PID_2308_I2SSR_BITS_LEN		(4)
#define AW_PID_2308_I2SSR_MASK			\
	(~(((1<<AW_PID_2308_I2SSR_BITS_LEN)-1) << AW_PID_2308_I2SSR_START_BIT))

#define AW_PID_2308_I2SSR_8_KHZ			(0)
#define AW_PID_2308_I2SSR_8_KHZ_VALUE	\
	(AW_PID_2308_I2SSR_8_KHZ << AW_PID_2308_I2SSR_START_BIT)

#define AW_PID_2308_I2SSR_11_KHZ		(1)
#define AW_PID_2308_I2SSR_11_KHZ_VALUE	\
	(AW_PID_2308_I2SSR_11_KHZ << AW_PID_2308_I2SSR_START_BIT)

#define AW_PID_2308_I2SSR_12_KHZ		(2)
#define AW_PID_2308_I2SSR_12_KHZ_VALUE	\
	(AW_PID_2308_I2SSR_12_KHZ << AW_PID_2308_I2SSR_START_BIT)

#define AW_PID_2308_I2SSR_16_KHZ		(3)
#define AW_PID_2308_I2SSR_16_KHZ_VALUE	\
	(AW_PID_2308_I2SSR_16_KHZ << AW_PID_2308_I2SSR_START_BIT)

#define AW_PID_2308_I2SSR_22_KHZ		(4)
#define AW_PID_2308_I2SSR_22_KHZ_VALUE	\
	(AW_PID_2308_I2SSR_22_KHZ << AW_PID_2308_I2SSR_START_BIT)

#define AW_PID_2308_I2SSR_24_KHZ		(5)
#define AW_PID_2308_I2SSR_24_KHZ_VALUE	\
	(AW_PID_2308_I2SSR_24_KHZ << AW_PID_2308_I2SSR_START_BIT)

#define AW_PID_2308_I2SSR_32_KHZ		(6)
#define AW_PID_2308_I2SSR_32_KHZ_VALUE	\
	(AW_PID_2308_I2SSR_32_KHZ << AW_PID_2308_I2SSR_START_BIT)

#define AW_PID_2308_I2SSR_44_KHZ		(7)
#define AW_PID_2308_I2SSR_44_KHZ_VALUE	\
	(AW_PID_2308_I2SSR_44_KHZ << AW_PID_2308_I2SSR_START_BIT)

#define AW_PID_2308_I2SSR_48_KHZ		(8)
#define AW_PID_2308_I2SSR_48_KHZ_VALUE	\
	(AW_PID_2308_I2SSR_48_KHZ << AW_PID_2308_I2SSR_START_BIT)

#define AW_PID_2308_I2SSR_96_KHZ		(9)
#define AW_PID_2308_I2SSR_96_KHZ_VALUE	\
	(AW_PID_2308_I2SSR_96_KHZ << AW_PID_2308_I2SSR_START_BIT)

#define AW_PID_2308_I2SSR_192KHZ		(10)
#define AW_PID_2308_I2SSR_192KHZ_VALUE	\
	(AW_PID_2308_I2SSR_192KHZ << AW_PID_2308_I2SSR_START_BIT)

#define AW_PID_2308_I2SSR_DEFAULT		(8)
#define AW_PID_2308_I2SSR_DEFAULT_VALUE	\
	(AW_PID_2308_I2SSR_DEFAULT << AW_PID_2308_I2SSR_START_BIT)

/* default value of I2SCTRL1 (0x06) */
/* #define AW_PID_2308_I2SCTRL1_DEFAULT		(0x04E8) */

/* I2SCTRL2 (0x07) detail */
/* IV2CH bit 15 (I2SCTRL2 0x07) */
#define AW_PID_2308_IV2CH_START_BIT		(15)
#define AW_PID_2308_IV2CH_BITS_LEN		(1)
#define AW_PID_2308_IV2CH_MASK			\
	(~(((1<<AW_PID_2308_IV2CH_BITS_LEN)-1) << AW_PID_2308_IV2CH_START_BIT))

#define AW_PID_2308_IV2CH_LEGACY		(0)
#define AW_PID_2308_IV2CH_LEGACY_VALUE	\
	(AW_PID_2308_IV2CH_LEGACY << AW_PID_2308_IV2CH_START_BIT)

#define AW_PID_2308_IV2CH_SPECIAL		(1)
#define AW_PID_2308_IV2CH_SPECIAL_VALUE	\
	(AW_PID_2308_IV2CH_SPECIAL << AW_PID_2308_IV2CH_START_BIT)

#define AW_PID_2308_IV2CH_DEFAULT		(0)
#define AW_PID_2308_IV2CH_DEFAULT_VALUE	\
	(AW_PID_2308_IV2CH_DEFAULT << AW_PID_2308_IV2CH_START_BIT)

/* SLOT_NUM bit 14:12 (I2SCTRL2 0x07) */
#define AW_PID_2308_SLOT_NUM_START_BIT	(12)
#define AW_PID_2308_SLOT_NUM_BITS_LEN	(3)
#define AW_PID_2308_SLOT_NUM_MASK		\
	(~(((1<<AW_PID_2308_SLOT_NUM_BITS_LEN)-1) << AW_PID_2308_SLOT_NUM_START_BIT))

#define AW_PID_2308_SLOT_NUM_I2S_MODE	(0)
#define AW_PID_2308_SLOT_NUM_I2S_MODE_VALUE	\
	(AW_PID_2308_SLOT_NUM_I2S_MODE << AW_PID_2308_SLOT_NUM_START_BIT)

#define AW_PID_2308_SLOT_NUM_TDM1S		(1)
#define AW_PID_2308_SLOT_NUM_TDM1S_VALUE	\
	(AW_PID_2308_SLOT_NUM_TDM1S << AW_PID_2308_SLOT_NUM_START_BIT)

#define AW_PID_2308_SLOT_NUM_TDM2S		(2)
#define AW_PID_2308_SLOT_NUM_TDM2S_VALUE	\
	(AW_PID_2308_SLOT_NUM_TDM2S << AW_PID_2308_SLOT_NUM_START_BIT)

#define AW_PID_2308_SLOT_NUM_TDM4S		(3)
#define AW_PID_2308_SLOT_NUM_TDM4S_VALUE	\
	(AW_PID_2308_SLOT_NUM_TDM4S << AW_PID_2308_SLOT_NUM_START_BIT)

#define AW_PID_2308_SLOT_NUM_TDM6S		(4)
#define AW_PID_2308_SLOT_NUM_TDM6S_VALUE	\
	(AW_PID_2308_SLOT_NUM_TDM6S << AW_PID_2308_SLOT_NUM_START_BIT)

#define AW_PID_2308_SLOT_NUM_TDM8S		(5)
#define AW_PID_2308_SLOT_NUM_TDM8S_VALUE	\
	(AW_PID_2308_SLOT_NUM_TDM8S << AW_PID_2308_SLOT_NUM_START_BIT)

#define AW_PID_2308_SLOT_NUM_TDM16S		(6)
#define AW_PID_2308_SLOT_NUM_TDM16S_VALUE	\
	(AW_PID_2308_SLOT_NUM_TDM16S << AW_PID_2308_SLOT_NUM_START_BIT)

#define AW_PID_2308_SLOT_NUM_RESERVED	(7)
#define AW_PID_2308_SLOT_NUM_RESERVED_VALUE	\
	(AW_PID_2308_SLOT_NUM_RESERVED << AW_PID_2308_SLOT_NUM_START_BIT)

#define AW_PID_2308_SLOT_NUM_DEFAULT	(0)
#define AW_PID_2308_SLOT_NUM_DEFAULT_VALUE	\
	(AW_PID_2308_SLOT_NUM_DEFAULT << AW_PID_2308_SLOT_NUM_START_BIT)

/* I2S_TX_SLOTVLD bit 11:8 (I2SCTRL2 0x07) */
#define AW_PID_2308_I2S_TX_SLOTVLD_START_BIT	(8)
#define AW_PID_2308_I2S_TX_SLOTVLD_BITS_LEN	(4)
#define AW_PID_2308_I2S_TX_SLOTVLD_MASK	\
	(~(((1<<AW_PID_2308_I2S_TX_SLOTVLD_BITS_LEN)-1) << AW_PID_2308_I2S_TX_SLOTVLD_START_BIT))

#define AW_PID_2308_I2S_TX_SLOTVLD_SLOT_0	(0)
#define AW_PID_2308_I2S_TX_SLOTVLD_SLOT_0_VALUE	\
	(AW_PID_2308_I2S_TX_SLOTVLD_SLOT_0 << AW_PID_2308_I2S_TX_SLOTVLD_START_BIT)

#define AW_PID_2308_I2S_TX_SLOTVLD_SLOT_1	(1)
#define AW_PID_2308_I2S_TX_SLOTVLD_SLOT_1_VALUE	\
	(AW_PID_2308_I2S_TX_SLOTVLD_SLOT_1 << AW_PID_2308_I2S_TX_SLOTVLD_START_BIT)

#define AW_PID_2308_I2S_TX_SLOTVLD_SLOT_2	(2)
#define AW_PID_2308_I2S_TX_SLOTVLD_SLOT_2_VALUE	\
	(AW_PID_2308_I2S_TX_SLOTVLD_SLOT_2 << AW_PID_2308_I2S_TX_SLOTVLD_START_BIT)

#define AW_PID_2308_I2S_TX_SLOTVLD_SLOT_3	(3)
#define AW_PID_2308_I2S_TX_SLOTVLD_SLOT_3_VALUE	\
	(AW_PID_2308_I2S_TX_SLOTVLD_SLOT_3 << AW_PID_2308_I2S_TX_SLOTVLD_START_BIT)

#define AW_PID_2308_I2S_TX_SLOTVLD_SLOT_15	(15)
#define AW_PID_2308_I2S_TX_SLOTVLD_SLOT_15_VALUE	\
	(AW_PID_2308_I2S_TX_SLOTVLD_SLOT_15 << AW_PID_2308_I2S_TX_SLOTVLD_START_BIT)

#define AW_PID_2308_I2S_TX_SLOTVLD_DEFAULT	(0)
#define AW_PID_2308_I2S_TX_SLOTVLD_DEFAULT_VALUE	\
	(AW_PID_2308_I2S_TX_SLOTVLD_DEFAULT << AW_PID_2308_I2S_TX_SLOTVLD_START_BIT)

/* I2S_RXR_SLOTVLD bit 7:4 (I2SCTRL2 0x07) */
#define AW_PID_2308_I2S_RXR_SLOTVLD_START_BIT	(4)
#define AW_PID_2308_I2S_RXR_SLOTVLD_BITS_LEN	(4)
#define AW_PID_2308_I2S_RXR_SLOTVLD_MASK	\
	(~(((1<<AW_PID_2308_I2S_RXR_SLOTVLD_BITS_LEN)-1) << AW_PID_2308_I2S_RXR_SLOTVLD_START_BIT))

#define AW_PID_2308_I2S_RXR_SLOTVLD_SLOT_0	(0)
#define AW_PID_2308_I2S_RXR_SLOTVLD_SLOT_0_VALUE	\
	(AW_PID_2308_I2S_RXR_SLOTVLD_SLOT_0 << AW_PID_2308_I2S_RXR_SLOTVLD_START_BIT)

#define AW_PID_2308_I2S_RXR_SLOTVLD_SLOT_1	(1)
#define AW_PID_2308_I2S_RXR_SLOTVLD_SLOT_1_VALUE	\
	(AW_PID_2308_I2S_RXR_SLOTVLD_SLOT_1 << AW_PID_2308_I2S_RXR_SLOTVLD_START_BIT)

#define AW_PID_2308_I2S_RXR_SLOTVLD_SLOT_2	(2)
#define AW_PID_2308_I2S_RXR_SLOTVLD_SLOT_2_VALUE	\
	(AW_PID_2308_I2S_RXR_SLOTVLD_SLOT_2 << AW_PID_2308_I2S_RXR_SLOTVLD_START_BIT)

#define AW_PID_2308_I2S_RXR_SLOTVLD_SLOT_3	(3)
#define AW_PID_2308_I2S_RXR_SLOTVLD_SLOT_3_VALUE	\
	(AW_PID_2308_I2S_RXR_SLOTVLD_SLOT_3 << AW_PID_2308_I2S_RXR_SLOTVLD_START_BIT)

#define AW_PID_2308_I2S_RXR_SLOTVLD_SLOT_15	(15)
#define AW_PID_2308_I2S_RXR_SLOTVLD_SLOT_15_VALUE	\
	(AW_PID_2308_I2S_RXR_SLOTVLD_SLOT_15 << AW_PID_2308_I2S_RXR_SLOTVLD_START_BIT)

#define AW_PID_2308_I2S_RXR_SLOTVLD_DEFAULT	(1)
#define AW_PID_2308_I2S_RXR_SLOTVLD_DEFAULT_VALUE	\
	(AW_PID_2308_I2S_RXR_SLOTVLD_DEFAULT << AW_PID_2308_I2S_RXR_SLOTVLD_START_BIT)

/* I2S_RXL_SLOTVLD bit 3:0 (I2SCTRL2 0x07) */
#define AW_PID_2308_I2S_RXL_SLOTVLD_START_BIT	(0)
#define AW_PID_2308_I2S_RXL_SLOTVLD_BITS_LEN	(4)
#define AW_PID_2308_I2S_RXL_SLOTVLD_MASK	\
	(~(((1<<AW_PID_2308_I2S_RXL_SLOTVLD_BITS_LEN)-1) << AW_PID_2308_I2S_RXL_SLOTVLD_START_BIT))

#define AW_PID_2308_I2S_RXL_SLOTVLD_SLOT_0	(0)
#define AW_PID_2308_I2S_RXL_SLOTVLD_SLOT_0_VALUE	\
	(AW_PID_2308_I2S_RXL_SLOTVLD_SLOT_0 << AW_PID_2308_I2S_RXL_SLOTVLD_START_BIT)

#define AW_PID_2308_I2S_RXL_SLOTVLD_SLOT_1	(1)
#define AW_PID_2308_I2S_RXL_SLOTVLD_SLOT_1_VALUE	\
	(AW_PID_2308_I2S_RXL_SLOTVLD_SLOT_1 << AW_PID_2308_I2S_RXL_SLOTVLD_START_BIT)

#define AW_PID_2308_I2S_RXL_SLOTVLD_SLOT_2	(2)
#define AW_PID_2308_I2S_RXL_SLOTVLD_SLOT_2_VALUE	\
	(AW_PID_2308_I2S_RXL_SLOTVLD_SLOT_2 << AW_PID_2308_I2S_RXL_SLOTVLD_START_BIT)

#define AW_PID_2308_I2S_RXL_SLOTVLD_SLOT_3	(3)
#define AW_PID_2308_I2S_RXL_SLOTVLD_SLOT_3_VALUE	\
	(AW_PID_2308_I2S_RXL_SLOTVLD_SLOT_3 << AW_PID_2308_I2S_RXL_SLOTVLD_START_BIT)

#define AW_PID_2308_I2S_RXL_SLOTVLD_SLOT_15	(15)
#define AW_PID_2308_I2S_RXL_SLOTVLD_SLOT_15_VALUE	\
	(AW_PID_2308_I2S_RXL_SLOTVLD_SLOT_15 << AW_PID_2308_I2S_RXL_SLOTVLD_START_BIT)

#define AW_PID_2308_I2S_RXL_SLOTVLD_DEFAULT	(0)
#define AW_PID_2308_I2S_RXL_SLOTVLD_DEFAULT_VALUE	\
	(AW_PID_2308_I2S_RXL_SLOTVLD_DEFAULT << AW_PID_2308_I2S_RXL_SLOTVLD_START_BIT)

/* default value of I2SCTRL2 (0x07) */
/* #define AW_PID_2308_I2SCTRL2_DEFAULT		(0x0010) */

/* I2SCTRL3 (0x08) detail */
/* RCV_GAIN0 bit 14:12 (I2SCTRL3 0x08) */
#define AW_PID_2308_RCV_GAIN0_START_BIT	(12)
#define AW_PID_2308_RCV_GAIN0_BITS_LEN	(3)
#define AW_PID_2308_RCV_GAIN0_MASK		\
	(~(((1<<AW_PID_2308_RCV_GAIN0_BITS_LEN)-1) << AW_PID_2308_RCV_GAIN0_START_BIT))

#define AW_PID_2308_RCV_GAIN0_MINUS3DB	(0)
#define AW_PID_2308_RCV_GAIN0_MINUS3DB_VALUE	\
	(AW_PID_2308_RCV_GAIN0_MINUS3DB << AW_PID_2308_RCV_GAIN0_START_BIT)

#define AW_PID_2308_RCV_GAIN0_0DB		(1)
#define AW_PID_2308_RCV_GAIN0_0DB_VALUE	\
	(AW_PID_2308_RCV_GAIN0_0DB << AW_PID_2308_RCV_GAIN0_START_BIT)

#define AW_PID_2308_RCV_GAIN0_6DB		(2)
#define AW_PID_2308_RCV_GAIN0_6DB_VALUE	\
	(AW_PID_2308_RCV_GAIN0_6DB << AW_PID_2308_RCV_GAIN0_START_BIT)

#define AW_PID_2308_RCV_GAIN0_10P4DB	(3)
#define AW_PID_2308_RCV_GAIN0_10P4DB_VALUE	\
	(AW_PID_2308_RCV_GAIN0_10P4DB << AW_PID_2308_RCV_GAIN0_START_BIT)

#define AW_PID_2308_RCV_GAIN0_12P5DB	(4)
#define AW_PID_2308_RCV_GAIN0_12P5DB_VALUE	\
	(AW_PID_2308_RCV_GAIN0_12P5DB << AW_PID_2308_RCV_GAIN0_START_BIT)

#define AW_PID_2308_RCV_GAIN0_17DB		(5)
#define AW_PID_2308_RCV_GAIN0_17DB_VALUE	\
	(AW_PID_2308_RCV_GAIN0_17DB << AW_PID_2308_RCV_GAIN0_START_BIT)

#define AW_PID_2308_RCV_GAIN0_DEFAULT	(4)
#define AW_PID_2308_RCV_GAIN0_DEFAULT_VALUE	\
	(AW_PID_2308_RCV_GAIN0_DEFAULT << AW_PID_2308_RCV_GAIN0_START_BIT)

/* SPK_GAIN0 bit 10:8 (I2SCTRL3 0x08) */
#define AW_PID_2308_SPK_GAIN0_START_BIT	(8)
#define AW_PID_2308_SPK_GAIN0_BITS_LEN	(3)
#define AW_PID_2308_SPK_GAIN0_MASK		\
	(~(((1<<AW_PID_2308_SPK_GAIN0_BITS_LEN)-1) << AW_PID_2308_SPK_GAIN0_START_BIT))

#define AW_PID_2308_SPK_GAIN0_3DB		(0)
#define AW_PID_2308_SPK_GAIN0_3DB_VALUE	\
	(AW_PID_2308_SPK_GAIN0_3DB << AW_PID_2308_SPK_GAIN0_START_BIT)

#define AW_PID_2308_SPK_GAIN0_9DB		(1)
#define AW_PID_2308_SPK_GAIN0_9DB_VALUE	\
	(AW_PID_2308_SPK_GAIN0_9DB << AW_PID_2308_SPK_GAIN0_START_BIT)

#define AW_PID_2308_SPK_GAIN0_12DB		(2)
#define AW_PID_2308_SPK_GAIN0_12DB_VALUE	\
	(AW_PID_2308_SPK_GAIN0_12DB << AW_PID_2308_SPK_GAIN0_START_BIT)

#define AW_PID_2308_SPK_GAIN0_15DB		(3)
#define AW_PID_2308_SPK_GAIN0_15DB_VALUE	\
	(AW_PID_2308_SPK_GAIN0_15DB << AW_PID_2308_SPK_GAIN0_START_BIT)

#define AW_PID_2308_SPK_GAIN0_18P5DB	(4)
#define AW_PID_2308_SPK_GAIN0_18P5DB_VALUE	\
	(AW_PID_2308_SPK_GAIN0_18P5DB << AW_PID_2308_SPK_GAIN0_START_BIT)

#define AW_PID_2308_SPK_GAIN0_19DB		(5)
#define AW_PID_2308_SPK_GAIN0_19DB_VALUE	\
	(AW_PID_2308_SPK_GAIN0_19DB << AW_PID_2308_SPK_GAIN0_START_BIT)

#define AW_PID_2308_SPK_GAIN0_20DB		(6)
#define AW_PID_2308_SPK_GAIN0_20DB_VALUE	\
	(AW_PID_2308_SPK_GAIN0_20DB << AW_PID_2308_SPK_GAIN0_START_BIT)

#define AW_PID_2308_SPK_GAIN0_DEFAULT	(5)
#define AW_PID_2308_SPK_GAIN0_DEFAULT_VALUE	\
	(AW_PID_2308_SPK_GAIN0_DEFAULT << AW_PID_2308_SPK_GAIN0_START_BIT)

/* FSYNC_TYPE bit 7 (I2SCTRL3 0x08) */
#define AW_PID_2308_FSYNC_TYPE_START_BIT	(7)
#define AW_PID_2308_FSYNC_TYPE_BITS_LEN	(1)
#define AW_PID_2308_FSYNC_TYPE_MASK		\
	(~(((1<<AW_PID_2308_FSYNC_TYPE_BITS_LEN)-1) << AW_PID_2308_FSYNC_TYPE_START_BIT))

#define AW_PID_2308_FSYNC_TYPE_ONEMINUSSLOT	(0)
#define AW_PID_2308_FSYNC_TYPE_ONEMINUSSLOT_VALUE	\
	(AW_PID_2308_FSYNC_TYPE_ONEMINUSSLOT << AW_PID_2308_FSYNC_TYPE_START_BIT)

#define AW_PID_2308_FSYNC_TYPE_ONEMINUSBCK	(1)
#define AW_PID_2308_FSYNC_TYPE_ONEMINUSBCK_VALUE	\
	(AW_PID_2308_FSYNC_TYPE_ONEMINUSBCK << AW_PID_2308_FSYNC_TYPE_START_BIT)

#define AW_PID_2308_FSYNC_TYPE_DEFAULT	(0)
#define AW_PID_2308_FSYNC_TYPE_DEFAULT_VALUE	\
	(AW_PID_2308_FSYNC_TYPE_DEFAULT << AW_PID_2308_FSYNC_TYPE_START_BIT)

/* DOHZ bit 6 (I2SCTRL3 0x08) */
#define AW_PID_2308_DOHZ_START_BIT		(6)
#define AW_PID_2308_DOHZ_BITS_LEN		(1)
#define AW_PID_2308_DOHZ_MASK			\
	(~(((1<<AW_PID_2308_DOHZ_BITS_LEN)-1) << AW_PID_2308_DOHZ_START_BIT))

#define AW_PID_2308_DOHZ_ALL			(0)
#define AW_PID_2308_DOHZ_ALL_VALUE		\
	(AW_PID_2308_DOHZ_ALL << AW_PID_2308_DOHZ_START_BIT)

#define AW_PID_2308_DOHZ_HIZ			(1)
#define AW_PID_2308_DOHZ_HIZ_VALUE		\
	(AW_PID_2308_DOHZ_HIZ << AW_PID_2308_DOHZ_START_BIT)

#define AW_PID_2308_DOHZ_DEFAULT		(1)
#define AW_PID_2308_DOHZ_DEFAULT_VALUE	\
	(AW_PID_2308_DOHZ_DEFAULT << AW_PID_2308_DOHZ_START_BIT)

/* DRVSTREN bit 5 (I2SCTRL3 0x08) */
#define AW_PID_2308_DRVSTREN_START_BIT	(5)
#define AW_PID_2308_DRVSTREN_BITS_LEN	(1)
#define AW_PID_2308_DRVSTREN_MASK		\
	(~(((1<<AW_PID_2308_DRVSTREN_BITS_LEN)-1) << AW_PID_2308_DRVSTREN_START_BIT))

#define AW_PID_2308_DRVSTREN_4MA		(0)
#define AW_PID_2308_DRVSTREN_4MA_VALUE	\
	(AW_PID_2308_DRVSTREN_4MA << AW_PID_2308_DRVSTREN_START_BIT)

#define AW_PID_2308_DRVSTREN_12MA		(1)
#define AW_PID_2308_DRVSTREN_12MA_VALUE	\
	(AW_PID_2308_DRVSTREN_12MA << AW_PID_2308_DRVSTREN_START_BIT)

#define AW_PID_2308_DRVSTREN_DEFAULT	(1)
#define AW_PID_2308_DRVSTREN_DEFAULT_VALUE	\
	(AW_PID_2308_DRVSTREN_DEFAULT << AW_PID_2308_DRVSTREN_START_BIT)

/* I2SDOSEL bit 4 (I2SCTRL3 0x08) */
#define AW_PID_2308_I2SDOSEL_START_BIT	(4)
#define AW_PID_2308_I2SDOSEL_BITS_LEN	(1)
#define AW_PID_2308_I2SDOSEL_MASK		\
	(~(((1<<AW_PID_2308_I2SDOSEL_BITS_LEN)-1) << AW_PID_2308_I2SDOSEL_START_BIT))

#define AW_PID_2308_I2SDOSEL_ZEROS		(0)
#define AW_PID_2308_I2SDOSEL_ZEROS_VALUE	\
	(AW_PID_2308_I2SDOSEL_ZEROS << AW_PID_2308_I2SDOSEL_START_BIT)

#define AW_PID_2308_I2SDOSEL_TXDATA		(1)
#define AW_PID_2308_I2SDOSEL_TXDATA_VALUE	\
	(AW_PID_2308_I2SDOSEL_TXDATA << AW_PID_2308_I2SDOSEL_START_BIT)

#define AW_PID_2308_I2SDOSEL_DEFAULT	(0)
#define AW_PID_2308_I2SDOSEL_DEFAULT_VALUE	\
	(AW_PID_2308_I2SDOSEL_DEFAULT << AW_PID_2308_I2SDOSEL_START_BIT)

/* I2SCHS bit 3 (I2SCTRL3 0x08) */
#define AW_PID_2308_I2SCHS_START_BIT	(3)
#define AW_PID_2308_I2SCHS_BITS_LEN		(1)
#define AW_PID_2308_I2SCHS_MASK			\
	(~(((1<<AW_PID_2308_I2SCHS_BITS_LEN)-1) << AW_PID_2308_I2SCHS_START_BIT))

#define AW_PID_2308_I2SCHS_LEFT			(0)
#define AW_PID_2308_I2SCHS_LEFT_VALUE	\
	(AW_PID_2308_I2SCHS_LEFT << AW_PID_2308_I2SCHS_START_BIT)

#define AW_PID_2308_I2SCHS_RIGHT		(1)
#define AW_PID_2308_I2SCHS_RIGHT_VALUE	\
	(AW_PID_2308_I2SCHS_RIGHT << AW_PID_2308_I2SCHS_START_BIT)

#define AW_PID_2308_I2SCHS_DEFAULT		(0)
#define AW_PID_2308_I2SCHS_DEFAULT_VALUE	\
	(AW_PID_2308_I2SCHS_DEFAULT << AW_PID_2308_I2SCHS_START_BIT)

/* LPBK bit 2:1 (I2SCTRL3 0x08) */
#define AW_PID_2308_LPBK_START_BIT		(1)
#define AW_PID_2308_LPBK_BITS_LEN		(2)
#define AW_PID_2308_LPBK_MASK			\
	(~(((1<<AW_PID_2308_LPBK_BITS_LEN)-1) << AW_PID_2308_LPBK_START_BIT))

#define AW_PID_2308_LPBK_DISABLE		(0)
#define AW_PID_2308_LPBK_DISABLE_VALUE	\
	(AW_PID_2308_LPBK_DISABLE << AW_PID_2308_LPBK_START_BIT)

#define AW_PID_2308_LPBK_FARMINUSBACK	(1)
#define AW_PID_2308_LPBK_FARMINUSBACK_VALUE	\
	(AW_PID_2308_LPBK_FARMINUSBACK << AW_PID_2308_LPBK_START_BIT)

#define AW_PID_2308_LPBK_NEARMINUSBACK	(2)
#define AW_PID_2308_LPBK_NEARMINUSBACK_VALUE	\
	(AW_PID_2308_LPBK_NEARMINUSBACK << AW_PID_2308_LPBK_START_BIT)

#define AW_PID_2308_LPBK_RESERVED		(3)
#define AW_PID_2308_LPBK_RESERVED_VALUE	\
	(AW_PID_2308_LPBK_RESERVED << AW_PID_2308_LPBK_START_BIT)

#define AW_PID_2308_LPBK_DEFAULT		(0)
#define AW_PID_2308_LPBK_DEFAULT_VALUE	\
	(AW_PID_2308_LPBK_DEFAULT << AW_PID_2308_LPBK_START_BIT)

/* ULS_MODE bit 0 (I2SCTRL3 0x08) */
#define AW_PID_2308_ULS_MODE_START_BIT	(0)
#define AW_PID_2308_ULS_MODE_BITS_LEN	(1)
#define AW_PID_2308_ULS_MODE_MASK		\
	(~(((1<<AW_PID_2308_ULS_MODE_BITS_LEN)-1) << AW_PID_2308_ULS_MODE_START_BIT))

#define AW_PID_2308_ULS_MODE_LOWPASS	(0)
#define AW_PID_2308_ULS_MODE_LOWPASS_VALUE	\
	(AW_PID_2308_ULS_MODE_LOWPASS << AW_PID_2308_ULS_MODE_START_BIT)

#define AW_PID_2308_ULS_MODE_TDM		(1)
#define AW_PID_2308_ULS_MODE_TDM_VALUE	\
	(AW_PID_2308_ULS_MODE_TDM << AW_PID_2308_ULS_MODE_START_BIT)

#define AW_PID_2308_ULS_MODE_DEFAULT	(0)
#define AW_PID_2308_ULS_MODE_DEFAULT_VALUE	\
	(AW_PID_2308_ULS_MODE_DEFAULT << AW_PID_2308_ULS_MODE_START_BIT)

/* default value of I2SCTRL3 (0x08) */
/* #define AW_PID_2308_I2SCTRL3_DEFAULT		(0x4560) */

/* DACCFG1 (0x09) detail */
/* RVTH bit 15:8 (DACCFG1 0x09) */
#define AW_PID_2308_RVTH_START_BIT		(8)
#define AW_PID_2308_RVTH_BITS_LEN		(8)
#define AW_PID_2308_RVTH_MASK			\
	(~(((1<<AW_PID_2308_RVTH_BITS_LEN)-1) << AW_PID_2308_RVTH_START_BIT))

#define AW_PID_2308_RVTH_DEFAULT		(0x39)
#define AW_PID_2308_RVTH_DEFAULT_VALUE	\
	(AW_PID_2308_RVTH_DEFAULT << AW_PID_2308_RVTH_START_BIT)

/* AVTH bit 7:0 (DACCFG1 0x09) */
#define AW_PID_2308_AVTH_START_BIT		(0)
#define AW_PID_2308_AVTH_BITS_LEN		(8)
#define AW_PID_2308_AVTH_MASK			\
	(~(((1<<AW_PID_2308_AVTH_BITS_LEN)-1) << AW_PID_2308_AVTH_START_BIT))

#define AW_PID_2308_AVTH_DEFAULT		(0x40)
#define AW_PID_2308_AVTH_DEFAULT_VALUE	\
	(AW_PID_2308_AVTH_DEFAULT << AW_PID_2308_AVTH_START_BIT)

/* default value of DACCFG1 (0x09) */
/* #define AW_PID_2308_DACCFG1_DEFAULT		(0x3940) */

/* DACCFG2 (0x0A) detail */
/* ATTH bit 15:0 (DACCFG2 0x0A) */
#define AW_PID_2308_ATTH_START_BIT		(0)
#define AW_PID_2308_ATTH_BITS_LEN		(16)
#define AW_PID_2308_ATTH_MASK			\
	(~(((1<<AW_PID_2308_ATTH_BITS_LEN)-1) << AW_PID_2308_ATTH_START_BIT))

#define AW_PID_2308_ATTH_RESERVED		(0)
#define AW_PID_2308_ATTH_RESERVED_VALUE	\
	(AW_PID_2308_ATTH_RESERVED << AW_PID_2308_ATTH_START_BIT)

#define AW_PID_2308_ATTH_DEFAULT		(0x0030)
#define AW_PID_2308_ATTH_DEFAULT_VALUE	\
	(AW_PID_2308_ATTH_DEFAULT << AW_PID_2308_ATTH_START_BIT)

/* default value of DACCFG2 (0x0A) */
/* #define AW_PID_2308_DACCFG2_DEFAULT		(0x0030) */

/* DACCFG3 (0x0B) detail */
/* RTTH bit 15:0 (DACCFG3 0x0B) */
#define AW_PID_2308_RTTH_START_BIT		(0)
#define AW_PID_2308_RTTH_BITS_LEN		(16)
#define AW_PID_2308_RTTH_MASK			\
	(~(((1<<AW_PID_2308_RTTH_BITS_LEN)-1) << AW_PID_2308_RTTH_START_BIT))

#define AW_PID_2308_RTTH_RESERVED		(0)
#define AW_PID_2308_RTTH_RESERVED_VALUE	\
	(AW_PID_2308_RTTH_RESERVED << AW_PID_2308_RTTH_START_BIT)

#define AW_PID_2308_RTTH_DEFAULT		(0x01E0)
#define AW_PID_2308_RTTH_DEFAULT_VALUE	\
	(AW_PID_2308_RTTH_DEFAULT << AW_PID_2308_RTTH_START_BIT)

/* default value of DACCFG3 (0x0B) */
/* #define AW_PID_2308_DACCFG3_DEFAULT		(0x01E0) */

/* DACCFG4 (0x0C) detail */
/* INIT_GAIN bit 14:8 (DACCFG4 0x0C) */
#define AW_PID_2308_INIT_GAIN_START_BIT	(8)
#define AW_PID_2308_INIT_GAIN_BITS_LEN	(7)
#define AW_PID_2308_INIT_GAIN_MASK		\
	(~(((1<<AW_PID_2308_INIT_GAIN_BITS_LEN)-1) << AW_PID_2308_INIT_GAIN_START_BIT))

#define AW_PID_2308_INIT_GAIN_DEFAULT	(0)
#define AW_PID_2308_INIT_GAIN_DEFAULT_VALUE	\
	(AW_PID_2308_INIT_GAIN_DEFAULT << AW_PID_2308_INIT_GAIN_START_BIT)

/* HOLDTH bit 7:0 (DACCFG4 0x0C) */
#define AW_PID_2308_HOLDTH_START_BIT	(0)
#define AW_PID_2308_HOLDTH_BITS_LEN		(8)
#define AW_PID_2308_HOLDTH_MASK			\
	(~(((1<<AW_PID_2308_HOLDTH_BITS_LEN)-1) << AW_PID_2308_HOLDTH_START_BIT))

#define AW_PID_2308_HOLDTH_RESERVED		(0)
#define AW_PID_2308_HOLDTH_RESERVED_VALUE	\
	(AW_PID_2308_HOLDTH_RESERVED << AW_PID_2308_HOLDTH_START_BIT)

#define AW_PID_2308_HOLDTH_DEFAULT		(0x64)
#define AW_PID_2308_HOLDTH_DEFAULT_VALUE	\
	(AW_PID_2308_HOLDTH_DEFAULT << AW_PID_2308_HOLDTH_START_BIT)

/* default value of DACCFG4 (0x0C) */
/* #define AW_PID_2308_DACCFG4_DEFAULT		(0x0064) */

/* VBAT (0x21) detail */
/* VBAT_DET bit 9:0 (VBAT 0x21) */
#define AW_PID_2308_VBAT_DET_START_BIT	(0)
#define AW_PID_2308_VBAT_DET_BITS_LEN	(10)
#define AW_PID_2308_VBAT_DET_MASK		\
	(~(((1<<AW_PID_2308_VBAT_DET_BITS_LEN)-1) << AW_PID_2308_VBAT_DET_START_BIT))

#define AW_PID_2308_VBAT_DET_DEFAULT	(0x2eb)
#define AW_PID_2308_VBAT_DET_DEFAULT_VALUE	\
	(AW_PID_2308_VBAT_DET_DEFAULT << AW_PID_2308_VBAT_DET_START_BIT)

/* default value of VBAT (0x21) */
/* #define AW_PID_2308_VBAT_DEFAULT		(0x02EB) */

/* TEMP (0x22) detail */
/* TEMP_DET bit 9:0 (TEMP 0x22) */
#define AW_PID_2308_TEMP_DET_START_BIT	(0)
#define AW_PID_2308_TEMP_DET_BITS_LEN	(10)
#define AW_PID_2308_TEMP_DET_MASK		\
	(~(((1<<AW_PID_2308_TEMP_DET_BITS_LEN)-1) << AW_PID_2308_TEMP_DET_START_BIT))

#define AW_PID_2308_TEMP_DET_MINUS40	(984)
#define AW_PID_2308_TEMP_DET_MINUS40_VALUE	\
	(AW_PID_2308_TEMP_DET_MINUS40 << AW_PID_2308_TEMP_DET_START_BIT)

#define AW_PID_2308_TEMP_DET_0			(0)
#define AW_PID_2308_TEMP_DET_0_VALUE	\
	(AW_PID_2308_TEMP_DET_0 << AW_PID_2308_TEMP_DET_START_BIT)

#define AW_PID_2308_TEMP_DET_1			(1)
#define AW_PID_2308_TEMP_DET_1_VALUE	\
	(AW_PID_2308_TEMP_DET_1 << AW_PID_2308_TEMP_DET_START_BIT)

#define AW_PID_2308_TEMP_DET_25			(25)
#define AW_PID_2308_TEMP_DET_25_VALUE	\
	(AW_PID_2308_TEMP_DET_25 << AW_PID_2308_TEMP_DET_START_BIT)

#define AW_PID_2308_TEMP_DET_55			(55)
#define AW_PID_2308_TEMP_DET_55_VALUE	\
	(AW_PID_2308_TEMP_DET_55 << AW_PID_2308_TEMP_DET_START_BIT)

#define AW_PID_2308_TEMP_DET_DEFAULT	(0x019)
#define AW_PID_2308_TEMP_DET_DEFAULT_VALUE	\
	(AW_PID_2308_TEMP_DET_DEFAULT << AW_PID_2308_TEMP_DET_START_BIT)

/* default value of TEMP (0x22) */
/* #define AW_PID_2308_TEMP_DEFAULT		(0x0019) */

/* PVDD (0x23) detail */
/* PVDD_DET bit 9:0 (PVDD 0x23) */
#define AW_PID_2308_PVDD_DET_START_BIT	(0)
#define AW_PID_2308_PVDD_DET_BITS_LEN	(10)
#define AW_PID_2308_PVDD_DET_MASK		\
	(~(((1<<AW_PID_2308_PVDD_DET_BITS_LEN)-1) << AW_PID_2308_PVDD_DET_START_BIT))

#define AW_PID_2308_PVDD_DET_DEFAULT	(0x13e)
#define AW_PID_2308_PVDD_DET_DEFAULT_VALUE	\
	(AW_PID_2308_PVDD_DET_DEFAULT << AW_PID_2308_PVDD_DET_START_BIT)

/* default value of PVDD (0x23) */
/* #define AW_PID_2308_PVDD_DEFAULT		(0x013E) */

/* BSTCTRL1 (0x60) detail */
/* BST_MODE bit 15:14 (BSTCTRL1 0x60) */
#define AW_PID_2308_BST_MODE_START_BIT	(14)
#define AW_PID_2308_BST_MODE_BITS_LEN	(2)
#define AW_PID_2308_BST_MODE_MASK		\
	(~(((1<<AW_PID_2308_BST_MODE_BITS_LEN)-1) << AW_PID_2308_BST_MODE_START_BIT))

#define AW_PID_2308_BST_MODE_PASS_THROUGH	(0)
#define AW_PID_2308_BST_MODE_PASS_THROUGH_VALUE	\
	(AW_PID_2308_BST_MODE_PASS_THROUGH << AW_PID_2308_BST_MODE_START_BIT)

#define AW_PID_2308_BST_MODE_FORCE_BOOST	(1)
#define AW_PID_2308_BST_MODE_FORCE_BOOST_VALUE	\
	(AW_PID_2308_BST_MODE_FORCE_BOOST << AW_PID_2308_BST_MODE_START_BIT)

#define AW_PID_2308_BST_MODE_SMARTBOOST_1	(2)
#define AW_PID_2308_BST_MODE_SMARTBOOST_1_VALUE	\
	(AW_PID_2308_BST_MODE_SMARTBOOST_1 << AW_PID_2308_BST_MODE_START_BIT)

#define AW_PID_2308_BST_MODE_SMARTBOOST_2	(3)
#define AW_PID_2308_BST_MODE_SMARTBOOST_2_VALUE	\
	(AW_PID_2308_BST_MODE_SMARTBOOST_2 << AW_PID_2308_BST_MODE_START_BIT)

#define AW_PID_2308_BST_MODE_DEFAULT	(0x3)
#define AW_PID_2308_BST_MODE_DEFAULT_VALUE	\
	(AW_PID_2308_BST_MODE_DEFAULT << AW_PID_2308_BST_MODE_START_BIT)

/* BST_RTH bit 13:7 (BSTCTRL1 0x60) */
#define AW_PID_2308_BST_RTH_START_BIT	(7)
#define AW_PID_2308_BST_RTH_BITS_LEN	(7)
#define AW_PID_2308_BST_RTH_MASK		\
	(~(((1<<AW_PID_2308_BST_RTH_BITS_LEN)-1) << AW_PID_2308_BST_RTH_START_BIT))

#define AW_PID_2308_BST_RTH_DEFAULT		(40)
#define AW_PID_2308_BST_RTH_DEFAULT_VALUE	\
	(AW_PID_2308_BST_RTH_DEFAULT << AW_PID_2308_BST_RTH_START_BIT)

/* BST_ATH bit 6:0 (BSTCTRL1 0x60) */
#define AW_PID_2308_BST_ATH_START_BIT	(0)
#define AW_PID_2308_BST_ATH_BITS_LEN	(7)
#define AW_PID_2308_BST_ATH_MASK		\
	(~(((1<<AW_PID_2308_BST_ATH_BITS_LEN)-1) << AW_PID_2308_BST_ATH_START_BIT))

#define AW_PID_2308_BST_ATH_DEFAULT		(38)
#define AW_PID_2308_BST_ATH_DEFAULT_VALUE	\
	(AW_PID_2308_BST_ATH_DEFAULT << AW_PID_2308_BST_ATH_START_BIT)

/* default value of BSTCTRL1 (0x60) */
/* #define AW_PID_2308_BSTCTRL1_DEFAULT		(0xD426) */

/* BSTCTRL2 (0x61) detail */
/* BST_IPEAK bit 15:12 (BSTCTRL2 0x61) */
#define AW_PID_2308_BST_IPEAK_START_BIT	(12)
#define AW_PID_2308_BST_IPEAK_BITS_LEN	(4)
#define AW_PID_2308_BST_IPEAK_MASK		\
	(~(((1<<AW_PID_2308_BST_IPEAK_BITS_LEN)-1) << AW_PID_2308_BST_IPEAK_START_BIT))

#define AW_PID_2308_BST_IPEAK_1P5A		(0)
#define AW_PID_2308_BST_IPEAK_1P5A_VALUE	\
	(AW_PID_2308_BST_IPEAK_1P5A << AW_PID_2308_BST_IPEAK_START_BIT)

#define AW_PID_2308_BST_IPEAK_1P75A		(1)
#define AW_PID_2308_BST_IPEAK_1P75A_VALUE	\
	(AW_PID_2308_BST_IPEAK_1P75A << AW_PID_2308_BST_IPEAK_START_BIT)

#define AW_PID_2308_BST_IPEAK_2P0A		(2)
#define AW_PID_2308_BST_IPEAK_2P0A_VALUE	\
	(AW_PID_2308_BST_IPEAK_2P0A << AW_PID_2308_BST_IPEAK_START_BIT)

#define AW_PID_2308_BST_IPEAK_2P25A		(3)
#define AW_PID_2308_BST_IPEAK_2P25A_VALUE	\
	(AW_PID_2308_BST_IPEAK_2P25A << AW_PID_2308_BST_IPEAK_START_BIT)

#define AW_PID_2308_BST_IPEAK_2P5A		(4)
#define AW_PID_2308_BST_IPEAK_2P5A_VALUE	\
	(AW_PID_2308_BST_IPEAK_2P5A << AW_PID_2308_BST_IPEAK_START_BIT)

#define AW_PID_2308_BST_IPEAK_2P75A		(5)
#define AW_PID_2308_BST_IPEAK_2P75A_VALUE	\
	(AW_PID_2308_BST_IPEAK_2P75A << AW_PID_2308_BST_IPEAK_START_BIT)

#define AW_PID_2308_BST_IPEAK_3P0A		(6)
#define AW_PID_2308_BST_IPEAK_3P0A_VALUE	\
	(AW_PID_2308_BST_IPEAK_3P0A << AW_PID_2308_BST_IPEAK_START_BIT)

#define AW_PID_2308_BST_IPEAK_3P25A		(7)
#define AW_PID_2308_BST_IPEAK_3P25A_VALUE	\
	(AW_PID_2308_BST_IPEAK_3P25A << AW_PID_2308_BST_IPEAK_START_BIT)

#define AW_PID_2308_BST_IPEAK_3P5A		(8)
#define AW_PID_2308_BST_IPEAK_3P5A_VALUE	\
	(AW_PID_2308_BST_IPEAK_3P5A << AW_PID_2308_BST_IPEAK_START_BIT)

#define AW_PID_2308_BST_IPEAK_3P75A		(9)
#define AW_PID_2308_BST_IPEAK_3P75A_VALUE	\
	(AW_PID_2308_BST_IPEAK_3P75A << AW_PID_2308_BST_IPEAK_START_BIT)

#define AW_PID_2308_BST_IPEAK_4A		(10)
#define AW_PID_2308_BST_IPEAK_4A_VALUE	\
	(AW_PID_2308_BST_IPEAK_4A << AW_PID_2308_BST_IPEAK_START_BIT)

#define AW_PID_2308_BST_IPEAK_4P25A		(11)
#define AW_PID_2308_BST_IPEAK_4P25A_VALUE	\
	(AW_PID_2308_BST_IPEAK_4P25A << AW_PID_2308_BST_IPEAK_START_BIT)

#define AW_PID_2308_BST_IPEAK_4P50A		(12)
#define AW_PID_2308_BST_IPEAK_4P50A_VALUE	\
	(AW_PID_2308_BST_IPEAK_4P50A << AW_PID_2308_BST_IPEAK_START_BIT)

#define AW_PID_2308_BST_IPEAK_4P75A		(13)
#define AW_PID_2308_BST_IPEAK_4P75A_VALUE	\
	(AW_PID_2308_BST_IPEAK_4P75A << AW_PID_2308_BST_IPEAK_START_BIT)

#define AW_PID_2308_BST_IPEAK_5P0A		(14)
#define AW_PID_2308_BST_IPEAK_5P0A_VALUE	\
	(AW_PID_2308_BST_IPEAK_5P0A << AW_PID_2308_BST_IPEAK_START_BIT)

#define AW_PID_2308_BST_IPEAK_5P25A		(15)
#define AW_PID_2308_BST_IPEAK_5P25A_VALUE	\
	(AW_PID_2308_BST_IPEAK_5P25A << AW_PID_2308_BST_IPEAK_START_BIT)

#define AW_PID_2308_BST_IPEAK_DEFAULT	(5)
#define AW_PID_2308_BST_IPEAK_DEFAULT_VALUE	\
	(AW_PID_2308_BST_IPEAK_DEFAULT << AW_PID_2308_BST_IPEAK_START_BIT)

/* BST_TDEG bit 11:8 (BSTCTRL2 0x61) */
#define AW_PID_2308_BST_TDEG_START_BIT	(8)
#define AW_PID_2308_BST_TDEG_BITS_LEN	(4)
#define AW_PID_2308_BST_TDEG_MASK		\
	(~(((1<<AW_PID_2308_BST_TDEG_BITS_LEN)-1) << AW_PID_2308_BST_TDEG_START_BIT))

#define AW_PID_2308_BST_TDEG_0P50_MS	(0)
#define AW_PID_2308_BST_TDEG_0P50_MS_VALUE	\
	(AW_PID_2308_BST_TDEG_0P50_MS << AW_PID_2308_BST_TDEG_START_BIT)

#define AW_PID_2308_BST_TDEG_1P00_MS	(1)
#define AW_PID_2308_BST_TDEG_1P00_MS_VALUE	\
	(AW_PID_2308_BST_TDEG_1P00_MS << AW_PID_2308_BST_TDEG_START_BIT)

#define AW_PID_2308_BST_TDEG_2P00_MS	(2)
#define AW_PID_2308_BST_TDEG_2P00_MS_VALUE	\
	(AW_PID_2308_BST_TDEG_2P00_MS << AW_PID_2308_BST_TDEG_START_BIT)

#define AW_PID_2308_BST_TDEG_4P00_MS	(3)
#define AW_PID_2308_BST_TDEG_4P00_MS_VALUE	\
	(AW_PID_2308_BST_TDEG_4P00_MS << AW_PID_2308_BST_TDEG_START_BIT)

#define AW_PID_2308_BST_TDEG_8P00_MS	(4)
#define AW_PID_2308_BST_TDEG_8P00_MS_VALUE	\
	(AW_PID_2308_BST_TDEG_8P00_MS << AW_PID_2308_BST_TDEG_START_BIT)

#define AW_PID_2308_BST_TDEG_10P7_MS	(5)
#define AW_PID_2308_BST_TDEG_10P7_MS_VALUE	\
	(AW_PID_2308_BST_TDEG_10P7_MS << AW_PID_2308_BST_TDEG_START_BIT)

#define AW_PID_2308_BST_TDEG_13P3_MS	(6)
#define AW_PID_2308_BST_TDEG_13P3_MS_VALUE	\
	(AW_PID_2308_BST_TDEG_13P3_MS << AW_PID_2308_BST_TDEG_START_BIT)

#define AW_PID_2308_BST_TDEG_16P0_MS	(7)
#define AW_PID_2308_BST_TDEG_16P0_MS_VALUE	\
	(AW_PID_2308_BST_TDEG_16P0_MS << AW_PID_2308_BST_TDEG_START_BIT)

#define AW_PID_2308_BST_TDEG_18P6_MS	(8)
#define AW_PID_2308_BST_TDEG_18P6_MS_VALUE	\
	(AW_PID_2308_BST_TDEG_18P6_MS << AW_PID_2308_BST_TDEG_START_BIT)

#define AW_PID_2308_BST_TDEG_21P3_MS	(9)
#define AW_PID_2308_BST_TDEG_21P3_MS_VALUE	\
	(AW_PID_2308_BST_TDEG_21P3_MS << AW_PID_2308_BST_TDEG_START_BIT)

#define AW_PID_2308_BST_TDEG_24P0_MS	(10)
#define AW_PID_2308_BST_TDEG_24P0_MS_VALUE	\
	(AW_PID_2308_BST_TDEG_24P0_MS << AW_PID_2308_BST_TDEG_START_BIT)

#define AW_PID_2308_BST_TDEG_32P0_MS	(11)
#define AW_PID_2308_BST_TDEG_32P0_MS_VALUE	\
	(AW_PID_2308_BST_TDEG_32P0_MS << AW_PID_2308_BST_TDEG_START_BIT)

#define AW_PID_2308_BST_TDEG_64P0_MS	(12)
#define AW_PID_2308_BST_TDEG_64P0_MS_VALUE	\
	(AW_PID_2308_BST_TDEG_64P0_MS << AW_PID_2308_BST_TDEG_START_BIT)

#define AW_PID_2308_BST_TDEG_128_MS		(13)
#define AW_PID_2308_BST_TDEG_128_MS_VALUE	\
	(AW_PID_2308_BST_TDEG_128_MS << AW_PID_2308_BST_TDEG_START_BIT)

#define AW_PID_2308_BST_TDEG_256_MS		(14)
#define AW_PID_2308_BST_TDEG_256_MS_VALUE	\
	(AW_PID_2308_BST_TDEG_256_MS << AW_PID_2308_BST_TDEG_START_BIT)

#define AW_PID_2308_BST_TDEG_1200_MS	(15)
#define AW_PID_2308_BST_TDEG_1200_MS_VALUE	\
	(AW_PID_2308_BST_TDEG_1200_MS << AW_PID_2308_BST_TDEG_START_BIT)

#define AW_PID_2308_BST_TDEG_DEFAULT	(11)
#define AW_PID_2308_BST_TDEG_DEFAULT_VALUE	\
	(AW_PID_2308_BST_TDEG_DEFAULT << AW_PID_2308_BST_TDEG_START_BIT)

/* BST_VOUT_SET bit 7:0 (BSTCTRL2 0x61) */
#define AW_PID_2308_BST_VOUT_SET_START_BIT	(0)
#define AW_PID_2308_BST_VOUT_SET_BITS_LEN	(8)
#define AW_PID_2308_BST_VOUT_SET_MASK	\
	(~(((1<<AW_PID_2308_BST_VOUT_SET_BITS_LEN)-1) << AW_PID_2308_BST_VOUT_SET_START_BIT))

#define AW_PID_2308_BST_VOUT_SET_3P5V	(0)
#define AW_PID_2308_BST_VOUT_SET_3P5V_VALUE	\
	(AW_PID_2308_BST_VOUT_SET_3P5V << AW_PID_2308_BST_VOUT_SET_START_BIT)

#define AW_PID_2308_BST_VOUT_SET_3P5417V	(1)
#define AW_PID_2308_BST_VOUT_SET_3P5417V_VALUE	\
	(AW_PID_2308_BST_VOUT_SET_3P5417V << AW_PID_2308_BST_VOUT_SET_START_BIT)

#define AW_PID_2308_BST_VOUT_SET_3P5834V	(2)
#define AW_PID_2308_BST_VOUT_SET_3P5834V_VALUE	\
	(AW_PID_2308_BST_VOUT_SET_3P5834V << AW_PID_2308_BST_VOUT_SET_START_BIT)

#define AW_PID_2308_BST_VOUT_SET_3P6251V	(3)
#define AW_PID_2308_BST_VOUT_SET_3P6251V_VALUE	\
	(AW_PID_2308_BST_VOUT_SET_3P6251V << AW_PID_2308_BST_VOUT_SET_START_BIT)

#define AW_PID_2308_BST_VOUT_SET_3P6668V	(4)
#define AW_PID_2308_BST_VOUT_SET_3P6668V_VALUE	\
	(AW_PID_2308_BST_VOUT_SET_3P6668V << AW_PID_2308_BST_VOUT_SET_START_BIT)

#define AW_PID_2308_BST_VOUT_SET_3P7085V	(5)
#define AW_PID_2308_BST_VOUT_SET_3P7085V_VALUE	\
	(AW_PID_2308_BST_VOUT_SET_3P7085V << AW_PID_2308_BST_VOUT_SET_START_BIT)

#define AW_PID_2308_BST_VOUT_SET_14P1335V	(255)
#define AW_PID_2308_BST_VOUT_SET_14P1335V_VALUE	\
	(AW_PID_2308_BST_VOUT_SET_14P1335V << AW_PID_2308_BST_VOUT_SET_START_BIT)

#define AW_PID_2308_BST_VOUT_SET_DEFAULT	(0xcc)
#define AW_PID_2308_BST_VOUT_SET_DEFAULT_VALUE	\
	(AW_PID_2308_BST_VOUT_SET_DEFAULT << AW_PID_2308_BST_VOUT_SET_START_BIT)

/* default value of BSTCTRL2 (0x61) */
/* #define AW_PID_2308_BSTCTRL2_DEFAULT		(0x5BCC) */

/* CCO_MUX bit 13 (DBGCTRL 0x1F) */
#define AW_PID_2308_CCO_MUX_START_BIT	(13)
#define AW_PID_2308_CCO_MUX_BITS_LEN	(1)
#define AW_PID_2308_CCO_MUX_MASK		\
	(~(((1<<AW_PID_2308_CCO_MUX_BITS_LEN)-1) << AW_PID_2308_CCO_MUX_START_BIT))

#define AW_PID_2308_CCO_MUX_DIVIDED		(0)
#define AW_PID_2308_CCO_MUX_DIVIDED_VALUE	\
	(AW_PID_2308_CCO_MUX_DIVIDED << AW_PID_2308_CCO_MUX_START_BIT)

#define AW_PID_2308_CCO_MUX_BYPASS		(1)
#define AW_PID_2308_CCO_MUX_BYPASS_VALUE	\
	(AW_PID_2308_CCO_MUX_BYPASS << AW_PID_2308_CCO_MUX_START_BIT)

#define AW_PID_2308_CCO_MUX_DEFAULT		(0)
#define AW_PID_2308_CCO_MUX_DEFAULT_VALUE	\
	(AW_PID_2308_CCO_MUX_DEFAULT << AW_PID_2308_CCO_MUX_START_BIT)

/* NOISE_GATE_EN bit 0 (NGCTRL3 0x5E) */
#define AW_PID_2308_NOISE_GATE_EN_START_BIT	(0)
#define AW_PID_2308_NOISE_GATE_EN_BITS_LEN	(1)
#define AW_PID_2308_NOISE_GATE_EN_MASK	\
	(~(((1<<AW_PID_2308_NOISE_GATE_EN_BITS_LEN)-1) << AW_PID_2308_NOISE_GATE_EN_START_BIT))

#define AW_PID_2308_NOISE_GATE_EN_DISABLE	(0)
#define AW_PID_2308_NOISE_GATE_EN_DISABLE_VALUE	\
	(AW_PID_2308_NOISE_GATE_EN_DISABLE << AW_PID_2308_NOISE_GATE_EN_START_BIT)

#define AW_PID_2308_NOISE_GATE_EN_ENABLE	(1)
#define AW_PID_2308_NOISE_GATE_EN_ENABLE_VALUE	\
	(AW_PID_2308_NOISE_GATE_EN_ENABLE << AW_PID_2308_NOISE_GATE_EN_START_BIT)

#define AW_PID_2308_NOISE_GATE_EN_DEFAULT	(0)
#define AW_PID_2308_NOISE_GATE_EN_DEFAULT_VALUE	\
	(AW_PID_2308_NOISE_GATE_EN_DEFAULT << AW_PID_2308_NOISE_GATE_EN_START_BIT)

/* DSMZTH bit 7:4 (NGCTRL3 0x5E) */
#define AW_PID_2308_DSMZTH_START_BIT	(4)
#define AW_PID_2308_DSMZTH_BITS_LEN		(4)
#define AW_PID_2308_DSMZTH_MASK			\
	(~(((1<<AW_PID_2308_DSMZTH_BITS_LEN)-1) << AW_PID_2308_DSMZTH_START_BIT))

#define AW_PID_2308_DSMZTH_NO_RESET		(0)
#define AW_PID_2308_DSMZTH_NO_RESET_VALUE	\
	(AW_PID_2308_DSMZTH_NO_RESET << AW_PID_2308_DSMZTH_START_BIT)

#define AW_PID_2308_DSMZTH_1P33MS		(1)
#define AW_PID_2308_DSMZTH_1P33MS_VALUE	\
	(AW_PID_2308_DSMZTH_1P33MS << AW_PID_2308_DSMZTH_START_BIT)

#define AW_PID_2308_DSMZTH_2P67MS		(2)
#define AW_PID_2308_DSMZTH_2P67MS_VALUE	\
	(AW_PID_2308_DSMZTH_2P67MS << AW_PID_2308_DSMZTH_START_BIT)

#define AW_PID_2308_DSMZTH_5P33MS		(3)
#define AW_PID_2308_DSMZTH_5P33MS_VALUE	\
	(AW_PID_2308_DSMZTH_5P33MS << AW_PID_2308_DSMZTH_START_BIT)

#define AW_PID_2308_DSMZTH_10P67MS		(4)
#define AW_PID_2308_DSMZTH_10P67MS_VALUE	\
	(AW_PID_2308_DSMZTH_10P67MS << AW_PID_2308_DSMZTH_START_BIT)

#define AW_PID_2308_DSMZTH_21P33MS		(5)
#define AW_PID_2308_DSMZTH_21P33MS_VALUE	\
	(AW_PID_2308_DSMZTH_21P33MS << AW_PID_2308_DSMZTH_START_BIT)

#define AW_PID_2308_DSMZTH_42P67MS		(6)
#define AW_PID_2308_DSMZTH_42P67MS_VALUE	\
	(AW_PID_2308_DSMZTH_42P67MS << AW_PID_2308_DSMZTH_START_BIT)

#define AW_PID_2308_DSMZTH_85P33MS		(7)
#define AW_PID_2308_DSMZTH_85P33MS_VALUE	\
	(AW_PID_2308_DSMZTH_85P33MS << AW_PID_2308_DSMZTH_START_BIT)

#define AW_PID_2308_DSMZTH_127P8MS		(8)
#define AW_PID_2308_DSMZTH_127P8MS_VALUE	\
	(AW_PID_2308_DSMZTH_127P8MS << AW_PID_2308_DSMZTH_START_BIT)

#define AW_PID_2308_DSMZTH_170P7MS		(9)
#define AW_PID_2308_DSMZTH_170P7MS_VALUE	\
	(AW_PID_2308_DSMZTH_170P7MS << AW_PID_2308_DSMZTH_START_BIT)

#define AW_PID_2308_DSMZTH_212P9MS		(10)
#define AW_PID_2308_DSMZTH_212P9MS_VALUE	\
	(AW_PID_2308_DSMZTH_212P9MS << AW_PID_2308_DSMZTH_START_BIT)

#define AW_PID_2308_DSMZTH_255P6MS		(11)
#define AW_PID_2308_DSMZTH_255P6MS_VALUE	\
	(AW_PID_2308_DSMZTH_255P6MS << AW_PID_2308_DSMZTH_START_BIT)

#define AW_PID_2308_DSMZTH_298P2MS		(12)
#define AW_PID_2308_DSMZTH_298P2MS_VALUE	\
	(AW_PID_2308_DSMZTH_298P2MS << AW_PID_2308_DSMZTH_START_BIT)

#define AW_PID_2308_DSMZTH_341P3MS		(13)
#define AW_PID_2308_DSMZTH_341P3MS_VALUE	\
	(AW_PID_2308_DSMZTH_341P3MS << AW_PID_2308_DSMZTH_START_BIT)

#define AW_PID_2308_DSMZTH_682P7MS		(14)
#define AW_PID_2308_DSMZTH_682P7MS_VALUE	\
	(AW_PID_2308_DSMZTH_682P7MS << AW_PID_2308_DSMZTH_START_BIT)

#define AW_PID_2308_DSMZTH_1370MS		(15)
#define AW_PID_2308_DSMZTH_1370MS_VALUE	\
	(AW_PID_2308_DSMZTH_1370MS << AW_PID_2308_DSMZTH_START_BIT)

#define AW_PID_2308_DSMZTH_DEFAULT		(0)
#define AW_PID_2308_DSMZTH_DEFAULT_VALUE	\
	(AW_PID_2308_DSMZTH_DEFAULT << AW_PID_2308_DSMZTH_START_BIT)

/*monitor reg*/
#define AW_PID_2308_MONITOR_VBAT_RANGE		(6025)
#define AW_PID_2308_MONITOR_INT_10BIT		(1023)
#define AW_PID_2308_MONITOR_TEMP_SIGN_MASK	(~(1<<9))
#define AW_PID_2308_MONITOR_TEMP_NEG_MASK	(0xFC00)

/* detail information of registers end */

#endif  /* #ifndef  __AW_PID_2308_REG_H__ */