// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
 *
 */

#include <dt-bindings/display/drm_mipi_dsi.h>
#include <dt-bindings/display/media-bus-format.h>
#include "rk3399-vop-clk-set.dtsi"
#include <dt-bindings/input/input.h>

/ {
	compatible = "rockchip,android", "rockchip,rk3399";

	chosen: chosen {
		bootargs = "earlycon=uart8250,mmio32,0xff1a0000 coherent_pool=1m";
	};

	cpuinfo {
		compatible = "rockchip,cpuinfo";
		nvmem-cells = <&cpu_id>;
		nvmem-cell-names = "id";
	};

	debug: debug {
		compatible = "rockchip,debug";
		reg = <0x0 0xfe430000 0x0 0x1000>,
		      <0x0 0xfe432000 0x0 0x1000>,
		      <0x0 0xfe434000 0x0 0x1000>,
		      <0x0 0xfe436000 0x0 0x1000>,
		      <0x0 0xfe610000 0x0 0x1000>,
		      <0x0 0xfe710000 0x0 0x1000>;
	};

	fiq_debugger: fiq-debugger {
		compatible = "rockchip,fiq-debugger";
		rockchip,serial-id = <2>;
		rockchip,wake-irq = <0>;
		rockchip,irq-mode-enable = <1>;  /* If enable uart uses irq instead of fiq */
		rockchip,baudrate = <1500000>;  /* Only 115200 and 1500000 */
		pinctrl-names = "default";
		pinctrl-0 = <&uart2c_xfer>;
		interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		drm_logo: drm-logo@0 {
			compatible = "rockchip,drm-logo";
			reg = <0x0 0x0 0x0 0x0>;
		};

		vendor_storage_rm: vendor-storage-rm@00000000 {
			compatible = "rockchip,vendor-storage-rm";
			reg = <0x0 0x0 0x0 0x0>;
		};

		ramoops: ramoops@110000 {
			compatible = "ramoops";
			reg = <0x0 0x110000 0x0 0xf0000>;
			record-size = <0x20000>;
			console-size = <0x80000>;
			ftrace-size = <0x00000>;
			pmsg-size = <0x50000>;
		};

		secure_memory: secure-memory@20000000 {
			compatible = "rockchip,secure-memory";
			reg = <0x0 0x20000000 0x0 0x10000000>;
			status = "disabled";
		};

		stb_devinfo: stb-devinfo@00000000 {
			compatible = "rockchip,stb-devinfo";
			reg = <0x0 0x0 0x0 0x0>;
		};
	};

	gpio_keys: gpio-keys {
		compatible = "gpio-keys";
		autorepeat;
		pinctrl-names = "default";
		pinctrl-0 = <&pwrbtn>;

		power {
			debounce-interval = <100>;
			gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
			label = "GPIO Key Power";
			linux,code = <KEY_POWER>;
			wakeup-source;
		};
	};

	vendor_storage: vendor-storage {
		compatible = "rockchip,ram-vendor-storage";
		memory-region = <&vendor_storage_rm>;
		status = "okay";
	};

	rga: rga@ff680000 {
		compatible = "rockchip,rga2";
		dev_mode = <1>;
		reg = <0x0 0xff680000 0x0 0x1000>;
		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
		clock-names = "aclk_rga", "hclk_rga", "clk_rga";
		power-domains = <&power RK3399_PD_RGA>;
		status = "okay";
	};

	hdmi_dp_sound: hdmi-dp-sound {
		status = "disabled";
		compatible = "rockchip,rk3399-hdmi-dp";
		rockchip,cpu = <&i2s2>;
		rockchip,codec = <&hdmi>, <&cdn_dp>;
	};

	firmware {
		firmware_android: android {};

		optee: optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};
	};
};

&uart2 {
	status = "disabled";
};

&vopb {
	support-multi-area;
	status = "okay";
};

&vopb_mmu {
	status = "okay";
};

&vopl {
	support-multi-area;
	status = "okay";
};

&vopl_mmu {
	status = "okay";
};

&hdmi {
	#address-cells = <1>;
	#size-cells = <0>;
	#sound-dai-cells = <0>;
	ddc-i2c-scl-high-time-ns = <9625>;
	ddc-i2c-scl-low-time-ns = <10000>;
	status = "okay";
};

&display_subsystem {
	status = "okay";

	ports = <&vopb_out>, <&vopl_out>;
	logo-memory-region = <&drm_logo>;
	secure-memory-region = <&secure_memory>;
	route {
		route_hdmi: route-hdmi {
			status = "disabled";
			logo,uboot = "logo.bmp";
			logo,kernel = "logo_kernel.bmp";
			logo,mode = "center";
			charge_logo,mode = "center";
			connect = <&vopb_out_hdmi>;
		};

		route_dsi: route-dsi {
			status = "disabled";
			logo,uboot = "logo.bmp";
			logo,kernel = "logo_kernel.bmp";
			logo,mode = "center";
			charge_logo,mode = "center";
			connect = <&vopb_out_dsi>;
		};

		route_dsi1: route-dsi1 {
			status = "disabled";
			logo,uboot = "logo.bmp";
			logo,kernel = "logo_kernel.bmp";
			logo,mode = "center";
			charge_logo,mode = "center";
			connect = <&vopl_out_dsi1>;
		};

		route_edp: route-edp {
			status = "disabled";
			logo,uboot = "logo.bmp";
			logo,kernel = "logo_kernel.bmp";
			logo,mode = "center";
			charge_logo,mode = "center";
			connect = <&vopb_out_edp>;
		};
	};
};

&dsi {
	panel@0 {
		reg = <0>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;

				panel_in_dsi: endpoint {
					remote-endpoint = <&dsi_out_panel>;
				};
			};
		};
	};

	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@1 {
			reg = <1>;

			dsi_out_panel: endpoint {
				remote-endpoint = <&panel_in_dsi>;
			};
		};
	};
};

&i2s2 {
	#sound-dai-cells = <0>;
	rockchip,bclk-fs = <128>;
};

&rkvdec {
	status = "okay";
};

&vdec_mmu {
	status = "okay";
};

&usbdrd_dwc3_0 {
	dr_mode = "otg";
};

&iep {
	status = "okay";
};

&iep_mmu {
	status = "okay";
};

&mpp_srv {
	status = "okay";
};

&vdpu {
	status = "okay";
};

&vepu {
	status = "okay";
};

&vpu_mmu {
	status = "okay";
};

&pvtm {
	status = "okay";
};

&rng {
	status = "okay";
};

&pinctrl {
	isp {
		cif_clkout: cif-clkout {
			rockchip,pins =
				/*cif_clkout*/
				<2 RK_PB3 3 &pcfg_pull_none>;
		};

		isp_dvp_d0d7: isp-dvp-d0d7 {
			rockchip,pins =
				/*cif_data0*/
				<2 RK_PA0 3 &pcfg_pull_none>,
				/*cif_data1*/
				<2 RK_PA1 3 &pcfg_pull_none>,
				/*cif_data2*/
				<2 RK_PA2 3 &pcfg_pull_none>,
				/*cif_data3*/
				<2 RK_PA3 3 &pcfg_pull_none>,
				/*cif_data4*/
				<2 RK_PA4 3 &pcfg_pull_none>,
				/*cif_data5*/
				<2 RK_PA5 3 &pcfg_pull_none>,
				/*cif_data6*/
				<2 RK_PA6 3 &pcfg_pull_none>,
				/*cif_data7*/
				<2 RK_PA7 3 &pcfg_pull_none>,
				/*cif_sync*/
				<2 RK_PB0 3 &pcfg_pull_none>,
				/*cif_href*/
				<2 RK_PB1 3 &pcfg_pull_none>,
				/*cif_clkin*/
				<2 RK_PB2 3 &pcfg_pull_none>;
		};
	};

	buttons {
		pwrbtn: pwrbtn {
			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
		};
	};
};