// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
 */

/ {
	memory: memory {
		device_type = "memory";
		reg = <0x00000000 0x08000000>;
	};

	ramdisk: ramdisk {
		compatible = "rockchip,ramdisk";
		memory-region = <&ramdisk_r>;
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		rtos: rtos@40000 {
			reg = <0x40000 0x40000>;
		};

		meta: meta@800000 {
			/* reg's offset MUST match with RTOS */
			reg = <0x00800000 0x60000>;
		};

		rkisp_thunderboot: rkisp@860000 {
			/* reg's offset MUST match with RTOS */
			/*
			 * vicap, capture raw10, ceil(w*10/8/256)*256*h *4(buf num)
			 * e.g. 1920x1080: 0xa8c000
			 */
			reg = <0x00860000 0xa8c000>;
		};

		ramdisk_r: ramdisk_r {
			reg = <0x12ec000 (10 * 0x00100000)>;
		};

		ramdisk_c: ramdisk_c {
			reg = <0x1cec000 (5 * 0x00100000)>;
		};

		rkisp1_thunderboot: rkisp1_thunderboot {
			/* vicap capture for other camera */
		};
	};

	thunder_boot_rkisp: thunder-boot-rkisp {
		compatible = "rockchip,thunder-boot-rkisp";
		clocks = <&cru ACLK_ISP3P2>, <&cru HCLK_ISP3P2>,
			 <&cru CLK_CORE_ISP3P2>, <&cru ISP0CLK_VICAP>,
			 <&cru ACLK_VICAP>, <&cru HCLK_VICAP>,
			 <&cru DCLK_VICAP>, <&cru PCLK_VICAP>,
			 <&cru I0CLK_VICAP>, <&cru I1CLK_VICAP>,
			 <&cru RX0PCLK_VICAP>, <&cru RX1PCLK_VICAP>,
			 <&cru ISP0CLK_VICAP>, <&cru SCLK_VICAP_M0>,
			 <&cru SCLK_VICAP_M1>, <&cru PCLK_VICAP_VEPU>,
			 <&cru PCLK_CSIHOST0>, <&cru CLK_RXBYTECLKHS_0>,
			 <&cru PCLK_CSIHOST1>, <&cru CLK_RXBYTECLKHS_1>,
			 <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
		clock-names = "aclk_isp", "hclk_isp",
			      "clk_isp_core", "clk_isp_core_vicap",
			      "aclk_cif","hclk_cif",
			      "dclk_cif", "pclk_cif",
			      "i0clk_cif", "i1clk_cif",
			      "rx0clk_cif", "rx1clk_cif",
			      "isp0clk_cif", "sclk_m0_cif",
			      "sclk_m1_cif", "pclk_vepu_cif",
			      "pclk_csi2host0", "clk_rxbyte_hs0",
			      "pclk_csi2host1", "clk_rxbyte_hs1",
			      "i2c", "pclk";
		status = "okay";
	};

	thunder_boot_service: thunder-boot-service {
		compatible = "rockchip,thunder-boot-service";
		mbox-names = "amp-rx";
		mboxes = <&mailbox 1>;
		resets = <&cru SRST_CORE_MCU>, <&cru SRST_CORE_MCU_PWRUP>,
			 <&cru SRST_CORE_MCU_CPU>, <&cru SRST_T_CORE_MCU_CPU>;
		reset-names = "core_mcu", "core_mcu_pwrup",
			      "core_mcu_cpu", "t_core_mcu_cpu";
		memory-region = <&rtos>;
		status = "disabled";
	};
};

&hw_decompress {
	status = "okay";
	memory-region = <&ramdisk_c>;
};

&rkisp_vir0 {
	memory-region-thunderboot = <&rkisp_thunderboot>;
};

&rkvenc {
	assigned-clocks = <&cru CLK_CORE_VEPU>;
	assigned-clock-rates = <410000000>;
};