// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
 */

#include "rv1106.dtsi"

/ {
	compatible = "rockchip,rv1103";

	aliases {
		/delete-property/ gpio2;
	};
};

/delete-node/ &gpio2;

&acodec {
	compatible = "rockchip,rv1103-codec";
};

&cpu0_opp_table {
	/delete-node/ opp-1200000000;
	/delete-node/ opp-1296000000;
	/delete-node/ opp-1416000000;
	/delete-node/ opp-1512000000;
	/delete-node/ opp-1608000000;
};

&cru {
	assigned-clocks =
		<&cru PLL_GPLL>, <&cru PLL_CPLL>,
		<&cru ARMCLK>,
		<&cru ACLK_PERI_ROOT>, <&cru HCLK_PERI_ROOT>,
		<&cru PCLK_PERI_ROOT>, <&cru ACLK_BUS_ROOT>,
		<&cru PCLK_TOP_ROOT>, <&cru PCLK_PMU_ROOT>,
		<&cru HCLK_PMU_ROOT>, <&cru CLK_339M_SRC>;
	assigned-clock-rates =
		<1188000000>, <1000000000>,
		<1104000000>,
		<400000000>, <200000000>,
		<100000000>, <300000000>,
		<100000000>, <100000000>,
		<200000000>, <264000000>;
};

&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c3m1_xfer>;
};

&i2c4 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c3m1_xfer>;
};

&u2phy_otg {
	rockchip,vbus-always-on;
};