// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
 */

#include <dt-bindings/clock/rockchip,rk3506-cru.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
#include <dt-bindings/suspend/rockchip-rk3506.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	compatible = "rockchip,rk3502";

	interrupt-parent = <&gic>;

	aliases {
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		gpio2 = &gpio2;
		gpio3 = &gpio3;
		gpio4 = &gpio4;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
		serial4 = &uart4;
		serial5 = &uart5;
		spi0 = &spi0;
		spi1 = &spi1;
		spi2 = &fspi;
		spi3 = &flexbus_fspi;
		spi4 = &flexbus_spi;
	};

	clocks {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		clk_rc: clk-rc {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <400000>;
			clock-output-names = "clk_rc";
		};

		xin24m: xin24m {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <24000000>;
			clock-output-names = "xin24m";
		};

		xin32k: xin32k {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
			clock-output-names = "xin32k";
		};

		clk_spdifrx_to_asrc: clk-spdifrx-to-asrc {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
			clock-output-names = "clk_spdifrx_to_asrc";
		};

		mclkin_sai0: mclkin-sai0 {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
			clock-output-names = "sai0_mclk_in";
		};

		mclkin_sai1: mclkin-sai1 {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
			clock-output-names = "sai1_mclk_in";
		};

		mclkin_sai2: mclkin-sai2 {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
			clock-output-names = "sai2_mclk_in";
		};

		mclkin_sai3: mclkin-sai3 {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
			clock-output-names = "sai3_mclk_in";
		};

		mclkout_sai0: mclkout-sai0@ff910004 {
			compatible = "rockchip,clk-out";
			reg = <0xff910004 0x4>;
			clocks = <&cru MCLK_OUT_SAI0>;
			#clock-cells = <0>;
			clock-output-names = "mclk_sai0_to_io";
			rockchip,bit-shift = <8>;
		};

		mclkout_sai1: mclkout-sai1@ff910004 {
			compatible = "rockchip,clk-out";
			reg = <0xff910004 0x4>;
			clocks = <&cru MCLK_OUT_SAI1>;
			#clock-cells = <0>;
			clock-output-names = "mclk_sai1_to_io";
			rockchip,bit-shift = <9>;
		};

		mclkout_sai2: mclkout-sai2@ff288004 {
			compatible = "rockchip,clk-out";
			reg = <0xff288004 0x4>;
			clocks = <&cru MCLK_OUT_SAI2>;
			#clock-cells = <0>;
			clock-output-names = "mclk_sai2_to_io";
			rockchip,bit-shift = <2>;
		};

		mclkout_sai3: mclkout-sai3@ff288004 {
			compatible = "rockchip,clk-out";
			reg = <0xff288004 0x4>;
			clocks = <&cru MCLK_OUT_SAI3>;
			#clock-cells = <0>;
			clock-output-names = "mclk_sai3_to_io";
			rockchip,bit-shift = <3>;
		};

		pvtpll_core: pvtpll-core@ff840000 {
			compatible = "rockchip,rk3506-core-pvtpll", "syscon";
			reg = <0xff840000 0x100>;
			clocks = <&cru ARMCLK>;
			#clock-cells = <0>;
			clock-output-names = "clk_core_pvtpll";
			assigned-clocks = <&pvtpll_core>;
			assigned-clock-rates = <1200000000>;
			nvmem-cells = <&cpu_opp_info>, <&specification_serial_number>;
			nvmem-cell-names = "opp-info", "specification_serial_number";
		};

		sai0_fs: sai0-fs {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
			clock-output-names = "sai0_fs";
		};

		sai1_fs: sai1-fs {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
			clock-output-names = "sai1_fs";
		};

		sai2_fs: sai2-fs {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
			clock-output-names = "sai2_fs";
		};

		sai3_fs: sai3-fs {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
			clock-output-names = "sai3_fs";
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@f00 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0xf00>;
			enable-method = "psci";
			clocks = <&cru ARMCLK>;
			operating-points-v2 = <&cpu0_opp_table>;
		};

		cpu1: cpu@f01 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0xf01>;
			enable-method = "psci";
			clocks = <&cru ARMCLK>;
			operating-points-v2 = <&cpu0_opp_table>;
		};

		cpu2: cpu@f02 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0xf02>;
			enable-method = "psci";
			clocks = <&cru ARMCLK>;
			operating-points-v2 = <&cpu0_opp_table>;
		};
	};

	cpu0_opp_table: cpu0-opp-table {
		compatible = "operating-points-v2";
		opp-shared;

		mbist-vmin = <850000 900000 975000>;
		nvmem-cells = <&cpu_leakage>, <&cpu_opp_info>, <&cpu_mbist_vmin>, <&cpu_pvtpll>,
			      <&specification_serial_number>;
		nvmem-cell-names = "leakage", "opp-info", "mbist-vmin", "pvtm",
				   "specification_serial_number";

		rockchip,temp-freq-table = <
			85000	1008000
			100000	600000
		>;

		rockchip,supported-hw;
		rockchip,pvtm-voltage-sel = <
			0	1520	0
			1521	1584	1
			1585	1648	2
			1649	1712	3
			1713	1776	4
			1777	1840	5
			1841	1904	6
			1905	1968	7
			1969	9999	8
		>;
		rockchip,pvtm-pvtpll;
		rockchip,pvtm-offset = <0x18>;
		rockchip,pvtm-sample-time = <500>;
		rockchip,pvtm-freq = <1608000>;
		rockchip,pvtm-volt = <1000000>;
		rockchip,pvtm-ref-temp = <40>;
		rockchip,pvtm-temp-prop = <0 0>;
		rockchip,pvtm-thermal-zone = "soc-thermal";
		rockchip,grf = <&pvtpll_core>;
		rockchip,temp-hysteresis = <5000>;
		rockchip,low-temp = <10000>;
		rockchip,low-temp-min-volt = <950000>;

		opp-600000000 {
			opp-supported-hw = <0xf9 0xffff>;
			opp-hz = /bits/ 64 <600000000>;
			opp-microvolt = <850000 850000 1100000>;
			opp-microvolt-L0 = <900000 900000 1100000>;
			opp-microvolt-L1 = <900000 900000 1100000>;
			opp-microvolt-L2 = <875000 875000 1100000>;
			clock-latency-ns = <40000>;
			opp-suspend;
		};
		opp-800000000 {
			opp-supported-hw = <0xf9 0xffff>;
			opp-hz = /bits/ 64 <800000000>;
			opp-microvolt = <850000 850000 1100000>;
			opp-microvolt-L0 = <900000 900000 1100000>;
			opp-microvolt-L1 = <900000 900000 1100000>;
			opp-microvolt-L2 = <875000 875000 1100000>;
			clock-latency-ns = <40000>;
		};
		opp-1008000000 {
			opp-supported-hw = <0xf9 0xffff>;
			opp-hz = /bits/ 64 <1008000000>;
			opp-microvolt = <850000 850000 1100000>;
			opp-microvolt-L0 = <900000 900000 1100000>;
			opp-microvolt-L1 = <900000 900000 1100000>;
			opp-microvolt-L2 = <875000 875000 1100000>;
			clock-latency-ns = <40000>;
		};
		opp-1200000000 {
			opp-supported-hw = <0xf9 0xffff>;
			opp-hz = /bits/ 64 <1200000000>;
			opp-microvolt = <900000 900000 1100000>;
			clock-latency-ns = <40000>;
		};
		opp-1296000000 {
			opp-supported-hw = <0xf9 0xffff>;
			opp-hz = /bits/ 64 <1296000000>;
			opp-microvolt = <900000 900000 1100000>;
			opp-microvolt-L0 = <950000 950000 1100000>;
			opp-microvolt-L1 = <925000 925000 1100000>;
			clock-latency-ns = <40000>;
		};
		opp-1416000000 {
			opp-supported-hw = <0xf9 0xffff>;
			opp-hz = /bits/ 64 <1416000000>;
			opp-microvolt = <900000 900000 1100000>;
			opp-microvolt-L0 = <1000000 1000000 1100000>;
			opp-microvolt-L1 = <975000 975000 1100000>;
			opp-microvolt-L2 = <950000 950000 1100000>;
			opp-microvolt-L3 = <925000 925000 1100000>;
			clock-latency-ns = <40000>;
		};
		opp-1512000000 {
			opp-supported-hw = <0xf9 0xffff>;
			opp-hz = /bits/ 64 <1512000000>;
			opp-microvolt = <900000 900000 1100000>;
			opp-microvolt-L0 = <1050000 1050000 1100000>;
			opp-microvolt-L1 = <1025000 1025000 1100000>;
			opp-microvolt-L2 = <1000000 1000000 1100000>;
			opp-microvolt-L3 = <975000 975000 1100000>;
			opp-microvolt-L4 = <950000 950000 1100000>;
			opp-microvolt-L5 = <925000 925000 1100000>;
			clock-latency-ns = <40000>;
		};
		opp-1608000000 {
			opp-supported-hw = <0xf9 0xffff>;
			opp-hz = /bits/ 64 <1608000000>;
			opp-microvolt = <950000 950000 1100000>;
			opp-microvolt-L0 = <1100000 1100000 1100000>;
			opp-microvolt-L1 = <1075000 1075000 1100000>;
			opp-microvolt-L2 = <1050000 1050000 1100000>;
			opp-microvolt-L3 = <1025000 1025000 1100000>;
			opp-microvolt-L4 = <1000000 1000000 1100000>;
			opp-microvolt-L5 = <975000 975000 1100000>;
			clock-latency-ns = <40000>;
		};

		/* RK3506J cpu OPPs */
		opp-j-600000000 {
			opp-supported-hw = <0x04 0xffff>;
			opp-hz = /bits/ 64 <600000000>;
			opp-microvolt = <900000 900000 1050000>;
			clock-latency-ns = <40000>;
			opp-suspend;
		};
		opp-j-800000000 {
			opp-supported-hw = <0x04 0xffff>;
			opp-hz = /bits/ 64 <800000000>;
			opp-microvolt = <900000 900000 1050000>;
			clock-latency-ns = <40000>;
		};
		opp-j-1008000000 {
			opp-supported-hw = <0x04 0xffff>;
			opp-hz = /bits/ 64 <1008000000>;
			opp-microvolt = <900000 900000 1050000>;
			clock-latency-ns = <40000>;
		};
		opp-j-1200000000 {
			opp-supported-hw = <0x04 0xffff>;
			opp-hz = /bits/ 64 <1200000000>;
			opp-microvolt = <900000 900000 1050000>;
			clock-latency-ns = <40000>;
		};
		/*
		 * The Max frequency is 1200MHz in default normal mode.
		 * The Max frequency is 1512MHz in overdrive mode,
		 * but under the overdrive mode for a long time,
		 * the chipset may shorten the lifetime, especially in high
		 * temperature condition. Disable overdrive opps by default
		 * and you can enable them in dts file.
		 */
		cpu_opp_j_od_1296000000: opp-j-od-1296000000 {
			opp-supported-hw = <0x04 0xffff>;
			opp-hz = /bits/ 64 <1296000000>;
			opp-microvolt = <925000 925000 1050000>;
			opp-microvolt-L0 = <950000 950000 1050000>;
			opp-microvolt-L1 = <950000 950000 1050000>;
			clock-latency-ns = <40000>;
			status = "disabled";
		};
		cpu_opp_j_od_1416000000: opp-j-od-1416000000 {
			opp-supported-hw = <0x04 0xffff>;
			opp-hz = /bits/ 64 <1416000000>;
			opp-microvolt = <925000 925000 1050000>;
			opp-microvolt-L0 = <1000000 1000000 1050000>;
			opp-microvolt-L1 = <1000000 1000000 1050000>;
			opp-microvolt-L2 = <975000 975000 1050000>;
			opp-microvolt-L3 = <950000 950000 1050000>;
			clock-latency-ns = <40000>;
			status = "disabled";
		};
		cpu_opp_j_od_1512000000: opp-j-od-1512000000 {
			opp-supported-hw = <0xf9 0xffff>;
			opp-hz = /bits/ 64 <1512000000>;
			opp-microvolt = <925000 925000 1050000>;
			opp-microvolt-L0 = <1050000 1050000 1050000>;
			opp-microvolt-L1 = <1050000 1050000 1050000>;
			opp-microvolt-L2 = <1025000 1025000 1050000>;
			opp-microvolt-L3 = <1000000 1000000 1050000>;
			opp-microvolt-L4 = <975000 975000 1050000>;
			opp-microvolt-L5 = <950000 950000 1050000>;
			clock-latency-ns = <40000>;
			status = "disabled";
		};
	};

	arm_pmu: arm-pmu {
		compatible = "arm,cortex-a7-pmu";
		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>;
	};

	cpuinfo {
		compatible = "rockchip,cpuinfo";
		nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>;
		nvmem-cell-names = "id", "cpu-version", "cpu-code";
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	reserved_memory: reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		trust@0 {
			reg = <0x0 0x62000>;
		};

		cma: linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			size = <0x0>;
			linux,cma-default;
		};

		drm_logo: drm-logo@0 {
			compatible = "rockchip,drm-logo";
			reg = <0x0 0x0>;
		};

		ramoops: ramoops@83000 {
			compatible = "ramoops";
			reg = <0x83000 0x2d000>;
			boot-log-size = <0xd000>;	/* do not change */
			boot-log-count = <0x1>;		/* do not change */
			console-size = <0x20000>;
			pmsg-size = <0x0>;
			ftrace-size = <0x0>;
			record-size = <0x0>;
		};
	};

	rockchip_suspend: rockchip-suspend {
		compatible = "rockchip,pm-config";
		status = "okay";

		rockchip,sleep-mode-config = <
			(0
			| RKPM_ARMOFF_DDRPD
			| RKPM_24M_OSC_DIS
			| RKPM_32K_CLK
			| RKPM_32K_SRC_RC
			)
		>;

		rockchip,wakeup-config = <
			(0
			| RKPM_GPIO0_WAKEUP_EN
			)
		>;
	};

	rockchip_system_monitor: rockchip-system-monitor {
		compatible = "rk3506,system-monitor";

		rockchip,thermal-zone = "soc-thermal";
		rockchip,temp-ddr-ref-mode = <
			(-40000)	1
			75000		4
		>;
	};

	thermal_zones: thermal-zones {
		soc_thermal: soc-thermal {
			polling-delay-passive = <20>; /* milliseconds */
			polling-delay = <1000>; /* milliseconds */
			thermal-sensors = <&tsadc 0>;
			trips {
				soc_crit: soc-crit {
					/* millicelsius */
					temperature = <115000>;
					/* millicelsius */
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>;
		clock-frequency = <24000000>;
	};

	dmac0: dma-controller@ff000000 {
		compatible = "arm,pl330", "arm,primecell";
		reg = <0xff000000 0x4000>;
		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_DMAC0>;
		clock-names = "apb_pclk";
		#dma-cells = <5>;
		arm,pl330-periph-burst;
	};

	dmac1: dma-controller@ff008000 {
		compatible = "arm,pl330", "arm,primecell";
		reg = <0xff008000 0x4000>;
		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_DMAC1>;
		clock-names = "apb_pclk";
		#dma-cells = <5>;
		arm,pl330-periph-burst;
	};

	i2c0: i2c@ff040000 {
		compatible = "rockchip,rk3506-i2c", "rockchip,rk3399-i2c";
		reg = <0xff040000 0x1000>;
		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
		clock-names = "i2c", "pclk";
		status = "disabled";
	};

	i2c1: i2c@ff050000 {
		compatible = "rockchip,rk3506-i2c", "rockchip,rk3399-i2c";
		reg = <0xff050000 0x1000>;
		interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
		clock-names = "i2c", "pclk";
		status = "disabled";
	};

	i2c2: i2c@ff060000 {
		compatible = "rockchip,rk3506-i2c", "rockchip,rk3399-i2c";
		reg = <0xff060000 0x1000>;
		interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
		clock-names = "i2c", "pclk";
		status = "disabled";
	};

	uart0: serial@ff0a0000 {
		compatible = "rockchip,rk3506-uart", "snps,dw-apb-uart";
		reg = <0xff0a0000 0x100>;
		interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <4>;
		dmas = <&dmac0 4 0xff2880a8 0x03000100 0x0 0x0>,
		       <&dmac0 5 0xff2880a8 0x0c000400 0x0 0x0>;
		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
		clock-names = "baudclk", "apb_pclk";
		pinctrl-names = "default";
		pinctrl-0 = <&uart0_xfer_pins>;
		status = "disabled";
	};

	uart1: serial@ff0b0000 {
		compatible = "rockchip,rk3506-uart", "snps,dw-apb-uart";
		reg = <0xff0b0000 0x100>;
		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <4>;
		dmas = <&dmac0 6 0xff2880a8 0x30001000 0x0 0x0>,
		       <&dmac0 7 0xff2880a8 0xc0004000 0x0 0x0>;
		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
		clock-names = "baudclk", "apb_pclk";
		status = "disabled";
	};

	uart2: serial@ff0c0000 {
		compatible = "rockchip,rk3506-uart", "snps,dw-apb-uart";
		reg = <0xff0c0000 0x100>;
		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <4>;
		dmas = <&dmac0 8 0xff2880ac 0x00030001 0x0 0x0>,
		       <&dmac0 9 0xff2880ac 0x000c0004 0x0 0x0>;
		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
		clock-names = "baudclk", "apb_pclk";
		status = "disabled";
	};

	uart3: serial@ff0d0000 {
		compatible = "rockchip,rk3506-uart", "snps,dw-apb-uart";
		reg = <0xff0d0000 0x100>;
		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <4>;
		dmas = <&dmac0 10 0xff2880ac 0x00300010 0x0 0x0>,
		       <&dmac0 11 0xff2880ac 0x00c00040 0x0 0x0>;
		clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
		clock-names = "baudclk", "apb_pclk";
		status = "disabled";
	};

	uart4: serial@ff0e0000 {
		compatible = "rockchip,rk3506-uart", "snps,dw-apb-uart";
		reg = <0xff0e0000 0x100>;
		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <4>;
		dmas = <&dmac1 12 0x0 0x0 0x0 0x0>, <&dmac1 13 0x0 0x0 0x0 0x0>;
		clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
		clock-names = "baudclk", "apb_pclk";
		status = "disabled";
	};

	spi0: spi@ff120000 {
		compatible = "rockchip,rk3506-spi", "rockchip,rk3066-spi";
		reg = <0xff120000 0x1000>;
		interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
		clock-names = "spiclk", "apb_pclk";
		dmas = <&dmac0 0 0xff2880a8 0x00030001 0x0 0x0>,
		       <&dmac0 1 0xff2880a8 0x000c0004 0x0 0x0>;
		dma-names = "tx", "rx";
		num-cs = <2>;
		pinctrl-names = "default";
		pinctrl-0 = <&spi0_csn0_pins &spi0_csn1_pins &spi0_clk_pins>;
		status = "disabled";
	};

	spi1: spi@ff130000 {
		compatible = "rockchip,rk3506-spi", "rockchip,rk3066-spi";
		reg = <0xff130000 0x1000>;
		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
		clock-names = "spiclk", "apb_pclk";
		dmas = <&dmac0 2 0xff2880a8 0x00300010 0x0 0x0>,
		       <&dmac0 3 0xff2880a8 0x00c00040 0x0 0x0>;
		dma-names = "tx", "rx";
		num-cs = <2>;
		pinctrl-names = "default";
		pinctrl-0 = <&spi1_csn0_pins &spi1_csn1_pins &spi1_clk_pins>;
		status = "disabled";
	};

	pwm1_8ch_0: pwm@ff170000 {
		compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm";
		reg = <0xff170000 0x200>;
		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
		clock-names = "pwm", "pclk";
		#pwm-cells = <3>;
		status = "disabled";
	};

	pwm1_8ch_1: pwm@ff171000 {
		compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm";
		reg = <0xff171000 0x200>;
		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
		clock-names = "pwm", "pclk";
		#pwm-cells = <3>;
		status = "disabled";
	};

	pwm1_8ch_2: pwm@ff172000 {
		compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm";
		reg = <0xff172000 0x200>;
		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
		clock-names = "pwm", "pclk";
		#pwm-cells = <3>;
		status = "disabled";
	};

	pwm1_8ch_3: pwm@ff173000 {
		compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm";
		reg = <0xff173000 0x200>;
		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
		clock-names = "pwm", "pclk";
		#pwm-cells = <3>;
		status = "disabled";
	};

	pwm1_8ch_4: pwm@ff174000 {
		compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm";
		reg = <0xff174000 0x200>;
		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
		clock-names = "pwm", "pclk";
		#pwm-cells = <3>;
		status = "disabled";
	};

	pwm1_8ch_5: pwm@ff175000 {
		compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm";
		reg = <0xff175000 0x200>;
		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
		clock-names = "pwm", "pclk";
		#pwm-cells = <3>;
		status = "disabled";
	};

	pwm1_8ch_6: pwm@ff176000 {
		compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm";
		reg = <0xff176000 0x200>;
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
		clock-names = "pwm", "pclk";
		#pwm-cells = <3>;
		status = "disabled";
	};

	pwm1_8ch_7: pwm@ff177000 {
		compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm";
		reg = <0xff177000 0x200>;
		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
		clock-names = "pwm", "pclk";
		#pwm-cells = <3>;
		status = "disabled";
	};

	hwlock0: hwspinlock@ff240000 {
		compatible = "rockchip,hwspinlock";
		reg = <0xff240000 0x20>;
		#hwlock-cells = <1>;
		rockchip,hwlock-num-locks = <8>;
		status = "disabled";
	};

	hwlock1: hwspinlock@ff241000 {
		compatible = "rockchip,hwspinlock";
		reg = <0xff241000 0x20>;
		#hwlock-cells = <1>;
		rockchip,hwlock-num-locks = <8>;
		status = "disabled";
	};

	hwlock2: hwspinlock@ff242000 {
		compatible = "rockchip,hwspinlock";
		reg = <0xff242000 0x20>;
		#hwlock-cells = <1>;
		rockchip,hwlock-num-locks = <8>;
		status = "disabled";
	};

	hwlock3: hwspinlock@ff243000 {
		compatible = "rockchip,hwspinlock";
		reg = <0xff243000 0x20>;
		#hwlock-cells = <1>;
		rockchip,hwlock-num-locks = <8>;
		status = "disabled";
	};

	wdt0: watchdog@ff260000 {
		compatible = "snps,dw-wdt";
		reg = <0xff260000 0x100>;
		clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>;
		clock-names = "tclk", "pclk";
		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	wdt1: watchdog@ff268000 {
		compatible = "snps,dw-wdt";
		reg = <0xff268000 0x100>;
		clocks = <&cru TCLK_WDT1>, <&cru PCLK_WDT1>;
		clock-names = "tclk", "pclk";
		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	grf: syscon@ff288000 {
		compatible = "rockchip,rk3506-grf", "syscon", "simple-mfd";
		reg = <0xff288000 0x4000>;
	};

	mailbox0: mailbox@ff290000 {
		compatible = "rockchip,rk3506-mailbox", "rockchip,rk3576-mailbox";
		reg = <0xff290000 0x20>;
		interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru PCLK_MAILBOX>;
		clock-names = "pclk_mailbox";
		#mbox-cells = <1>;
		status = "disabled";
	};

	mailbox1: mailbox@ff291000 {
		compatible = "rockchip,rk3506-mailbox", "rockchip,rk3576-mailbox";
		reg = <0xff291000 0x20>;
		interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru PCLK_MAILBOX>;
		clock-names = "pclk_mailbox";
		#mbox-cells = <1>;
		status = "disabled";
	};

	mailbox2: mailbox@ff292000 {
		compatible = "rockchip,rk3506-mailbox", "rockchip,rk3576-mailbox";
		reg = <0xff292000 0x20>;
		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru PCLK_MAILBOX>;
		clock-names = "pclk_mailbox";
		#mbox-cells = <1>;
		status = "disabled";
	};

	mailbox3: mailbox@ff293000 {
		compatible = "rockchip,rk3506-mailbox", "rockchip,rk3576-mailbox";
		reg = <0xff293000 0x20>;
		interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru PCLK_MAILBOX>;
		clock-names = "pclk_mailbox";
		#mbox-cells = <1>;
		status = "disabled";
	};

	usb2phy: usb2-phy@ff2b0000 {
		compatible = "rockchip,rk3506-usb2phy";
		reg = <0xff2b0000 0x8000>;
		clocks = <&cru CLK_REF_USBPHY_TOP>, <&cru PCLK_USBPHY>;
		clock-names = "phyclk", "apb_pclk";
		#clock-cells = <0>;
		rockchip,usbgrf = <&grf>;
		status = "disabled";

		u2phy_otg0: otg-port {
			#phy-cells = <0>;
			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "otg-bvalid",
					  "otg-id",
					  "linestate";
			status = "disabled";
		};

		u2phy_otg1: host-port {
			#phy-cells = <0>;
			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "otg-bvalid",
					  "otg-id",
					  "linestate";
			status = "disabled";
		};
	};

	sai0: sai@ff300000 {
		compatible = "rockchip,rk3506-sai", "rockchip,sai-v1";
		reg = <0xff300000 0x1000>;
		interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru MCLK_SAI0>, <&cru HCLK_SAI0>;
		clock-names = "mclk", "hclk";
		dmas = <&dmac1 1 0xff2880a4 0x01000000 0x0 0x0>,
		       <&dmac1 0 0xff2880a4 0x00800000 0x0 0x0>;
	//	dmas = <&dmac0 9 0xff2880a4 0x01000100 0xff2880ac 0x000c0000>,
	//	       <&dmac0 8 0xff2880a4 0x00800080 0xff2880ac 0x00030002>;
		dma-names = "tx", "rx";
		resets = <&cru SRST_M_SAI0>, <&cru SRST_H_SAI0>;
		reset-names = "m", "h";
		#sound-dai-cells = <0>;
		sound-name-prefix = "SAI0";
		pinctrl-names = "default";
		pinctrl-0 = <&sai0_lrck_pins
			     &sai0_sclk_pins
			     &sai0_sdi0_pins
			     &sai0_sdi1_pins
			     &sai0_sdi2_pins
			     &sai0_sdi3_pins
			     &sai0_sdo_pins>;
		status = "disabled";
	};

	sai1: sai@ff310000 {
		compatible = "rockchip,rk3506-sai", "rockchip,sai-v1";
		reg = <0xff310000 0x1000>;
		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru MCLK_SAI1>, <&cru HCLK_SAI1>;
		clock-names = "mclk", "hclk";
		dmas = <&dmac1 3  0xff2880a4 0x04000000 0x0 0x0>,
		       <&dmac1 2  0xff2880a4 0x02000000 0x0 0x0>;
	//	dmas = <&dmac0 11 0xff2880a4 0x04000400 0xff2880ac 0x00c00000>,
	//	       <&dmac0 10 0xff2880a4 0x02000200 0xff2880ac 0x00300020>;
		dma-names = "tx", "rx";
		resets = <&cru SRST_M_SAI1>, <&cru SRST_H_SAI1>;
		reset-names = "m", "h";
		#sound-dai-cells = <0>;
		sound-name-prefix = "SAI1";
		pinctrl-names = "default";
		pinctrl-0 = <&sai1_lrck_pins
			     &sai1_sclk_pins
			     &sai1_sdi_pins
			     &sai1_sdo0_pins
			     &sai1_sdo1_pins
			     &sai1_sdo2_pins
			     &sai1_sdo3_pins>;
		status = "disabled";
	};

	pdm: pdm@ff380000 {
		compatible = "rockchip,rk3506-pdm", "rockchip,rk3576-pdm";
		reg = <0xff380000 0x1000>;
		interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>, <&cru CLKOUT_PDM>;
		clock-names = "pdm_clk", "pdm_hclk", "pdm_clk_out";
		dmas = <&dmac1 9 0xff2880a4 0x00100000 0x0 0x0>;
	//	dmas = <&dmac0 5 0xff2880a4 0x00100010 0xff2880a8 0x0c000800>;
		dma-names = "rx";
		pinctrl-names = "default";
		pinctrl-0 = <&rm_io0_pdm_clk0
			     &rm_io0_pdm_clk1
			     &rm_io0_pdm_sdi0
			     &rm_io0_pdm_sdi1
			     &rm_io0_pdm_sdi2
			     &rm_io0_pdm_sdi3>;
		#sound-dai-cells = <0>;
		sound-name-prefix = "PDM0";
		status = "disabled";
	};

	spdif_tx: spdif-tx@ff3a0000 {
		compatible = "rockchip,rk3506-spdif", "rockchip,rk3066-spdif";
		reg = <0xff3a0000 0x1000>;
		interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru MCLK_SPDIFTX>, <&cru HCLK_SPDIFTX>;
		clock-names = "mclk", "hclk";
		dmas = <&dmac1 10 0xff2880a4 0x00200000 0xff2880ac 0x03000100>;
	//	dmas = <&dmac0 6  0xff2880a4 0x00200020 0xff2880a8 0x30000000>;
		dma-names = "tx";
		pinctrl-names = "default";
		pinctrl-0 = <&rm_io0_spdif_tx>;
		#sound-dai-cells = <0>;
		status = "disabled";
	};

	spdif_rx: spdif-rx@ff3b0000 {
		compatible = "rockchip,rk3506-spdifrx", "rockchip,rk3308-spdifrx";
		reg = <0xff3b0000 0x1000>;
		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru MCLK_SPDIFRX>, <&cru HCLK_SPDIFRX>;
		clock-names = "mclk", "hclk";
		dmas = <&dmac1 11 0xff2880a4 0x00400000 0xff2880ac 0x0c000400>;
	//	dmas = <&dmac0 7  0xff2880a4 0x00400040 0xff2880a8 0xc0000000>;
		dma-names = "rx";
		resets = <&cru SRST_SPDIFRX>;
		reset-names = "spdifrx-m";
		pinctrl-names = "default";
		pinctrl-0 = <&rm_io0_spdif_rx>;
		#sound-dai-cells = <0>;
		status = "disabled";
	};

	asrc0: asrc@ff3c0000 {
		compatible = "rockchip,rk3506-asrc";
		reg = <0xff3c0000 0x1000>;
		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru CLK_ASRC0>, <&cru HCLK_ASRC0>,
			 <&cru LRCK_ASRC0_SRC>, <&cru LRCK_ASRC0_DST>;
		clock-names = "mclk", "hclk",
			      "src_lrck", "dst_lrck";
	//	dmas = <&dmac0 0 0xff2880a4 0x00010001 0xff2880a8 0x00030002>,
	//	       <&dmac0 1 0xff2880a4 0x00020002 0xff2880a8 0x000c0008>;
		dmas = <&dmac1 16 0xff2880a4 0x00010000 0x0 0x0>,
		       <&dmac1 17 0xff2880a4 0x00020000 0x0 0x0>;
		dma-names = "rx", "tx";
		resets = <&cru SRST_ASRC0>, <&cru SRST_H_ASRC0>;
		reset-names = "m", "h";
		#sound-dai-cells = <0>;
		sound-name-prefix = "ASRC0";
		status = "disabled";
	};

	asrc1: asrc@ff3d0000 {
		compatible = "rockchip,rk3506-asrc";
		reg = <0xff3d0000 0x1000>;
		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru CLK_ASRC1>, <&cru HCLK_ASRC1>,
			 <&cru LRCK_ASRC1_SRC>, <&cru LRCK_ASRC1_DST>;
		clock-names = "mclk", "hclk",
			      "src_lrck", "dst_lrck";
	//	dmas = <&dmac0 2 0xff2880a4 0x00040004 0xff2880a8 0x00300020>,
	//	       <&dmac0 3 0xff2880a4 0x00080008 0xff2880a8 0x00c00080>;
		dmas = <&dmac1 18 0xff2880a4 0x00040000 0x0 0x0>,
		       <&dmac1 19 0xff2880a4 0x00080000 0x0 0x0>;
		dma-names = "rx", "tx";
		resets = <&cru SRST_ASRC1>, <&cru SRST_H_ASRC1>;
		reset-names = "m", "h";
		#sound-dai-cells = <0>;
		sound-name-prefix = "ASRC1";
		status = "disabled";
	};

	mmc: mmc@ff480000 {
		compatible = "rockchip,rk3506-dw-mshc", "rockchip,rk3288-dw-mshc";
		reg = <0xff480000 0x4000>;
		interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
		max-frequency = <150000000>;
		bus-width = <4>;
		clocks = <&cru HCLK_SDMMC>, <&cru CCLK_SRC_SDMMC>;
		clock-names = "biu", "ciu";
		fifo-depth = <0x100>;
		resets = <&cru SRST_H_SDMMC>;
		reset-names = "reset";
		status = "disabled";
	};

	fspi: spi@ff488000 {
		compatible = "rockchip,rk3506-fspi", "rockchip,fspi";
		reg = <0xff488000 0x4000>;
		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_FSPI>, <&cru HCLK_FSPI>;
		clock-names = "clk_sfc", "hclk_sfc";
		rockchip,grf = <&grf_pmu>;
		rockchip,max-dll = <0x17F>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	sai2: sai@ff498000 {
		compatible = "rockchip,rk3506-sai", "rockchip,sai-v1";
		reg = <0xff498000 0x1000>;
		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru MCLK_SAI2>, <&cru HCLK_SAI2>;
		clock-names = "mclk", "hclk";
		dmas = <&dmac1 5 0x0 0x0 0x0 0x0>, <&dmac1 4 0x0 0x0 0x0 0x0>;
		dma-names = "tx", "rx";
		resets = <&cru SRST_M_SAI2>, <&cru SRST_H_SAI2>;
		reset-names = "m", "h";
		#sound-dai-cells = <0>;
		sound-name-prefix = "SAI2";
		pinctrl-names = "default";
		pinctrl-0 = <&sai2m0_lrck_pins
			     &sai2m0_sclk_pins
			     &sai2m0_sdi_pins
			     &sai2m0_sdo_pins>;
		status = "disabled";
	};

	sai3: sai@ff4a0000 {
		compatible = "rockchip,rk3506-sai", "rockchip,sai-v1";
		reg = <0xff4a0000 0x1000>;
		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru MCLK_SAI3>, <&cru HCLK_SAI3>;
		clock-names = "mclk", "hclk";
		dmas = <&dmac1 6 0x0 0x0 0x0 0x0>, <&dmac1 7 0x0 0x0 0x0 0x0>;
		dma-names = "tx", "rx";
		resets = <&cru SRST_M_SAI3>, <&cru SRST_H_SAI3>;
		reset-names = "m", "h";
		#sound-dai-cells = <0>;
		sound-name-prefix = "SAI3";
		pinctrl-names = "default";
		pinctrl-0 = <&sai3_lrck_pins
			     &sai3_sclk_pins
			     &sai3_sdi_pins
			     &sai3_sdo_pins>;
		status = "disabled";
	};

	sai4: sai@ff4a8000 {
		compatible = "rockchip,rk3506-sai", "rockchip,sai-v1";
		reg = <0xff4a8000 0x1000>;
		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru MCLK_SAI4>, <&cru HCLK_SAI4>;
		clock-names = "mclk", "hclk";
		dmas = <&dmac1 8 0x0 0x0 0x0 0x0>;
		dma-names = "rx";
		resets = <&cru SRST_M_SAI4>, <&cru SRST_H_SAI4>;
		reset-names = "m", "h";
		#sound-dai-cells = <0>;
		sound-name-prefix = "SAI4";
		status = "disabled";
	};

	acdcdig_dsm: acdcdig-dsm@ff4b0000 {
		compatible = "rockchip,rk3506-dsm";
		reg = <0xff4b0000 0x1000>;
		clocks = <&cru MCLK_DSM>, <&cru HCLK_DSM>;
		clock-names = "dac", "pclk";
		resets = <&cru SRST_M_DSM>;
		reset-names = "reset" ;
		rockchip,grf = <&grf>;
		/**
		 * this is bitmap
		 * 0x1: (1 << 0) - audm0 enabled
		 * 0x2: (1 << 1) - audm1 enabled
		 * 0x3:          - audm0 + audm1 enabled
		 * others        - invalid
		 */
		rockchip,dsm-audm-en = <0x1>;
		pinctrl-names = "audm0-iodown", "audm0-pins",
				"audm1-iodown", "audm1-pins",
				"audm0m1-iodown", "audm0m1-pins";
		pinctrl-0 = <&dsm_audm0_iodown_pins>;
		pinctrl-1 = <&dsm_audm0_pins>;
		pinctrl-2 = <&dsm_audm1_iodown_pins>;
		pinctrl-3 = <&dsm_audm1_pins>;
		pinctrl-4 = <&dsm_audm0_iodown_pins>, <&dsm_audm1_iodown_pins>;
		pinctrl-5 = <&dsm_audm0_pins>, <&dsm_audm1_pins>;
		#sound-dai-cells = <0>;
		status = "disabled";
	};

	ioc_grf: syscon@ff4d8000 {
		compatible = "rockchip,rk3506-ioc-grf", "syscon";
		reg = <0xff4d8000 0x8000>;
	};

	uart5: serial@ff4e0000 {
		compatible = "rockchip,rk3506-uart", "snps,dw-apb-uart";
		reg = <0xff4e0000 0x100>;
		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <4>;
		dmas = <&dmac1 14 0x0 0x0 0x0 0x0>, <&dmac1 15 0x0 0x0 0x0 0x0>;
		clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
		clock-names = "baudclk", "apb_pclk";
		pinctrl-names = "default";
		pinctrl-0 = <&uart5m0_xfer_pins &uart5m0_ctsn_pins &uart5m0_rtsn_pins>;
		status = "disabled";
	};

	saradc: adc@ff4e8000 {
		compatible = "rockchip,rk3506-saradc", "rockchip,rk3562-saradc";
		reg = <0xff4e8000 0x8000>;
		interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
		#io-channel-cells = <1>;
		clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
		clock-names = "saradc", "apb_pclk";
		resets = <&cru SRST_P_SARADC>;
		reset-names = "saradc-apb";
		status = "disabled";
	};

	otp: otp@ff4f0000 {
		compatible = "rockchip,rk3506-otp";
		reg = <0xff4f0000 0x4000>;
		#address-cells = <1>;
		#size-cells = <1>;
		clocks = <&cru CLK_USER_OTPC_NS>, <&cru CLK_SBPI_OTPC_NS>,
			 <&cru PCLK_OTPC_NS>;
		clock-names = "usr", "sbpi", "apb";
		resets = <&cru SRST_USER_OTPC_NS>, <&cru SRST_SBPI_OTPC_NS>,
			 <&cru SRST_P_OTPC_NS>;
		reset-names = "usr", "sbpi", "apb";

		/* Data cells */
		cpu_code: cpu-code@2 {
			reg = <0x02 0x2>;
		};
		otp_cpu_version: cpu-version@5 {
			reg = <0x05 0x1>;
			bits = <3 3>;
		};
		specification_serial_number: specification-serial-number@8 {
			reg = <0x08 0x1>;
			bits = <0 5>;
		};
		otp_id: id@a {
			reg = <0x0a 0x10>;
		};
		cpu_leakage: cpu-leakage@1e {
			reg = <0x1e 0x1>;
		};
		log_leakage: log-leakage@1f {
			reg = <0x1f 0x1>;
		};
		cpu_tsadc_trim_l: cpu-tsadc-trim-l@20 {
			reg = <0x20 0x1>;
		};
		cpu_tsadc_trim_h: cpu-tsadc-trim-h@21 {
			reg = <0x21 0x1>;
			bits = <0 2>;
		};
		cpu_opp_info: cpu-opp-info@24 {
			reg = <0x24 0x6>;
		};
		cpu_pvtpll: cpu-pvtpll@30 {
			reg = <0x30 0x2>;
		};
		cpu_mbist_vmin: mbist-vmin@33 {
			reg = <0x33 0x1>;
			bits = <0 4>;
		};
	};

	audio_codec: audio-codec@ff4f8000 {
		compatible = "rockchip,rk3506-codec";
		reg = <0xff4f8000 0x1000>;
		#sound-dai-cells = <0>;
		clocks = <&cru PCLK_AUDIO_ADC>, <&cru MCLK_AUDIO_ADC>;
		clock-names = "pclk", "mclk";
		resets = <&cru SRST_M_AUDIO_ADC>;
		reset-names = "rst";
		status = "disabled";
	};

	gic: interrupt-controller@ff581000 {
		compatible = "arm,gic-400";
		reg = <0xff581000 0x1000>,
		      <0xff582000 0x2000>,
		      <0xff584000 0x2000>,
		      <0xff586000 0x2000>;
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
		#interrupt-cells = <3>;
		interrupt-controller;
		#address-cells = <0>;
	};

	rga2: rga@ff610000 {
		compatible = "rockchip,rga2";
		reg = <0xff610000 0x1000>;
		interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "rga2_irq";
		clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_CORE_RGA>;
		clock-names = "aclk_rga", "hclk_rga", "clk_rga";
		status = "disabled";
	};

	tsadc: tsadc@ff650000 {
		compatible = "rockchip,rk3506-tsadc";
		reg = <0xff650000 0x400>;
		interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>, <&cru CLK_TSADC_TSEN>;
		clock-names = "tsadc", "apb_pclk", "tsen";
		assigned-clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>;
		assigned-clock-rates = <1000000>, <12000000>;
		resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>;
		reset-names = "tsadc", "tsadc-apb";
		#thermal-sensor-cells = <1>;
		rockchip,grf = <&grf>;
		rockchip,hw-tshut-temp = <120000>;
		rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
		rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
		nvmem-cells = <&cpu_tsadc_trim_l>, <&cpu_tsadc_trim_h>;
		nvmem-cell-names = "trim_l", "trim_h";
		status = "disabled";
	};

	ioc1: syscon@ff660000 {
		compatible = "rockchip,rk3506-ioc1", "syscon";
		reg = <0xff660000 0x10000>;
	};

	crypto: crypto@ff700000 {
		compatible = "rockchip,crypto-v4";
		reg = <0xff700000 0x2000>;
		interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_CRYPTO_NS>, <&cru HCLK_CRYPTO_NS>,
			 <&cru CLK_CORE_CRYPTO_NS>, <&cru CLK_PKA_CRYPTO_NS>;
		clock-names = "aclk", "hclk", "core", "pka";
		resets = <&cru SRST_H_CRYPTO>;
		reset-names = "crypto-rst";
		status = "disabled";
	};

	rng: rng@ff710000 {
		compatible = "rockchip,rkrng";
		reg = <0xff710000 0x200>;
		interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_RNG>;
		clock-names = "hclk_trng";
		resets = <&cru SRST_H_RNG>;
		reset-names = "reset";
		status = "disabled";
	};

	usb20_otg0: usb@ff740000 {
		compatible = "rockchip,rk3506-usb", "rockchip,rk3066-usb",
			     "snps,dwc2";
		reg = <0xff740000 0x40000>;
		interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_USBOTG0>, <&cru HCLK_USBOTG0_PMU>,
			 <&cru CLK_USBOTG0_ADP>;
		clock-names = "otg", "pmu", "adp";
		dr_mode = "otg";
		phys = <&u2phy_otg0>;
		phy-names = "usb2-phy";
		g-np-tx-fifo-size = <16>;
		g-rx-fifo-size = <280>;
		g-tx-fifo-size = <256 128 128 64 32 16>;
		status = "disabled";
	};

	usb20_otg1: usb@ff780000 {
		compatible = "rockchip,rk3506-usb", "rockchip,rk3066-usb",
			     "snps,dwc2";
		reg = <0xff780000 0x40000>;
		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_USBOTG1>, <&cru HCLK_USBOTG1_PMU>,
			 <&cru CLK_USBOTG1_ADP>;
		clock-names = "otg", "pmu", "adp";
		dr_mode = "otg";
		phys = <&u2phy_otg1>;
		phy-names = "usb2-phy";
		g-np-tx-fifo-size = <16>;
		g-rx-fifo-size = <280>;
		g-tx-fifo-size = <256 128 128 64 32 16>;
		status = "disabled";
	};

	arm-debug@ff810000 {
		compatible = "rockchip,debug";
		reg = <0xff810000 0x1000>,
		      <0xff812000 0x1000>,
		      <0xff814000 0x1000>;
	};

	flexbus: flexbus@ff880000 {
		compatible = "rockchip,rk3506-flexbus";
		reg = <0xff880000 0x200>;
		interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru CLK_FLEXBUS_TX>, <&cru CLK_FLEXBUS_RX>,
			 <&cru ACLK_FLEXBUS>, <&cru HCLK_FLEXBUS>;
		clock-names = "tx_clk_flexbus", "rx_clk_flexbus",
			      "aclk_flexbus", "hclk_flexbus";
		rockchip,grf = <&grf>;
		status = "disabled";

		flexbus_adc: adc {
			compatible = "rockchip,flexbus-adc";
			#io-channel-cells = <0>;
			clocks = <&cru CLK_REF_OUT1>;
			clock-names = "ref_clk";	/* ref_clk is only used for slave-mode */
			rockchip,slave-mode;
			rockchip,free-sclk;
			rockchip,auto-pad;
			rockchip,dfs = <16>;
			status = "disabled";
		};

		flexbus_cif: cif {
			compatible = "rockchip,flexbus-cif-rk3506";
			status = "disabled";
		};

		flexbus_dac: dac {
			compatible = "rockchip,flexbus-dac";
			#io-channel-cells = <0>;
			rockchip,free-sclk;
			rockchip,dfs = <16>;
			status = "disabled";
		};

		flexbus_fspi: fspi {
			compatible = "rockchip,flexbus-fspi";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		flexbus_spi: spi {
			compatible = "rockchip,flexbus-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};
	};

	grf_pmu: syscon@ff910000 {
		compatible = "rockchip,rk3506-grf-pmu", "syscon", "simple-mfd";
		reg = <0xff910000 0x4000>;

		reboot_mode: reboot-mode {
			compatible = "syscon-reboot-mode";
			offset = <0x200>;
			mode-bootloader = <BOOT_BL_DOWNLOAD>;
			mode-charge = <BOOT_CHARGING>;
			mode-fastboot = <BOOT_FASTBOOT>;
			mode-loader = <BOOT_BL_DOWNLOAD>;
			mode-normal = <BOOT_NORMAL>;
			mode-recovery = <BOOT_RECOVERY>;
			mode-ums = <BOOT_UMS>;
			mode-panic = <BOOT_PANIC>;
			mode-watchdog = <BOOT_WATCHDOG>;
		};
	};

	pwm0_4ch_0: pwm@ff930000 {
		compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm";
		reg = <0xff930000 0x200>;
		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>, <&cru CLK_OSC_PWM0>;
		clock-names = "pwm", "pclk", "osc";
		#pwm-cells = <3>;
		status = "disabled";
	};

	pwm0_4ch_1: pwm@ff931000 {
		compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm";
		reg = <0xff931000 0x200>;
		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>, <&cru CLK_OSC_PWM0>;
		clock-names = "pwm", "pclk", "osc";
		#pwm-cells = <3>;
		status = "disabled";
	};

	pwm0_4ch_2: pwm@ff932000 {
		compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm";
		reg = <0xff932000 0x200>;
		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>, <&cru CLK_OSC_PWM0>;
		clock-names = "pwm", "pclk", "osc";
		#pwm-cells = <3>;
		status = "disabled";
	};

	pwm0_4ch_3: pwm@ff933000 {
		compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm";
		reg = <0xff933000 0x200>;
		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>, <&cru CLK_OSC_PWM0>;
		clock-names = "pwm", "pclk", "osc";
		#pwm-cells = <3>;
		status = "disabled";
	};

	ioc_pmu: syscon@ff950000 {
		compatible = "rockchip,rk3506-ioc-pmu", "syscon";
		reg = <0xff950000 0x10000>;
	};

	cru: clock-controller@ff9a0000 {
		compatible = "rockchip,rk3506-cru";
		reg = <0xff9a0000 0x20000>;
		rockchip,grf = <&grf>;
		#clock-cells = <1>;
		#reset-cells = <1>;

		assigned-clocks =
			<&cru CLK_FRAC_UART_MATRIX0>,
			<&cru CLK_FRAC_UART_MATRIX1>;
		assigned-clock-rates =
			<96000000>,
			<128000000>;
	};

	pinctrl: pinctrl {
		compatible = "rockchip,rk3506-pinctrl";
		rockchip,grf = <&ioc_grf>;
		rockchip,ioc1 = <&ioc1>;
		rockchip,pmu = <&ioc_pmu>;
		rockchip,rmio = <&grf_pmu>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		gpio0: gpio@ff940000 {
			compatible = "rockchip,gpio-bank";
			reg = <0xff940000 0x200>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;

			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl 0 0 32>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio1: gpio@ff870000 {
			compatible = "rockchip,gpio-bank";
			reg = <0xff870000 0x200>;
			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;

			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl 0 32 32>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio@ff1c0000 {
			compatible = "rockchip,gpio-bank";
			reg = <0xff1c0000 0x200>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;

			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl 0 64 32>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio@ff1d0000 {
			compatible = "rockchip,gpio-bank";
			reg = <0xff1d0000 0x200>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;

			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl 0 96 32>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio4: gpio@ff1e0000 {
			compatible = "rockchip,gpio-bank";
			reg = <0xff1e0000 0x200>;
			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;

			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl 0 128 32>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};
};

#include "rk3506-pinctrl.dtsi"
#include "rk3506-pinctrl-rmio.dtsi"