// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3288-cru.h>
#include <dt-bindings/power/rk3288-power.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
#include <dt-bindings/suspend/rockchip-rk3288.h>

/ {
	#address-cells = <2>;
	#size-cells = <2>;

	compatible = "rockchip,rk3288";

	interrupt-parent = <&gic>;

	aliases {
		dsi0 = &dsi0;
		dsi1 = &dsi1;
		ethernet0 = &gmac;
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		gpio2 = &gpio2;
		gpio3 = &gpio3;
		gpio4 = &gpio4;
		gpio5 = &gpio5;
		gpio6 = &gpio6;
		gpio7 = &gpio7;
		gpio8 = &gpio8;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		i2c4 = &i2c4;
		i2c5 = &i2c5;
		mshc0 = &emmc;
		mshc1 = &sdmmc;
		mshc2 = &sdio0;
		mshc3 = &sdio1;
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
		serial4 = &uart4;
		spi0 = &spi0;
		spi1 = &spi1;
		spi2 = &spi2;
	};

	arm-pmu {
		compatible = "arm,cortex-a12-pmu";
		interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "rockchip,rk3066-smp";
		rockchip,pmu = <&pmu>;

		cpu0: cpu@500 {
			device_type = "cpu";
			compatible = "arm,cortex-a12";
			reg = <0x500>;
			enable-method = "psci";
			resets = <&cru SRST_CORE0>;
			operating-points-v2 = <&cpu_opp_table>;
			#cooling-cells = <2>; /* min followed by max */
			clock-latency = <40000>;
			clocks = <&cru ARMCLK>;
			dynamic-power-coefficient = <370>;
		};
		cpu1: cpu@501 {
			device_type = "cpu";
			compatible = "arm,cortex-a12";
			reg = <0x501>;
			enable-method = "psci";
			resets = <&cru SRST_CORE1>;
			operating-points-v2 = <&cpu_opp_table>;
			#cooling-cells = <2>; /* min followed by max */
			clock-latency = <40000>;
			clocks = <&cru ARMCLK>;
			dynamic-power-coefficient = <370>;
		};
		cpu2: cpu@502 {
			device_type = "cpu";
			compatible = "arm,cortex-a12";
			reg = <0x502>;
			enable-method = "psci";
			resets = <&cru SRST_CORE2>;
			operating-points-v2 = <&cpu_opp_table>;
			#cooling-cells = <2>; /* min followed by max */
			clock-latency = <40000>;
			clocks = <&cru ARMCLK>;
			dynamic-power-coefficient = <370>;
		};
		cpu3: cpu@503 {
			device_type = "cpu";
			compatible = "arm,cortex-a12";
			reg = <0x503>;
			enable-method = "psci";
			resets = <&cru SRST_CORE3>;
			operating-points-v2 = <&cpu_opp_table>;
			#cooling-cells = <2>; /* min followed by max */
			clock-latency = <40000>;
			clocks = <&cru ARMCLK>;
			dynamic-power-coefficient = <370>;
		};
	};

	cpu_opp_table: opp-table-0 {
		compatible = "operating-points-v2";
		opp-shared;

		clocks = <&cru PLL_APLL>;
		rockchip,avs-scale = <17>;
		rockchip,max-volt = <1350000>;
		nvmem-cells = <&cpu_leakage>, <&special_function>,
			      <&performance>, <&process_version>,
			      <&performance_w>, <&package_info>;
		nvmem-cell-names = "leakage", "special",
				   "performance", "process",
				   "performance-w", "package";
		rockchip,bin-scaling-sel = <
			0               17
			1               25
			2               27
			3               31
		>;
		rockchip,pvtm-voltage-sel = <
			0        15300   0
			15301    16000   1
			16001    17000   2
			17001    99999   3
		>;
		rockchip,pvtm-freq = <408000>;
		rockchip,pvtm-volt = <1000000>;
		rockchip,pvtm-ch = <0 0>;
		rockchip,pvtm-sample-time = <1000>;
		rockchip,pvtm-number = <10>;
		rockchip,pvtm-error = <1000>;
		rockchip,pvtm-ref-temp = <35>;
		rockchip,pvtm-temp-prop = <(-18) (-18)>;
		rockchip,thermal-zone = "cpu-thermal";

		opp-126000000 {
			opp-hz = /bits/ 64 <126000000>;
			opp-microvolt = <950000 950000 1350000>;
			opp-microvolt-L0 = <950000 950000 1350000>;
			opp-microvolt-L1 = <950000 950000 1350000>;
			opp-microvolt-L2 = <950000 950000 1350000>;
			opp-microvolt-L3 = <950000 950000 1350000>;
			clock-latency-ns = <40000>;
		};
		opp-216000000 {
			opp-hz = /bits/ 64 <216000000>;
			opp-microvolt = <950000 950000 1350000>;
			opp-microvolt-L0 = <950000 950000 1350000>;
			opp-microvolt-L1 = <950000 950000 1350000>;
			opp-microvolt-L2 = <950000 950000 1350000>;
			opp-microvolt-L3 = <950000 950000 1350000>;
			clock-latency-ns = <40000>;
		};
		opp-408000000 {
			opp-hz = /bits/ 64 <408000000>;
			opp-microvolt = <975000 975000 1350000>;
			opp-microvolt-L0 = <975000 975000 1350000>;
			opp-microvolt-L1 = <950000 950000 1350000>;
			opp-microvolt-L2 = <950000 950000 1350000>;
			opp-microvolt-L3 = <950000 950000 1350000>;
			clock-latency-ns = <40000>;
		};
		opp-600000000 {
			opp-hz = /bits/ 64 <600000000>;
			opp-microvolt = <975000 975000 1350000>;
			opp-microvolt-L0 = <975000 975000 1350000>;
			opp-microvolt-L1 = <950000 950000 1350000>;
			opp-microvolt-L2 = <950000 950000 1350000>;
			opp-microvolt-L3 = <950000 950000 1350000>;
			clock-latency-ns = <40000>;
		};
		opp-696000000 {
			opp-hz = /bits/ 64 <696000000>;
			opp-microvolt = <975000 975000 1350000>;
			opp-microvolt-L0 = <975000 975000 1350000>;
			opp-microvolt-L1 = <950000 950000 1350000>;
			opp-microvolt-L2 = <950000 950000 1350000>;
			opp-microvolt-L3 = <950000 950000 1350000>;
			clock-latency-ns = <40000>;
		};
		opp-816000000 {
			opp-hz = /bits/ 64 <816000000>;
			opp-microvolt = <1075000 1075000 1350000>;
			opp-microvolt-L0 = <1075000 1075000 1350000>;
			opp-microvolt-L1 = <1050000 1050000 1350000>;
			opp-microvolt-L2 = <1000000 1000000 1350000>;
			opp-microvolt-L3 = <950000 950000 1350000>;
			clock-latency-ns = <40000>;
			opp-suspend;
		};
		opp-1008000000 {
			opp-hz = /bits/ 64 <1008000000>;
			opp-microvolt = <1150000 1150000 1350000>;
			opp-microvolt-L0 = <1150000 1150000 1350000>;
			opp-microvolt-L1 = <1100000 1100000 1350000>;
			opp-microvolt-L2 = <1050000 1050000 1350000>;
			opp-microvolt-L3 = <1000000 1000000 1350000>;
			clock-latency-ns = <40000>;
		};
		opp-1200000000 {
			opp-hz = /bits/ 64 <1200000000>;
			opp-microvolt = <1200000 1200000 1350000>;
			opp-microvolt-L0 = <1200000 1200000 1350000>;
			opp-microvolt-L1 = <1150000 1150000 1350000>;
			opp-microvolt-L2 = <1100000 1100000 1350000>;
			opp-microvolt-L3 = <1050000 1050000 1350000>;
			clock-latency-ns = <40000>;
		};
		opp-1416000000 {
			opp-hz = /bits/ 64 <1416000000>;
			opp-microvolt = <1300000 1300000 1350000>;
			opp-microvolt-L0 = <1300000 1300000 1350000>;
			opp-microvolt-L1 = <1250000 1250000 1350000>;
			opp-microvolt-L2 = <1200000 1200000 1350000>;
			opp-microvolt-L3 = <1150000 1150000 1350000>;
			clock-latency-ns = <40000>;
		};
		opp-1512000000 {
			opp-hz = /bits/ 64 <1512000000>;
			opp-microvolt = <1350000 1350000 1350000>;
			opp-microvolt-L0 = <1350000 1350000 1350000>;
			opp-microvolt-L1 = <1300000 1300000 1350000>;
			opp-microvolt-L2 = <1250000 1250000 1350000>;
			opp-microvolt-L3 = <1200000 1200000 1350000>;
			clock-latency-ns = <40000>;
		};
		opp-1608000000 {
			opp-hz = /bits/ 64 <1608000000>;
			opp-microvolt = <1350000 1350000 1350000>;
			opp-microvolt-L0 = <1350000 1350000 1350000>;
			opp-microvolt-L1 = <1350000 1350000 1350000>;
			opp-microvolt-L2 = <1300000 1300000 1350000>;
			opp-microvolt-L3 = <1250000 1250000 1350000>;
			clock-latency-ns = <40000>;
		};
	};

	firmware {
		optee: optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/*
		 * The rk3288 cannot use the memory area above 0xfe000000
		 * for dma operations for some reason. While there is
		 * probably a better solution available somewhere, we
		 * haven't found it yet and while devices with 2GB of ram
		 * are not affected, this issue prevents 4GB from booting.
		 * So to make these devices at least bootable, block
		 * this area for the time being until the real solution
		 * is found.
		 */
		dma-unusable@fe000000 {
			reg = <0x0 0xfe000000 0x0 0x1000000>;
		};
	};

	xin24m: oscillator {
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		clock-output-names = "xin24m";
		#clock-cells = <0>;
	};

	timer {
		compatible = "arm,armv7-timer";
		arm,cpu-registers-not-fw-configured;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		clock-frequency = <24000000>;
		arm,no-tick-in-suspend;
	};

	display-subsystem {
		compatible = "rockchip,display-subsystem";
		ports = <&vopl_out>, <&vopb_out>;
	};

	sdmmc: mmc@ff0c0000 {
		compatible = "rockchip,rk3288-dw-mshc";
		max-frequency = <150000000>;
		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
		fifo-depth = <0x100>;
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
		reg = <0x0 0xff0c0000 0x0 0x4000>;
		resets = <&cru SRST_MMC0>;
		reset-names = "reset";
		status = "disabled";
	};

	sdio0: mmc@ff0d0000 {
		compatible = "rockchip,rk3288-dw-mshc";
		max-frequency = <150000000>;
		clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
			 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
		fifo-depth = <0x100>;
		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
		reg = <0x0 0xff0d0000 0x0 0x4000>;
		resets = <&cru SRST_SDIO0>;
		reset-names = "reset";
		status = "disabled";
	};

	sdio1: mmc@ff0e0000 {
		compatible = "rockchip,rk3288-dw-mshc";
		max-frequency = <150000000>;
		clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
			 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
		fifo-depth = <0x100>;
		interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
		reg = <0x0 0xff0e0000 0x0 0x4000>;
		resets = <&cru SRST_SDIO1>;
		reset-names = "reset";
		status = "disabled";
	};

	emmc: mmc@ff0f0000 {
		compatible = "rockchip,rk3288-dw-mshc";
		max-frequency = <150000000>;
		clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
			 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
		fifo-depth = <0x100>;
		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
		reg = <0x0 0xff0f0000 0x0 0x4000>;
		resets = <&cru SRST_EMMC>;
		reset-names = "reset";
		status = "disabled";
	};

	saradc: saradc@ff100000 {
		compatible = "rockchip,saradc";
		reg = <0x0 0xff100000 0x0 0x100>;
		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
		#io-channel-cells = <1>;
		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
		clock-names = "saradc", "apb_pclk";
		resets = <&cru SRST_SARADC>;
		reset-names = "saradc-apb";
		status = "disabled";
	};

	spi0: spi@ff110000 {
		compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
		clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
		clock-names = "spiclk", "apb_pclk";
		dmas = <&dmac_peri 11>, <&dmac_peri 12>;
		dma-names = "tx", "rx";
		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
		reg = <0x0 0xff110000 0x0 0x1000>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	spi1: spi@ff120000 {
		compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
		clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
		clock-names = "spiclk", "apb_pclk";
		dmas = <&dmac_peri 13>, <&dmac_peri 14>;
		dma-names = "tx", "rx";
		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
		reg = <0x0 0xff120000 0x0 0x1000>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	spi2: spi@ff130000 {
		compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
		clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
		clock-names = "spiclk", "apb_pclk";
		dmas = <&dmac_peri 15>, <&dmac_peri 16>;
		dma-names = "tx", "rx";
		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
		reg = <0x0 0xff130000 0x0 0x1000>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c0: i2c@ff650000 {
		compatible = "rockchip,rk3288-i2c";
		reg = <0x0 0xff650000 0x0 0x1000>;
		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "i2c";
		clocks = <&cru PCLK_I2C0>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c0_xfer>;
		status = "disabled";
	};

	i2c1: i2c@ff140000 {
		compatible = "rockchip,rk3288-i2c";
		reg = <0x0 0xff140000 0x0 0x1000>;
		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "i2c";
		clocks = <&cru PCLK_I2C1>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c1_xfer>;
		status = "disabled";
	};

	i2c3: i2c@ff150000 {
		compatible = "rockchip,rk3288-i2c";
		reg = <0x0 0xff150000 0x0 0x1000>;
		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "i2c";
		clocks = <&cru PCLK_I2C3>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c3_xfer>;
		status = "disabled";
	};

	i2c4: i2c@ff160000 {
		compatible = "rockchip,rk3288-i2c";
		reg = <0x0 0xff160000 0x0 0x1000>;
		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "i2c";
		clocks = <&cru PCLK_I2C4>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c4_xfer>;
		status = "disabled";
	};

	i2c5: i2c@ff170000 {
		compatible = "rockchip,rk3288-i2c";
		reg = <0x0 0xff170000 0x0 0x1000>;
		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "i2c";
		clocks = <&cru PCLK_I2C5>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c5_xfer>;
		status = "disabled";
	};

	uart0: serial@ff180000 {
		compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
		reg = <0x0 0xff180000 0x0 0x100>;
		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <4>;
		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
		clock-names = "baudclk", "apb_pclk";
		dmas = <&dmac_peri 1>, <&dmac_peri 2>;
		dma-names = "tx", "rx";
		pinctrl-names = "default";
		pinctrl-0 = <&uart0_xfer>;
		status = "disabled";
	};

	uart1: serial@ff190000 {
		compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
		reg = <0x0 0xff190000 0x0 0x100>;
		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <4>;
		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
		clock-names = "baudclk", "apb_pclk";
		dmas = <&dmac_peri 3>, <&dmac_peri 4>;
		dma-names = "tx", "rx";
		pinctrl-names = "default";
		pinctrl-0 = <&uart1_xfer>;
		status = "disabled";
	};

	uart2: serial@ff690000 {
		compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
		reg = <0x0 0xff690000 0x0 0x100>;
		interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <4>;
		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
		clock-names = "baudclk", "apb_pclk";
		pinctrl-names = "default";
		pinctrl-0 = <&uart2_xfer>;
		status = "disabled";
	};

	uart3: serial@ff1b0000 {
		compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
		reg = <0x0 0xff1b0000 0x0 0x100>;
		interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <4>;
		clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
		clock-names = "baudclk", "apb_pclk";
		dmas = <&dmac_peri 7>, <&dmac_peri 8>;
		dma-names = "tx", "rx";
		pinctrl-names = "default";
		pinctrl-0 = <&uart3_xfer>;
		status = "disabled";
	};

	uart4: serial@ff1c0000 {
		compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
		reg = <0x0 0xff1c0000 0x0 0x100>;
		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <4>;
		clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
		clock-names = "baudclk", "apb_pclk";
		dmas = <&dmac_peri 9>, <&dmac_peri 10>;
		dma-names = "tx", "rx";
		pinctrl-names = "default";
		pinctrl-0 = <&uart4_xfer>;
		status = "disabled";
	};

	dmac_peri: dma-controller@ff250000 {
		compatible = "arm,pl330", "arm,primecell";
		reg = <0x0 0xff250000 0x0 0x4000>;
		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
		#dma-cells = <1>;
		arm,pl330-broken-no-flushp;
		arm,pl330-periph-burst;
		clocks = <&cru ACLK_DMAC2>;
		clock-names = "apb_pclk";
	};

	thermal-zones {
		reserve_thermal: reserve-thermal {
			polling-delay-passive = <1000>; /* milliseconds */
			polling-delay = <5000>; /* milliseconds */

			thermal-sensors = <&tsadc 0>;
		};

		cpu_thermal: cpu-thermal {
			polling-delay-passive = <100>; /* milliseconds */
			polling-delay = <5000>; /* milliseconds */

			thermal-sensors = <&tsadc 1>;

			trips {
				cpu_alert0: cpu_alert0 {
					temperature = <70000>; /* millicelsius */
					hysteresis = <2000>; /* millicelsius */
					type = "passive";
				};
				cpu_alert1: cpu_alert1 {
					temperature = <75000>; /* millicelsius */
					hysteresis = <2000>; /* millicelsius */
					type = "passive";
				};
				cpu_crit: cpu_crit {
					temperature = <90000>; /* millicelsius */
					hysteresis = <2000>; /* millicelsius */
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu_alert0>;
					cooling-device =
						<&cpu0 THERMAL_NO_LIMIT 6>,
						<&cpu1 THERMAL_NO_LIMIT 6>,
						<&cpu2 THERMAL_NO_LIMIT 6>,
						<&cpu3 THERMAL_NO_LIMIT 6>;
				};
				map1 {
					trip = <&cpu_alert1>;
					cooling-device =
						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};

		gpu_thermal: gpu-thermal {
			polling-delay-passive = <100>; /* milliseconds */
			polling-delay = <5000>; /* milliseconds */

			thermal-sensors = <&tsadc 2>;

			trips {
				gpu_alert0: gpu_alert0 {
					temperature = <70000>; /* millicelsius */
					hysteresis = <2000>; /* millicelsius */
					type = "passive";
				};
				gpu_crit: gpu_crit {
					temperature = <90000>; /* millicelsius */
					hysteresis = <2000>; /* millicelsius */
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&gpu_alert0>;
					cooling-device =
						<&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};
	};

	tsadc: tsadc@ff280000 {
		compatible = "rockchip,rk3288-tsadc";
		reg = <0x0 0xff280000 0x0 0x100>;
		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
		clock-names = "tsadc", "apb_pclk";
		assigned-clocks = <&cru SCLK_TSADC>;
		assigned-clock-rates = <5000>;
		resets = <&cru SRST_TSADC>;
		reset-names = "tsadc-apb";
		pinctrl-names = "gpio", "otpout";
		pinctrl-0 = <&otp_pin>;
		pinctrl-1 = <&otp_out>;
		#thermal-sensor-cells = <1>;
		rockchip,grf = <&grf>;
		rockchip,hw-tshut-temp = <95000>;
		status = "disabled";
	};

	gmac: ethernet@ff290000 {
		compatible = "rockchip,rk3288-gmac";
		reg = <0x0 0xff290000 0x0 0x10000>;
		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "macirq", "eth_wake_irq";
		rockchip,grf = <&grf>;
		clocks = <&cru SCLK_MAC>,
			<&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
			<&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
			<&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
		clock-names = "stmmaceth",
			"mac_clk_rx", "mac_clk_tx",
			"clk_mac_ref", "clk_mac_refout",
			"aclk_mac", "pclk_mac";
		resets = <&cru SRST_MAC>;
		reset-names = "stmmaceth";
		status = "disabled";
	};

	usb_host0_ehci: usb@ff500000 {
		compatible = "generic-ehci";
		reg = <0x0 0xff500000 0x0 0x100>;
		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_USBHOST0>, <&usbphy1>;
		clock-names = "usbhost", "utmi";
		phys = <&usbphy1>;
		phy-names = "usb";
		status = "disabled";
	};

	/* NOTE: doesn't work on RK3288, but was fixed on RK3288W */
	usb_host0_ohci: usb@ff520000 {
		compatible = "generic-ohci";
		reg = <0x0 0xff520000 0x0 0x100>;
		interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_USBHOST0>, <&usbphy1>;
		clock-names = "usbhost", "utmi";
		phys = <&usbphy1>;
		phy-names = "usb";
		status = "disabled";
	};

	usb_host1: usb@ff540000 {
		compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
				"snps,dwc2";
		reg = <0x0 0xff540000 0x0 0x40000>;
		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_USBHOST1>;
		clock-names = "otg";
		dr_mode = "host";
		phys = <&usbphy2>;
		phy-names = "usb2-phy";
		snps,reset-phy-on-wake;
		status = "disabled";
	};

	usb_otg: usb@ff580000 {
		compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
				"snps,dwc2";
		reg = <0x0 0xff580000 0x0 0x40000>;
		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_OTG0>;
		clock-names = "otg";
		dr_mode = "otg";
		g-np-tx-fifo-size = <16>;
		g-rx-fifo-size = <280>;
		g-tx-fifo-size = <256 128 128 64 32 16>;
		phys = <&usbphy0>;
		phy-names = "usb2-phy";
		status = "disabled";
	};

	usb_hsic: usb@ff5c0000 {
		compatible = "generic-ehci";
		reg = <0x0 0xff5c0000 0x0 0x100>;
		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_HSIC>;
		status = "disabled";
	};

	dmac_bus_ns: dma-controller@ff600000 {
		compatible = "arm,pl330", "arm,primecell";
		reg = <0x0 0xff600000 0x0 0x4000>;
		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
		#dma-cells = <1>;
		arm,pl330-broken-no-flushp;
		arm,pl330-periph-burst;
		clocks = <&cru ACLK_DMAC1>;
		clock-names = "apb_pclk";
		status = "disabled";
	};

	i2c2: i2c@ff660000 {
		compatible = "rockchip,rk3288-i2c";
		reg = <0x0 0xff660000 0x0 0x1000>;
		interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "i2c";
		clocks = <&cru PCLK_I2C2>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c2_xfer>;
		status = "disabled";
	};

	pwm0: pwm@ff680000 {
		compatible = "rockchip,rk3288-pwm";
		reg = <0x0 0xff680000 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm0_pin>;
		clocks = <&cru PCLK_RKPWM>;
		status = "disabled";
	};

	pwm1: pwm@ff680010 {
		compatible = "rockchip,rk3288-pwm";
		reg = <0x0 0xff680010 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm1_pin>;
		clocks = <&cru PCLK_RKPWM>;
		status = "disabled";
	};

	pwm2: pwm@ff680020 {
		compatible = "rockchip,rk3288-pwm";
		reg = <0x0 0xff680020 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm2_pin>;
		clocks = <&cru PCLK_RKPWM>;
		status = "disabled";
	};

	pwm3: pwm@ff680030 {
		compatible = "rockchip,rk3288-pwm";
		reg = <0x0 0xff680030 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm3_pin>;
		clocks = <&cru PCLK_RKPWM>;
		status = "disabled";
	};

	timer: timer@ff6b0000 {
		compatible = "rockchip,rk3288-timer";
		reg = <0x0 0xff6b0000 0x0 0x20>;
		interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru PCLK_TIMER>, <&xin24m>;
		clock-names = "pclk", "timer";
	};

	bus_intmem: sram@ff700000 {
		compatible = "mmio-sram";
		reg = <0x0 0xff700000 0x0 0x18000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x0 0xff700000 0x18000>;
		smp-sram@0 {
			compatible = "rockchip,rk3066-smp-sram";
			reg = <0x00 0x10>;
		};
	};

	pmu_sram: sram@ff720000 {
		compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
		reg = <0x0 0xff720000 0x0 0x1000>;
	};

	pmu: power-management@ff730000 {
		compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
		reg = <0x0 0xff730000 0x0 0x100>;

		power: power-controller {
			compatible = "rockchip,rk3288-power-controller";
			#power-domain-cells = <1>;
			#address-cells = <1>;
			#size-cells = <0>;

			assigned-clocks = <&cru SCLK_EDP_24M>;
			assigned-clock-parents = <&xin24m>;

			/*
			 * Note: Although SCLK_* are the working clocks
			 * of device without including on the NOC, needed for
			 * synchronous reset.
			 *
			 * The clocks on the which NOC:
			 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
			 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
			 * ACLK_RGA is on ACLK_RGA_NIU.
			 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
			 *
			 * Which clock are device clocks:
			 *	clocks		devices
			 *	*_IEP		IEP:Image Enhancement Processor
			 *	*_ISP		ISP:Image Signal Processing
			 *	*_VIP		VIP:Video Input Processor
			 *	*_VOP*		VOP:Visual Output Processor
			 *	*_RGA		RGA
			 *	*_EDP*		EDP
			 *	*_LVDS_*	LVDS
			 *	*_HDMI		HDMI
			 *	*_MIPI_*	MIPI
			 */
			power-domain@RK3288_PD_VIO {
				reg = <RK3288_PD_VIO>;
				clocks = <&cru ACLK_IEP>,
					 <&cru ACLK_ISP>,
					 <&cru ACLK_RGA>,
					 <&cru ACLK_VIP>,
					 <&cru ACLK_VOP0>,
					 <&cru ACLK_VOP1>,
					 <&cru DCLK_VOP0>,
					 <&cru DCLK_VOP1>,
					 <&cru HCLK_IEP>,
					 <&cru HCLK_ISP>,
					 <&cru HCLK_RGA>,
					 <&cru HCLK_VIP>,
					 <&cru HCLK_VOP0>,
					 <&cru HCLK_VOP1>,
					 <&cru PCLK_EDP_CTRL>,
					 <&cru PCLK_HDMI_CTRL>,
					 <&cru PCLK_LVDS_PHY>,
					 <&cru PCLK_MIPI_CSI>,
					 <&cru PCLK_MIPI_DSI0>,
					 <&cru PCLK_MIPI_DSI1>,
					 <&cru SCLK_EDP_24M>,
					 <&cru SCLK_EDP>,
					 <&cru SCLK_HDMI_CEC>,
					 <&cru SCLK_ISP_JPE>,
					 <&cru SCLK_ISP>,
					 <&cru SCLK_RGA>;
				pm_qos = <&qos_vio0_iep>,
					 <&qos_vio1_vop>,
					 <&qos_vio1_isp_w0>,
					 <&qos_vio1_isp_w1>,
					 <&qos_vio0_vop>,
					 <&qos_vio0_vip>,
					 <&qos_vio2_rga_r>,
					 <&qos_vio2_rga_w>,
					 <&qos_vio1_isp_r>;
				#power-domain-cells = <0>;
			};

			/*
			 * Note: The following 3 are HEVC(H.265) clocks,
			 * and on the ACLK_HEVC_NIU (NOC).
			 */
			power-domain@RK3288_PD_HEVC {
				reg = <RK3288_PD_HEVC>;
				clocks = <&cru ACLK_HEVC>,
					 <&cru SCLK_HEVC_CABAC>,
					 <&cru SCLK_HEVC_CORE>;
				pm_qos = <&qos_hevc_r>,
					 <&qos_hevc_w>;
				#power-domain-cells = <0>;
			};

			/*
			 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
			 * (video endecoder & decoder) clocks that on the
			 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
			 */
			power-domain@RK3288_PD_VIDEO {
				reg = <RK3288_PD_VIDEO>;
				clocks = <&cru ACLK_VCODEC>,
					 <&cru HCLK_VCODEC>;
				pm_qos = <&qos_video>;
				#power-domain-cells = <0>;
			};

			/*
			 * Note: ACLK_GPU is the GPU clock,
			 * and on the ACLK_GPU_NIU (NOC).
			 */
			power-domain@RK3288_PD_GPU {
				reg = <RK3288_PD_GPU>;
				clocks = <&cru ACLK_GPU>;
				pm_qos = <&qos_gpu_r>,
					 <&qos_gpu_w>;
				#power-domain-cells = <0>;
			};
		};

		reboot-mode {
			compatible = "syscon-reboot-mode";
			offset = <0x94>;
			mode-normal = <BOOT_NORMAL>;
			mode-recovery = <BOOT_RECOVERY>;
			mode-bootloader = <BOOT_FASTBOOT>;
			mode-loader = <BOOT_BL_DOWNLOAD>;
			mode-ums = <BOOT_UMS>;
		};
	};

	sgrf: syscon@ff740000 {
		compatible = "rockchip,rk3288-sgrf", "syscon";
		reg = <0x0 0xff740000 0x0 0x1000>;
	};

	cru: clock-controller@ff760000 {
		compatible = "rockchip,rk3288-cru";
		reg = <0x0 0xff760000 0x0 0x1000>;
		clocks = <&xin24m>;
		clock-names = "xin24m";
		rockchip,grf = <&grf>;
		#clock-cells = <1>;
		#reset-cells = <1>;
		assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_NPLL>,
				  <&cru ACLK_CPU>, <&cru HCLK_CPU>,
				  <&cru PCLK_CPU>, <&cru ACLK_PERI>,
				  <&cru HCLK_PERI>, <&cru PCLK_PERI>,
				  <&cru ACLK_VIO0>, <&cru ACLK_VIO1>;
		assigned-clock-rates = <594000000>, <500000000>,
				       <300000000>, <150000000>,
				       <75000000>, <300000000>,
				       <150000000>, <75000000>,
				       <594000000>, <297000000>;
	};

	grf: syscon@ff770000 {
		compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
		reg = <0x0 0xff770000 0x0 0x1000>;

		edp_phy: edp-phy {
			compatible = "rockchip,rk3288-dp-phy";
			clocks = <&cru SCLK_EDP_24M>;
			clock-names = "24m";
			#phy-cells = <0>;
			status = "disabled";
		};

		io_domains: io-domains {
			compatible = "rockchip,rk3288-io-voltage-domain";
			status = "disabled";
		};

		mipi_phy_rx0: mipi-phy-rx0 {
			compatible = "rockchip,rk3288-mipi-dphy";
			clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_CSI>;
			clock-names = "dphy-ref", "pclk";
			status = "disabled";
		};

		lvds: lvds {
			compatible = "rockchip,rk3288-lvds";
			phys = <&video_phy>;
			phy-names = "phy";
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					#address-cells = <1>;
					#size-cells = <0>;

					lvds_in_vopb: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&vopb_out_lvds>;
					};

					lvds_in_vopl: endpoint@1 {
						reg = <1>;
						remote-endpoint = <&vopl_out_lvds>;
					};
				};
			};
		};

		rgb: rgb {
			compatible = "rockchip,rk3288-rgb";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&lcdc_rgb_pins>;
			pinctrl-1 = <&lcdc_sleep_pins>;
			phys = <&video_phy>;
			phy-names = "phy";
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					#address-cells = <1>;
					#size-cells = <0>;

					rgb_in_vopb: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&vopb_out_rgb>;
					};

					rgb_in_vopl: endpoint@1 {
						reg = <1>;
						remote-endpoint = <&vopl_out_rgb>;
					};
				};
			};
		};

		usbphy: usbphy {
			compatible = "rockchip,rk3288-usb-phy";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			usbphy0: usb-phy@320 {
				#phy-cells = <0>;
				reg = <0x320>;
				clocks = <&cru SCLK_OTGPHY0>;
				clock-names = "phyclk";
				#clock-cells = <0>;
				resets = <&cru SRST_USBOTG_PHY>;
				reset-names = "phy-reset";
				interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "otg-bvalid";
			};

			usbphy1: usb-phy@334 {
				#phy-cells = <0>;
				reg = <0x334>;
				clocks = <&cru SCLK_OTGPHY1>;
				clock-names = "phyclk";
				#clock-cells = <0>;
				resets = <&cru SRST_USBHOST0_PHY>;
				reset-names = "phy-reset";
			};

			usbphy2: usb-phy@348 {
				#phy-cells = <0>;
				reg = <0x348>;
				clocks = <&cru SCLK_OTGPHY2>;
				clock-names = "phyclk";
				#clock-cells = <0>;
				resets = <&cru SRST_USBHOST1_PHY>;
				reset-names = "phy-reset";
			};
		};

		pvtm: pvtm {
			compatible = "rockchip,rk3288-pvtm";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "okay";

			pvtm@0 {
				reg = <0>;
				clocks = <&cru SCLK_PVTM_CORE>;
				clock-names = "clk";
				resets = <&cru SRST_CORE_PVTM>;
				reset-names = "rst";
			};
			pvtm@1 {
				reg = <1>;
				clocks = <&cru SCLK_PVTM_GPU>;
				clock-names = "clk";
				resets = <&cru SRST_GPU_PVTM>;
				reset-names = "rst";
			};
		};
	};

	wdt: watchdog@ff800000 {
		compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
		reg = <0x0 0xff800000 0x0 0x100>;
		clocks = <&cru PCLK_WDT>;
		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	spdif_2ch: sound@ff880000 {
		compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
		reg = <0x0 0xff880000 0x0 0x10000>;
		#sound-dai-cells = <0>;
		clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>;
		clock-names = "mclk", "hclk";
		dmas = <&dmac_bus_s 2>;
		dma-names = "tx";
		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&spdif_tx>;
		rockchip,grf = <&grf>;
		status = "disabled";
	};

	i2s: i2s@ff890000 {
		compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
		reg = <0x0 0xff890000 0x0 0x10000>;
		#sound-dai-cells = <0>;
		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
		clock-names = "i2s_clk", "i2s_hclk";
		assigned-clocks = <&cru SCLK_I2S_SRC>;
		assigned-clock-parents = <&cru PLL_GPLL>;
		dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
		dma-names = "tx", "rx";
		pinctrl-names = "default";
		pinctrl-0 = <&i2s0_bus>;
		resets = <&cru SRST_I2S0>;
		reset-names = "reset-m";
		rockchip,playback-channels = <8>;
		rockchip,capture-channels = <2>;
		status = "disabled";
	};

	rng: rng@ff8a0000 {
		compatible = "rockchip,cryptov1-rng";
		reg = <0x0 0xff8a0000 0x0 0x4000>;
		clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO>;
		clock-names = "clk_crypto", "hclk_crypto";
		assigned-clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO>;
		assigned-clock-rates = <150000000>, <100000000>;
		status = "disabled";
	};

	crypto: crypto@ff8a0000 {
		compatible = "rockchip,rk3288-crypto";
		reg = <0x0 0xff8a0000 0x0 0x4000>;
		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
			 <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
		clock-names = "aclk", "hclk", "sclk", "apb_pclk";
		resets = <&cru SRST_CRYPTO>;
		reset-names = "crypto-rst";
		status = "disabled";
	};

	spdif: sound@ff8b0000 {
		compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
		reg = <0x0 0xff8b0000 0x0 0x10000>;
		#sound-dai-cells = <0>;
		clocks = <&cru SCLK_SPDIF8CH>, <&cru HCLK_SPDIF8CH>;
		clock-names = "mclk", "hclk";
		dmas = <&dmac_bus_s 3>;
		dma-names = "tx";
		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&spdif_tx>;
		rockchip,grf = <&grf>;
		status = "disabled";
	};

	iep: iep@ff90000 {
		compatible = "rockchip,iep";
		iommu_enabled = <1>;
		iommus = <&iep_mmu>;
		reg = <0x0 0xff900000 0x0 0x800>;
		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
		clock-names = "aclk_iep", "hclk_iep";
		power-domains = <&power RK3288_PD_VIO>;
		allocator = <1>;
		version = <1>;
		status = "disabled";
	};

	iep_mmu: iommu@ff900800 {
		compatible = "rockchip,iommu";
		reg = <0x0 0xff900800 0x0 0x40>;
		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
		clock-names = "aclk", "iface";
		#iommu-cells = <0>;
		status = "disabled";
	};

	isp: isp@ff910000 {
		compatible = "rockchip,rk3288-isp", "rockchip,isp";
		reg = <0x0 0xff910000 0x0 0x4000>;
		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&power RK3288_PD_VIO>;
		clocks =
			<&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
			<&cru SCLK_ISP_JPE>, <&cru PCLK_ISP_IN>,
			<&cru SCLK_VIP_OUT>, <&cru SCLK_MIPIDSI_24M>,
			<&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>;
		clock-names =
			"aclk_isp", "hclk_isp", "clk_isp",
			"clk_isp_jpe", "pclkin_isp", "clk_cif_out",
			"clk_mipi_24m", "clk_cif_pll", "hclk_mipiphy1";
		pinctrl-names =
			"default", "isp_dvp8bit2", "isp_dvp10bit",
			"isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl",
			"isp_mipi_fl_prefl", "isp_flash_as_gpio",
			"isp_flash_as_trigger_out";
		pinctrl-0 = <&isp_mipi>;
		pinctrl-1 = <&isp_mipi &isp_dvp_d2d9>;
		pinctrl-2 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1>;
		pinctrl-3 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1
					&isp_dvp_d10d11>;
		pinctrl-4 = <&isp_mipi &isp_dvp_d0d7>;
		pinctrl-5 = <&isp_mipi>;
		pinctrl-6 = <&isp_mipi &isp_prelight>;
		pinctrl-7 = <&isp_flash_trigger_as_gpio>;
		pinctrl-8 = <&isp_flash_trigger>;
		rockchip,isp,mipiphy = <2>;
		rockchip,isp,cifphy = <1>;
		rockchip,isp,mipiphy1,reg = <0xff968000 0x4000>;
		rockchip,grf = <&grf>;
		rockchip,cru = <&cru>;
		rockchip,gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>;
		rockchip,isp,iommu_enable = <1>;
		iommus = <&isp_mmu>;
		status = "disabled";
	};

	rkisp1: rkisp1@ff910000 {
		compatible = "rockchip,rk3288-rkisp1";
		reg = <0x0 0xff910000 0x0 0x4000>;
		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "isp_irq";
		clocks = <&cru SCLK_ISP>, <&cru ACLK_ISP>,
			<&cru HCLK_ISP>, <&cru PCLK_ISP_IN>,
			<&cru SCLK_ISP_JPE>;
		clock-names = "clk_isp", "aclk_isp",
			"hclk_isp", "pclk_isp_in",
			"sclk_isp_jpe";
		assigned-clocks = <&cru SCLK_ISP>, <&cru SCLK_ISP_JPE>;
		assigned-clock-rates = <400000000>, <400000000>;
		power-domains = <&power RK3288_PD_VIO>;
		iommus = <&isp_mmu>;
		status = "disabled";
	};

	isp_mmu: iommu@ff914000 {
		compatible = "rockchip,iommu";
		reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
		clock-names = "aclk", "iface";
		#iommu-cells = <0>;
		rockchip,disable-mmu-reset;
		status = "disabled";
	};

	rga: rga@ff920000 {
		compatible = "rockchip,rk3288-rga";
		reg = <0x0 0xff920000 0x0 0x180>;
		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
		clock-names = "aclk", "hclk", "sclk";
		power-domains = <&power RK3288_PD_VIO>;
		resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
		reset-names = "core", "axi", "ahb";
		status = "disabled";
	};

	vopb: vop@ff930000 {
		compatible = "rockchip,rk3288-vop-big";
		reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>;
		reg-names = "regs", "gamma_lut";
		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
		power-domains = <&power RK3288_PD_VIO>;
		resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
		reset-names = "axi", "ahb", "dclk";
		iommus = <&vopb_mmu>;
		status = "disabled";

		vopb_out: port {
			#address-cells = <1>;
			#size-cells = <0>;

			vopb_out_hdmi: endpoint@0 {
				reg = <0>;
				remote-endpoint = <&hdmi_in_vopb>;
			};

			vopb_out_edp: endpoint@1 {
				reg = <1>;
				remote-endpoint = <&edp_in_vopb>;
			};

			vopb_out_dsi0: endpoint@2 {
				reg = <2>;
				remote-endpoint = <&dsi0_in_vopb>;
			};

			vopb_out_dsi1: endpoint@3 {
				reg = <3>;
				remote-endpoint = <&dsi1_in_vopb>;
			};

			vopb_out_lvds: endpoint@4 {
				reg = <4>;
				remote-endpoint = <&lvds_in_vopb>;
			};

			vopb_out_rgb: endpoint@5 {
				reg = <5>;
				remote-endpoint = <&rgb_in_vopb>;
			};
		};
	};

	vopb_mmu: iommu@ff930300 {
		compatible = "rockchip,iommu";
		reg = <0x0 0xff930300 0x0 0x100>;
		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
		clock-names = "aclk", "iface";
		power-domains = <&power RK3288_PD_VIO>;
		#iommu-cells = <0>;
		rockchip,disable-device-link-resume;
		status = "disabled";
	};

	vopl: vop@ff940000 {
		compatible = "rockchip,rk3288-vop-lit";
		reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>;
		reg-names = "regs", "gamma_lut";
		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
		power-domains = <&power RK3288_PD_VIO>;
		resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
		reset-names = "axi", "ahb", "dclk";
		iommus = <&vopl_mmu>;
		status = "disabled";

		vopl_out: port {
			#address-cells = <1>;
			#size-cells = <0>;

			vopl_out_hdmi: endpoint@0 {
				reg = <0>;
				remote-endpoint = <&hdmi_in_vopl>;
			};

			vopl_out_edp: endpoint@1 {
				reg = <1>;
				remote-endpoint = <&edp_in_vopl>;
			};

			vopl_out_dsi0: endpoint@2 {
				reg = <2>;
				remote-endpoint = <&dsi0_in_vopl>;
			};

			vopl_out_dsi1: endpoint@3 {
				reg = <3>;
				remote-endpoint = <&dsi1_in_vopl>;
			};

			vopl_out_lvds: endpoint@4 {
				reg = <4>;
				remote-endpoint = <&lvds_in_vopl>;
			};

			vopl_out_rgb: endpoint@5 {
				reg = <5>;
				remote-endpoint = <&rgb_in_vopl>;
			};
		};
	};

	vopl_mmu: iommu@ff940300 {
		compatible = "rockchip,iommu";
		reg = <0x0 0xff940300 0x0 0x100>;
		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
		clock-names = "aclk", "iface";
		power-domains = <&power RK3288_PD_VIO>;
		#iommu-cells = <0>;
		rockchip,disable-device-link-resume;
		status = "disabled";
	};

	cif: cif@ff950000 {
		compatible = "rockchip,cif", "rockchip,rk3288-cif";
		reg = <0x0 0xff950000 0x0 0x400>;
		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_VIP>, <&cru HCLK_VIP>,
			<&cru PCLK_VIP_IN>, <&cru SCLK_VIP_OUT>;
		clock-names = "aclk_cif0", "hclk_cif0",
				"cif0_in", "cif0_out";
		resets = <&cru SRST_VIP>;
		reset-names = "rst_cif";
		pinctrl-names = "cif_pin_all";
		pinctrl-0 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d10d11>;
		rockchip,grf = <&grf>;
		rockchip,cru = <&cru>;
		power-domains = <&power RK3288_PD_VIO>;
		status = "disabled";
	};

	dsi0: dsi@ff960000 {
		compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
		reg = <0x0 0xff960000 0x0 0x4000>;
		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
		clock-names = "ref", "pclk";
		resets = <&cru SRST_MIPIDSI0>;
		reset-names = "apb";
		power-domains = <&power RK3288_PD_VIO>;
		rockchip,grf = <&grf>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";

		ports {
			mipi_in: port {
				#address-cells = <1>;
				#size-cells = <0>;
				dsi0_in_vopb: endpoint@0 {
					reg = <0>;
					remote-endpoint = <&vopb_out_dsi0>;
				};
				dsi0_in_vopl: endpoint@1 {
					reg = <1>;
					remote-endpoint = <&vopl_out_dsi0>;
				};
			};
		};
	};

	dsi1: dsi@ff964000 {
		compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
		reg = <0x0 0xff964000 0x0 0x4000>;
		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI1>;
		clock-names = "ref", "pclk";
		resets = <&cru SRST_MIPIDSI1>;
		reset-names = "apb";
		power-domains = <&power RK3288_PD_VIO>;
		rockchip,grf = <&grf>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			dsi1_in: port {
				#address-cells = <1>;
				#size-cells = <0>;

				dsi1_in_vopb: endpoint@0 {
					reg = <0>;
					remote-endpoint = <&vopb_out_dsi1>;
				};
				dsi1_in_vopl: endpoint@1 {
					reg = <1>;
					remote-endpoint = <&vopl_out_dsi1>;
				};
			};
		};
	};

	video_phy: video-phy@ff96c000 {
		compatible = "rockchip,rk3288-video-phy";
		reg = <0x0 0xff96c000 0x0 0x4000>;
		clocks = <&cru PCLK_LVDS_PHY>;
		clock-names = "pclk";
		resets = <&cru SRST_LVDS_PHY>;
		reset-names = "rst";
		power-domains = <&power RK3288_PD_VIO>;
		#phy-cells = <0>;
		status = "disabled";
	};

	edp: dp@ff970000 {
		compatible = "rockchip,rk3288-dp";
		reg = <0x0 0xff970000 0x0 0x4000>;
		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>,
			 <&cru SCLK_EDP>;
		clock-names = "dp", "pclk", "spdif";
		assigned-clocks = <&cru SCLK_EDP_24M>;
		assigned-clock-parents = <&xin24m>;
		power-domains = <&power RK3288_PD_VIO>;
		resets = <&cru SRST_EDP>;
		reset-names = "dp";
		rockchip,grf = <&grf>;
		status = "disabled";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;
			edp_in: port@0 {
				reg = <0>;
				#address-cells = <1>;
				#size-cells = <0>;
				edp_in_vopb: endpoint@0 {
					reg = <0>;
					remote-endpoint = <&vopb_out_edp>;
				};
				edp_in_vopl: endpoint@1 {
					reg = <1>;
					remote-endpoint = <&vopl_out_edp>;
				};
			};
		};
	};

	hdmi: hdmi@ff980000 {
		compatible = "rockchip,rk3288-dw-hdmi";
		reg = <0x0 0xff980000 0x0 0x20000>;
		reg-io-width = <4>;
		#sound-dai-cells = <0>;
		rockchip,grf = <&grf>;
		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
		clock-names = "iahb", "isfr", "cec";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&hdmi_ddc>;
		pinctrl-1 = <&hdmi_gpio>;
		power-domains = <&power RK3288_PD_VIO>;
		unsupported-yuv-input;
		status = "disabled";

		ports {
			hdmi_in: port {
				#address-cells = <1>;
				#size-cells = <0>;
				hdmi_in_vopb: endpoint@0 {
					reg = <0>;
					remote-endpoint = <&vopb_out_hdmi>;
				};
				hdmi_in_vopl: endpoint@1 {
					reg = <1>;
					remote-endpoint = <&vopl_out_hdmi>;
				};
			};
		};
	};

	vpu: video-codec@ff9a0000 {
		compatible = "rockchip,rk3288-vpu";
		reg = <0x0 0xff9a0000 0x0 0x800>;
		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "vepu", "vdpu";
		clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
		clock-names = "aclk", "hclk";
		iommus = <&vpu_mmu>;
		power-domains = <&power RK3288_PD_VIDEO>;
		status = "disabled";
	};

	mpp_srv: mpp-srv {
		compatible = "rockchip,mpp-service";
		rockchip,taskqueue-count = <2>;
		rockchip,resetgroup-count = <2>;
		status = "disabled";
	};

	vepu: vepu@ff9a0000 {
		compatible = "rockchip,vpu-encoder-v1";
		reg = <0x0 0xff9a0000 0x0 0x400>;
		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "irq_enc";
		clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
		clock-names = "aclk_vcodec", "hclk_vcodec";
		resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
		reset-names = "shared_video_a", "shared_video_h";
		assigned-clocks = <&cru ACLK_VCODEC>;
		assigned-clock-rates = <400000000>;
		iommus = <&vpu_mmu>;
		power-domains = <&power RK3288_PD_VIDEO>;
		rockchip,srv = <&mpp_srv>;
		rockchip,taskqueue-node = <0>;
		rockchip,resetgroup-node = <0>;
		status = "disabled";
	};

	vdpu: vdpu@ff9a0400 {
		compatible = "rockchip,vpu-decoder-rk3288", "rockchip,vpu-decoder-v1";
		reg = <0x0 0xff9a0400 0x0 0x400>;
		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "irq_dec";
		clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
		clock-names = "aclk_vcodec", "hclk_vcodec";
		rockchip,normal-rates = <300000000>, <0>;
		rockchip,advanced-rates = <600000000>, <0>;
		resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
		reset-names = "shared_video_a", "shared_video_h";
		assigned-clocks = <&cru ACLK_VCODEC>;
		assigned-clock-rates = <400000000>;
		iommus = <&vpu_mmu>;
		power-domains = <&power RK3288_PD_VIDEO>;
		rockchip,srv = <&mpp_srv>;
		rockchip,taskqueue-node = <0>;
		rockchip,resetgroup-node = <0>;
		status = "disabled";
	};

	vpu_mmu: iommu@ff9a0800 {
		compatible = "rockchip,iommu";
		reg = <0x0 0xff9a0800 0x0 0x100>;
		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
		clock-names = "aclk", "iface";
		#iommu-cells = <0>;
		power-domains = <&power RK3288_PD_VIDEO>;
		status = "disabled";
	};

	hevc: hevc_service@ff9c0000 {
		compatible = "rockchip,hevc-decoder";
		reg = <0x0 0xff9c0000 0x0 0x400>;
		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "irq_dec";
		clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>, <&cru SCLK_HEVC_CORE>,
			 <&cru SCLK_HEVC_CABAC>;
		clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
			      "clk_cabac";
		rockchip,normal-rates = <300000000>, <0>, <200000000>,
				<200000000>;
		rockchip,advanced-rates = <500000000>, <0>, <400000000>,
				<400000000>;
		rockchip,default-max-load = <2088960>;
		resets =  <&cru SRST_HEVC>;
		reset-names = "video_core";

		/*
		 * The 4K hevc would also work well with 500/125/300/300,
		 * no more err irq and reset request.
		 */
		assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
				  <&cru SCLK_HEVC_CORE>,
				  <&cru SCLK_HEVC_CABAC>;
		assigned-clock-rates = <400000000>, <100000000>,
				       <300000000>, <300000000>;
		iommus = <&hevc_mmu>;
		rockchip,srv = <&mpp_srv>;
		rockchip,taskqueue-node = <1>;
		rockchip,resetgroup-node = <1>;
		power-domains = <&power RK3288_PD_HEVC>;
		status = "disabled";
	};

	hevc_mmu: iommu@ff9c0440 {
		compatible = "rockchip,iommu";
		reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
		interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>;
		clock-names = "aclk", "iface";
		power-domains = <&power RK3288_PD_HEVC>;
		#iommu-cells = <0>;
		status = "disabled";
	};

	gpu: gpu@ffa30000 {
		compatible = "rockchip,rk3288-mali", "arm,mali-t760",
			     "arm,malit764", "arm,malit76x", "arm,malit7xx",
			     "arm,mali-midgard";
		reg = <0x0 0xffa30000 0x0 0x10000>;
		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "job", "mmu", "gpu";
		clocks = <&cru ACLK_GPU>;
		clock-names = "clk_mali";
		operating-points-v2 = <&gpu_opp_table>;
		#cooling-cells = <2>; /* min followed by max */
		power-domains = <&power RK3288_PD_GPU>;
		status = "disabled";

		upthreshold = <75>;
		downdifferential = <10>;

		gpu_power_model: power_model {
			compatible = "arm,mali-simple-power-model";
			static-coefficient = <411000>;
			dynamic-coefficient = <733>;
			ts = <32000 4700 (-80) 2>;
			thermal-zone = "gpu-thermal";
		};
	};

	gpu_opp_table: opp-table-1 {
		compatible = "operating-points-v2";

		clocks = <&cru PLL_GPLL>;
		nvmem-cells = <&performance>, <&performance_w>;
		nvmem-cell-names = "performance", "performance-w";
		rockchip,bin-scaling-sel = <
			0               55
			1               59
			2               61
			3               61
		>;

		opp-100000000 {
			opp-hz = /bits/ 64 <100000000>;
			opp-microvolt = <950000>;
		};
		opp-200000000 {
			opp-hz = /bits/ 64 <200000000>;
			opp-microvolt = <950000>;
		};
		opp-300000000 {
			opp-hz = /bits/ 64 <300000000>;
			opp-microvolt = <1000000>;
		};
		opp-420000000 {
			opp-hz = /bits/ 64 <420000000>;
			opp-microvolt = <1100000>;
		};
		opp-600000000 {
			opp-hz = /bits/ 64 <600000000>;
			opp-microvolt = <1250000>;
		};
	};

	qos_gpu_r: qos@ffaa0000 {
		compatible = "rockchip,rk3288-qos", "syscon";
		reg = <0x0 0xffaa0000 0x0 0x20>;
	};

	qos_gpu_w: qos@ffaa0080 {
		compatible = "rockchip,rk3288-qos", "syscon";
		reg = <0x0 0xffaa0080 0x0 0x20>;
	};

	qos_vio1_vop: qos@ffad0000 {
		compatible = "rockchip,rk3288-qos", "syscon";
		reg = <0x0 0xffad0000 0x0 0x20>;
	};

	qos_vio1_isp_w0: qos@ffad0100 {
		compatible = "rockchip,rk3288-qos", "syscon";
		reg = <0x0 0xffad0100 0x0 0x20>;
	};

	qos_vio1_isp_w1: qos@ffad0180 {
		compatible = "rockchip,rk3288-qos", "syscon";
		reg = <0x0 0xffad0180 0x0 0x20>;
	};

	qos_vio0_vop: qos@ffad0400 {
		compatible = "rockchip,rk3288-qos", "syscon";
		reg = <0x0 0xffad0400 0x0 0x20>;
	};

	qos_vio0_vip: qos@ffad0480 {
		compatible = "rockchip,rk3288-qos", "syscon";
		reg = <0x0 0xffad0480 0x0 0x20>;
	};

	qos_vio0_iep: qos@ffad0500 {
		compatible = "rockchip,rk3288-qos", "syscon";
		reg = <0x0 0xffad0500 0x0 0x20>;
	};

	qos_vio2_rga_r: qos@ffad0800 {
		compatible = "rockchip,rk3288-qos", "syscon";
		reg = <0x0 0xffad0800 0x0 0x20>;
	};

	qos_vio2_rga_w: qos@ffad0880 {
		compatible = "rockchip,rk3288-qos", "syscon";
		reg = <0x0 0xffad0880 0x0 0x20>;
	};

	qos_vio1_isp_r: qos@ffad0900 {
		compatible = "rockchip,rk3288-qos", "syscon";
		reg = <0x0 0xffad0900 0x0 0x20>;
	};

	qos_video: qos@ffae0000 {
		compatible = "rockchip,rk3288-qos", "syscon";
		reg = <0x0 0xffae0000 0x0 0x20>;
	};

	qos_hevc_r: qos@ffaf0000 {
		compatible = "rockchip,rk3288-qos", "syscon";
		reg = <0x0 0xffaf0000 0x0 0x20>;
	};

	qos_hevc_w: qos@ffaf0080 {
		compatible = "rockchip,rk3288-qos", "syscon";
		reg = <0x0 0xffaf0080 0x0 0x20>;
	};

	dmac_bus_s: dma-controller@ffb20000 {
		compatible = "arm,pl330", "arm,primecell";
		reg = <0x0 0xffb20000 0x0 0x4000>;
		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
		#dma-cells = <1>;
		arm,pl330-broken-no-flushp;
		arm,pl330-periph-burst;
		clocks = <&cru ACLK_DMAC1>;
		clock-names = "apb_pclk";
	};

	efuse: efuse@ffb40000 {
		compatible = "rockchip,rk3288-efuse";
		reg = <0x0 0xffb40000 0x0 0x20>;
		#address-cells = <1>;
		#size-cells = <1>;
		clocks = <&cru PCLK_EFUSE256>;
		clock-names = "pclk_efuse";

		special_function: special-function@5 {
			reg = <0x5 0x1>;
			bits = <4 4>;
		};
		package_info: package-info@5 {
			reg = <0x5 0x1>;
			bits = <2 2>;
		};
		process_version: process-version@6 {
			reg = <0x6 0x1>;
			bits = <0 4>;
		};
		cpu_id: cpu-id@7 {
			reg = <0x07 0x10>;
		};
		cpu_leakage: cpu_leakage@17 {
			reg = <0x17 0x1>;
		};
		performance_w: performance@1c {
			reg = <0x1c 0x1>;
			bits = <4 3>;
		};
		performance: performance@1d {
			reg = <0x1d 0x1>;
			bits = <4 3>;
		};
	};

	gic: interrupt-controller@ffc01000 {
		compatible = "arm,gic-400";
		interrupt-controller;
		#interrupt-cells = <3>;
		#address-cells = <0>;

		reg = <0x0 0xffc01000 0x0 0x1000>,
		      <0x0 0xffc02000 0x0 0x2000>,
		      <0x0 0xffc04000 0x0 0x2000>,
		      <0x0 0xffc06000 0x0 0x2000>;
		interrupts = <GIC_PPI 9 0xf04>;
	};

	rockchip_system_monitor: rockchip-system-monitor {
		compatible = "rockchip,system-monitor";
	};

	rockchip_suspend: rockchip-suspend {
		compatible = "rockchip,pm-rk3288";
		status = "disabled";
		rockchip,sleep-mode-config = <
			(0
			|RKPM_CTR_PWR_DMNS
			|RKPM_CTR_GTCLKS
			|RKPM_CTR_PLLS
			|RKPM_CTR_ARMOFF_LPMD
			|RKPM_CTR_SYSCLK_OSC_DIS
			)
		>;
		rockchip,wakeup-config = <
			(0
			| RKPM_GPIO_WKUP_EN
			)
		>;
		rockchip,pwm-regulator-config = <
			(0
			| PWM2_REGULATOR_EN
			)
		>;
	};

	pinctrl: pinctrl {
		compatible = "rockchip,rk3288-pinctrl";
		rockchip,grf = <&grf>;
		rockchip,pmu = <&pmu>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		gpio0: gpio@ff750000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xff750000 0x0 0x100>;
			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO0>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio1: gpio@ff780000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xff780000 0x0 0x100>;
			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO1>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio@ff790000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xff790000 0x0 0x100>;
			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO2>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio@ff7a0000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xff7a0000 0x0 0x100>;
			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO3>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio4: gpio@ff7b0000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xff7b0000 0x0 0x100>;
			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO4>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio5: gpio@ff7c0000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xff7c0000 0x0 0x100>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO5>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio6: gpio@ff7d0000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xff7d0000 0x0 0x100>;
			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO6>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio7: gpio@ff7e0000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xff7e0000 0x0 0x100>;
			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO7>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio8: gpio@ff7f0000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xff7f0000 0x0 0x100>;
			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO8>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		pcfg_pull_none_12ma: pcfg-pull-none-12ma {
			bias-disable;
			drive-strength = <12>;
		};
	};
};

#include "rk3288-pinctrl.dtsi"