Enabled Panthor support on the dts-level

This commit is contained in:
Nathan 2025-02-04 15:42:42 -06:00
parent 6fef0bac9d
commit b2214c9509

View File

@ -2366,7 +2366,7 @@
}; };
}; };
gpu: gpu@fb000000 { gpu_mali: gpu-mali@fb000000 {
compatible = "arm,mali-bifrost"; compatible = "arm,mali-bifrost";
reg = <0x0 0xfb000000 0x0 0x200000>; reg = <0x0 0xfb000000 0x0 0x200000>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
@ -2391,7 +2391,7 @@
status = "disabled"; status = "disabled";
}; };
gpu_panthor: gpu-panthor@fb000000 { gpu: gpu@fb000000 {
compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf"; compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf";
reg = <0x0 0xfb000000 0x0 0x200000>; reg = <0x0 0xfb000000 0x0 0x200000>;
#cooling-cells = <2>; #cooling-cells = <2>;
@ -5519,10 +5519,6 @@
compatible = "rockchip,rk3588-dfi"; compatible = "rockchip,rk3588-dfi";
reg = <0x00 0xfe060000 0x00 0x10000>; reg = <0x00 0xfe060000 0x00 0x10000>;
rockchip,pmu_grf = <&pmu1_grf>; rockchip,pmu_grf = <&pmu1_grf>;
clocks = <&cru PCLK_DDR_MON_CH0>, <&cru PCLK_DDR_MON_CH1>,
<&cru PCLK_DDR_MON_CH2>, <&cru PCLK_DDR_MON_CH3>;
clock-names = "pclk_ddr_mon_ch0", "pclk_ddr_mon_ch1",
"pclk_ddr_mon_ch2", "pclk_ddr_mon_ch3";
status = "disabled"; status = "disabled";
}; };
@ -6673,8 +6669,8 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,
<&cru CLK_OTP_PHY_G>; <&cru CLK_OTPC_ARB>, <&cru CLK_OTP_PHY_G>;
clock-names = "otpc", "apb", "phy"; clock-names = "otpc", "apb", "arb", "phy";
resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>, resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>,
<&cru SRST_OTPC_ARB>; <&cru SRST_OTPC_ARB>;
reset-names = "otpc", "apb", "arb"; reset-names = "otpc", "apb", "arb";