139 lines
3.5 KiB
C
139 lines
3.5 KiB
C
/*
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* Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* Based on drivers/misc/eeprom/sunxi_sid.c
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*/
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#include <linux/device.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/kobject.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/random.h>
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#include <linux/tegra-soc.h>
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#include "fuse.h"
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#define FUSE_BEGIN 0x100
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#define FUSE_SIZE 0x1f8
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#define FUSE_SKU_INFO 0x10
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#define FUSE_UID_LOW 0x08
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#define FUSE_UID_HIGH 0x0c
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static phys_addr_t fuse_phys;
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static struct clk *fuse_clk;
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static struct tegra_sku_info sku_info;
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static u32 tegra20_fuse_readl(const unsigned int offset)
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{
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int ret;
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u32 val;
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clk_prepare_enable(fuse_clk);
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ret = tegra_apb_readl_using_dma(fuse_phys + FUSE_BEGIN + offset, &val);
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clk_disable_unprepare(fuse_clk);
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return (ret < 0) ? 0 : val;
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}
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static void tegra20_fuse_add_randomness(void)
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{
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u32 randomness[7];
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randomness[0] = tegra20_fuse_readl(FUSE_SKU_INFO);
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randomness[1] = tegra_read_straps();
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randomness[2] = tegra_read_chipid();
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randomness[3] = sku_info.cpu_process_id << 16;
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randomness[3] |= sku_info.core_process_id;
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randomness[4] = sku_info.cpu_speedo_id << 16 | sku_info.soc_speedo_id;
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randomness[5] = tegra20_fuse_readl(FUSE_UID_LOW);
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randomness[6] = tegra20_fuse_readl(FUSE_UID_HIGH);
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add_device_randomness(randomness, sizeof(randomness));
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}
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bool tegra20_spare_fuse(int spare_bit)
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{
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u32 offset = spare_bit * 4 + 0x100;
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return tegra20_fuse_readl(offset) & 1;
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}
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bool tegra20_spare_fuse_early(int spare_bit, void *fuse_base)
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{
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u32 offset = spare_bit * 4 + 0x100;
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return readl_relaxed(fuse_base + FUSE_BEGIN + offset);
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}
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static const struct of_device_id tegra20_fuse_of_match[] = {
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{ .compatible = "nvidia,tegra20-efuse" },
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{},
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}
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MODULE_DEVICE_TABLE(of, tegra20_fuse_of_match);
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static int tegra20_fuse_probe(struct platform_device *pdev)
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{
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struct resource *res;
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fuse_clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(fuse_clk)) {
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dev_err(&pdev->dev, "missing clock");
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return PTR_ERR(fuse_clk);
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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return -EINVAL;
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fuse_phys = res->start;
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tegra_sku_id = tegra20_fuse_readl(FUSE_SKU_INFO) & 0xff;
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sku_info.sku_id = tegra_sku_id;
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sku_info.revision = tegra_revision;
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tegra20_init_speedo_data(&sku_info, &pdev->dev);
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dev_dbg(&pdev->dev, "Soc Speedo ID %d", sku_info.soc_speedo_id);
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tegra20_fuse_add_randomness();
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if (tegra_fuse_create_sysfs(&pdev->dev, FUSE_SIZE, tegra20_fuse_readl,
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NULL, &sku_info))
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return -ENODEV;
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dev_dbg(&pdev->dev, "loaded\n");
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return 0;
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}
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static struct platform_driver tegra20_fuse_driver = {
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.probe = tegra20_fuse_probe,
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.driver = {
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.name = "tegra20_fuse",
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.owner = THIS_MODULE,
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.of_match_table = tegra20_fuse_of_match,
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}
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};
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static int __init tegra20_fuse_init(void)
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{
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return platform_driver_register(&tegra20_fuse_driver);
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}
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postcore_initcall(tegra20_fuse_init);
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