33 lines
1.2 KiB
Plaintext
33 lines
1.2 KiB
Plaintext
NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 fuse driver.
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Required properties:
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- compatible : should be:
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"nvidia,tegra20-efuse"
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"nvidia,tegra30-efuse"
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"nvidia,tegra114-efuse"
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"nvidia,tegra124-efuse"
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Details:
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nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data
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due to a hardware bug. Tegra20 also lacks certain information which is
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available in later generations such as fab code, lot code, wafer id,..
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nvidia,tegra30-efuse, nvidia,tegra114-efuse and nvidia,tegra124-efuse:
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The differences between these SoCs are the size of the efuse array,
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the location of the spare (OEM programmable) bits and the location of
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the speedo data.
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- reg: Should contain 2 entries: the first entry gives the physical address
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and length of the fuse registers, the second entry gives the physical
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address and length of the apbmisc registers. These are used to provide
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the chipid, chip revision and strapping options.
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- clocks: Should contain a pointer to the fuse clock.
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Example:
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fuse@7000f800 {
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compatible = "nvidia,tegra20-efuse";
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reg = <0x7000F800 0x400>,
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<0x70000000 0x400>;
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clocks = <&tegra_car TEGRA20_CLK_FUSE>;
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};
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