705 lines
16 KiB
C
705 lines
16 KiB
C
/*
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* Copyright (C) 2013 NVIDIA Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/debugfs.h>
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#include <linux/delay.h>
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#include <linux/gpio.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/of_gpio.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <linux/tegra-powergate.h>
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#include <drm/drm_dp_helper.h>
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#include <drm/drm_panel.h>
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#include "dpaux.h"
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#include "drm.h"
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static DEFINE_MUTEX(dpaux_lock);
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static LIST_HEAD(dpaux_list);
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struct tegra_dpaux {
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struct drm_dp_aux aux;
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struct host1x_client client;
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struct device *dev;
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void __iomem *regs;
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int irq;
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struct tegra_output *output;
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struct reset_control *rst;
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struct clk *clk_parent;
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struct clk *clk;
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struct completion complete;
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struct list_head list;
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bool enabled;
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struct drm_minor *minor;
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struct drm_info_list *debugfs_files;
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struct dentry *debugfs;
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};
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static inline struct tegra_dpaux *
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host1x_client_to_dpaux(struct host1x_client *client)
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{
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return container_of(client, struct tegra_dpaux, client);
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}
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static inline struct tegra_dpaux *to_dpaux(struct drm_dp_aux *aux)
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{
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return container_of(aux, struct tegra_dpaux, aux);
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}
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static inline unsigned long tegra_dpaux_readl(struct tegra_dpaux *dpaux,
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unsigned long offset)
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{
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return readl(dpaux->regs + (offset << 2));
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}
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static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux,
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unsigned long value,
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unsigned long offset)
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{
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writel(value, dpaux->regs + (offset << 2));
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}
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static void tegra_dpaux_write_fifo(struct tegra_dpaux *dpaux, const u8 *buffer,
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size_t size)
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{
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unsigned long offset = DPAUX_DP_AUXDATA_WRITE(0);
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size_t i, j;
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for (i = 0; i < size; i += 4) {
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size_t num = min_t(size_t, size - i, 4);
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unsigned long value = 0;
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for (j = 0; j < num; j++)
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value |= buffer[i + j] << (j * 8);
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tegra_dpaux_writel(dpaux, value, offset++);
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}
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}
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static void tegra_dpaux_read_fifo(struct tegra_dpaux *dpaux, u8 *buffer,
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size_t size)
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{
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unsigned long offset = DPAUX_DP_AUXDATA_READ(0);
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size_t i, j;
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for (i = 0; i < size; i += 4) {
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size_t num = min_t(size_t, size - i, 4);
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unsigned long value;
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value = tegra_dpaux_readl(dpaux, offset++);
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for (j = 0; j < num; j++)
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buffer[i + j] = value >> (j * 8);
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}
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}
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static int tegra_dpaux_wait_plugged(struct tegra_dpaux *dpaux)
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{
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unsigned long value;
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unsigned long timeout;
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/*
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* Typical plugged latency is 250us, but we use usleep below which
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* involves kernel schedule, so set a somewhat big timeout here.
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*/
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timeout = jiffies + msecs_to_jiffies(250);
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while (time_before(jiffies, timeout)) {
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value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
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if (value & DPAUX_DP_AUXSTAT_HPD_STATUS)
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return 0;
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usleep_range(1000, 2000);
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}
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/* Recheck in case the polling is skipped due to process schedule */
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value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
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if (value & DPAUX_DP_AUXSTAT_HPD_STATUS) {
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return 0;
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} else {
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WARN(1, "dpaux waits for plugged timeout.\n");
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return -ETIMEDOUT;
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}
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}
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static ssize_t tegra_dpaux_transfer(struct drm_dp_aux *aux,
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struct drm_dp_aux_msg *msg)
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{
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unsigned long timeout = msecs_to_jiffies(250);
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struct tegra_dpaux *dpaux = to_dpaux(aux);
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unsigned long status;
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ssize_t ret = 0;
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u32 value;
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/* Tegra has 4x4 byte DP AUX transmit and receive FIFOs. */
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if (msg->size > 16)
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return -EINVAL;
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/*
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* Allow zero-sized messages only for I2C, in which case they specify
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* address-only transactions.
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*/
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if (msg->size < 1) {
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switch (msg->request & ~DP_AUX_I2C_MOT) {
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case DP_AUX_I2C_WRITE:
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case DP_AUX_I2C_READ:
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value = DPAUX_DP_AUXCTL_CMD_ADDRESS_ONLY;
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break;
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default:
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return -EINVAL;
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}
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} else {
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/* For non-zero-sized messages, set the CMDLEN field. */
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value = DPAUX_DP_AUXCTL_CMDLEN(msg->size - 1);
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}
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switch (msg->request & ~DP_AUX_I2C_MOT) {
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case DP_AUX_I2C_WRITE:
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if (msg->request & DP_AUX_I2C_MOT)
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value |= DPAUX_DP_AUXCTL_CMD_MOT_WR;
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else
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value |= DPAUX_DP_AUXCTL_CMD_I2C_WR;
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break;
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case DP_AUX_I2C_READ:
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if (msg->request & DP_AUX_I2C_MOT)
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value |= DPAUX_DP_AUXCTL_CMD_MOT_RD;
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else
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value |= DPAUX_DP_AUXCTL_CMD_I2C_RD;
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break;
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case DP_AUX_I2C_STATUS:
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if (msg->request & DP_AUX_I2C_MOT)
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value |= DPAUX_DP_AUXCTL_CMD_MOT_RQ;
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else
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value |= DPAUX_DP_AUXCTL_CMD_I2C_RQ;
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break;
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case DP_AUX_NATIVE_WRITE:
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value |= DPAUX_DP_AUXCTL_CMD_AUX_WR;
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break;
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case DP_AUX_NATIVE_READ:
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value |= DPAUX_DP_AUXCTL_CMD_AUX_RD;
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break;
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default:
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return -EINVAL;
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}
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if (!dpaux->enabled)
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tegra_dpaux_enable(dpaux);
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if (tegra_dpaux_wait_plugged(dpaux) < 0) {
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WARN(1, "wait HPD failed in dpaux transfer.\n");
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ret = -ETIMEDOUT;
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goto out;
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}
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tegra_dpaux_writel(dpaux, msg->address, DPAUX_DP_AUXADDR);
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tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
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if ((msg->request & DP_AUX_I2C_READ) == 0) {
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tegra_dpaux_write_fifo(dpaux, msg->buffer, msg->size);
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ret = msg->size;
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}
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/* start transaction */
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value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXCTL);
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value |= DPAUX_DP_AUXCTL_TRANSACTREQ;
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tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
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status = wait_for_completion_timeout(&dpaux->complete, timeout);
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if (!status) {
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WARN(1, "wait dpaux transfer complete timeout.\n");
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ret = -ETIMEDOUT;
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goto out;
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}
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/* read status and clear errors */
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value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
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tegra_dpaux_writel(dpaux, 0xf00, DPAUX_DP_AUXSTAT);
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if (value & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR) {
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WARN(1, "dpaux transfer error: timedout.\n");
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ret = -ETIMEDOUT;
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goto out;
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}
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if ((value & DPAUX_DP_AUXSTAT_RX_ERROR) ||
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(value & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR) ||
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(value & DPAUX_DP_AUXSTAT_NO_STOP_ERROR)) {
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ret = -EIO;
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goto out;
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}
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switch ((value & DPAUX_DP_AUXSTAT_REPLY_TYPE_MASK) >> 16) {
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case 0x00:
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msg->reply = DP_AUX_NATIVE_REPLY_ACK;
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break;
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case 0x01:
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msg->reply = DP_AUX_NATIVE_REPLY_NACK;
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break;
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case 0x02:
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msg->reply = DP_AUX_NATIVE_REPLY_DEFER;
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break;
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case 0x04:
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msg->reply = DP_AUX_I2C_REPLY_NACK;
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break;
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case 0x08:
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msg->reply = DP_AUX_I2C_REPLY_DEFER;
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break;
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}
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if ((msg->size > 0) && (msg->reply == DP_AUX_NATIVE_REPLY_ACK)) {
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if (msg->request & DP_AUX_I2C_READ) {
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size_t count = value & DPAUX_DP_AUXSTAT_REPLY_MASK;
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if (WARN_ON(count != msg->size))
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count = min_t(size_t, count, msg->size);
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tegra_dpaux_read_fifo(dpaux, msg->buffer, count);
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ret = count;
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}
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} else if (msg->reply &
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(DP_AUX_NATIVE_REPLY_DEFER | DP_AUX_I2C_REPLY_DEFER)) {
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/* return the requested size for retry */
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ret = msg->size;
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}
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out:
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return ret;
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}
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static irqreturn_t tegra_dpaux_irq(int irq, void *data)
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{
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struct tegra_dpaux *dpaux = data;
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irqreturn_t ret = IRQ_HANDLED;
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unsigned long value;
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/* clear interrupts */
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value = tegra_dpaux_readl(dpaux, DPAUX_INTR_AUX);
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tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
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if (value & DPAUX_INTR_IRQ_EVENT) {
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/* TODO: handle this */
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}
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if (value & DPAUX_INTR_AUX_DONE)
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complete(&dpaux->complete);
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return ret;
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}
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static int tegra_dpaux_show_regs(struct seq_file *s, void *data)
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{
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struct drm_info_node *node = s->private;
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struct tegra_dpaux *dpaux = node->info_ent->data;
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#define DUMP_REG(name) \
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seq_printf(s, "%-40s %#05x %08lx\n", #name, name, \
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tegra_dpaux_readl(dpaux, name))
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DUMP_REG(DPAUX_CTXSW);
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DUMP_REG(DPAUX_INTR_EN_AUX);
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DUMP_REG(DPAUX_INTR_AUX);
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DUMP_REG(DPAUX_DP_AUXADDR);
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DUMP_REG(DPAUX_DP_AUXCTL);
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DUMP_REG(DPAUX_DP_AUXSTAT);
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DUMP_REG(DPAUX_DP_AUX_SINKSTAT_LO);
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DUMP_REG(DPAUX_DP_AUX_SINKSTAT_HI);
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DUMP_REG(DPAUX_HPD_CONFIG);
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DUMP_REG(DPAUX_HPD_IRQ_CONFIG);
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DUMP_REG(DPAUX_DP_AUX_CONFIG);
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DUMP_REG(DPAUX_HYBRID_PADCTL);
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DUMP_REG(DPAUX_HYBRID_SPARE);
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DUMP_REG(DPAUX_SCRATCH_REG0);
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DUMP_REG(DPAUX_SCRATCH_REG1);
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DUMP_REG(DPAUX_SCRATCH_REG2);
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#undef DUMP_REG
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return 0;
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}
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static struct drm_info_list debugfs_files[] = {
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{ "regs", tegra_dpaux_show_regs, 0, NULL },
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};
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static int tegra_dpaux_debugfs_init(struct tegra_dpaux *dpaux,
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struct drm_minor *minor)
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{
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unsigned int i;
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int err;
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dpaux->debugfs = debugfs_create_dir("dpaux", minor->debugfs_root);
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if (!dpaux->debugfs)
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return -ENOMEM;
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dpaux->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
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GFP_KERNEL);
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if (!dpaux->debugfs_files) {
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err = -ENOMEM;
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goto remove;
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}
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for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
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dpaux->debugfs_files[i].data = dpaux;
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err = drm_debugfs_create_files(dpaux->debugfs_files,
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ARRAY_SIZE(debugfs_files),
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dpaux->debugfs, minor);
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if (err < 0)
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goto free;
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dpaux->minor = minor;
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return 0;
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free:
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kfree(dpaux->debugfs_files);
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dpaux->debugfs_files = NULL;
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remove:
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debugfs_remove(dpaux->debugfs);
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dpaux->debugfs = NULL;
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return err;
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}
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static int tegra_dpaux_debugfs_exit(struct tegra_dpaux *dpaux)
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{
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drm_debugfs_remove_files(dpaux->debugfs_files, ARRAY_SIZE(debugfs_files),
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dpaux->minor);
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dpaux->minor = NULL;
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kfree(dpaux->debugfs_files);
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dpaux->debugfs_files = NULL;
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debugfs_remove(dpaux->debugfs);
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dpaux->debugfs = NULL;
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return 0;
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}
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static int tegra_dpaux_init(struct host1x_client *client)
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{
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struct tegra_drm *tegra = dev_get_drvdata(client->parent);
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struct tegra_dpaux *dpaux = host1x_client_to_dpaux(client);
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int err;
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if (IS_ENABLED(CONFIG_DEBUG_FS)) {
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err = tegra_dpaux_debugfs_init(dpaux, tegra->drm->primary);
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if (err < 0)
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dev_err(dpaux->dev, "debugfs setup failed: %d\n", err);
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return err;
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}
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return 0;
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}
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static int tegra_dpaux_exit(struct host1x_client *client)
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{
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struct tegra_dpaux *dpaux = host1x_client_to_dpaux(client);
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int err;
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if (IS_ENABLED(CONFIG_DEBUG_FS)) {
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err = tegra_dpaux_debugfs_exit(dpaux);
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if (err < 0)
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dev_err(dpaux->dev,
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"debugfs cleanup failed: %d\n", err);
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return err;
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}
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return 0;
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}
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static const struct host1x_client_ops dpaux_client_ops = {
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.init = tegra_dpaux_init,
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.exit = tegra_dpaux_exit,
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};
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static int tegra_dpaux_probe(struct platform_device *pdev)
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{
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struct tegra_dpaux *dpaux;
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struct host1x_client *client;
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struct resource *regs;
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unsigned long value;
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int err;
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client = drm_host1x_get_client(&pdev->dev);
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if (client) {
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dpaux = host1x_client_to_dpaux(client);
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} else {
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dpaux = kzalloc(sizeof(*dpaux), GFP_KERNEL);
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if (!dpaux)
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return -ENOMEM;
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INIT_LIST_HEAD(&dpaux->client.list);
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dpaux->client.ops = &dpaux_client_ops;
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dpaux->client.dev = &pdev->dev;
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}
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err = drm_host1x_register(&dpaux->client);
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if (err < 0) {
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dev_err(&pdev->dev, "failed to register host1x client: %d\n",
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err);
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return err;
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}
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init_completion(&dpaux->complete);
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INIT_LIST_HEAD(&dpaux->list);
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dpaux->dev = &pdev->dev;
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regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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dpaux->regs = devm_ioremap_resource(&pdev->dev, regs);
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if (IS_ERR(dpaux->regs))
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return PTR_ERR(dpaux->regs);
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dpaux->irq = platform_get_irq(pdev, 0);
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if (dpaux->irq < 0) {
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dev_err(&pdev->dev, "failed to get IRQ\n");
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return -ENXIO;
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}
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dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux");
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if (IS_ERR(dpaux->rst))
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return PTR_ERR(dpaux->rst);
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dpaux->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(dpaux->clk))
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return PTR_ERR(dpaux->clk);
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dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent");
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if (IS_ERR(dpaux->clk_parent))
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return PTR_ERR(dpaux->clk_parent);
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err = clk_prepare_enable(dpaux->clk_parent);
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if (err < 0)
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return err;
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err = clk_set_rate(dpaux->clk_parent, 270000000);
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if (err < 0) {
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dev_err(&pdev->dev, "failed to set clock to 270 MHz: %d\n",
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err);
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return err;
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}
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err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0,
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dev_name(dpaux->dev), dpaux);
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if (err < 0) {
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dev_err(dpaux->dev, "failed to request IRQ#%u: %d\n",
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dpaux->irq, err);
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return err;
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}
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disable_irq(dpaux->irq);
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dpaux->aux.transfer = tegra_dpaux_transfer;
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dpaux->aux.dev = &pdev->dev;
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|
|
err = drm_dp_aux_register_i2c_bus(&dpaux->aux);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
/* enable and clear all interrupts */
|
|
value = DPAUX_INTR_AUX_DONE | DPAUX_INTR_IRQ_EVENT;
|
|
tegra_dpaux_writel(dpaux, value, DPAUX_INTR_EN_AUX);
|
|
tegra_dpaux_writel(dpaux, 0xffffffff, DPAUX_INTR_AUX);
|
|
|
|
mutex_lock(&dpaux_lock);
|
|
list_add_tail(&dpaux->list, &dpaux_list);
|
|
mutex_unlock(&dpaux_lock);
|
|
|
|
platform_set_drvdata(pdev, dpaux);
|
|
dpaux->client.driver_probed = 1;
|
|
dev_info(&pdev->dev, "initialized\n");
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_dpaux_remove(struct platform_device *pdev)
|
|
{
|
|
struct tegra_dpaux *dpaux = platform_get_drvdata(pdev);
|
|
|
|
drm_dp_aux_unregister_i2c_bus(&dpaux->aux);
|
|
|
|
mutex_lock(&dpaux_lock);
|
|
list_del(&dpaux->list);
|
|
mutex_unlock(&dpaux_lock);
|
|
|
|
clk_disable_unprepare(dpaux->clk_parent);
|
|
reset_control_assert(dpaux->rst);
|
|
clk_disable_unprepare(dpaux->clk);
|
|
|
|
kfree(dpaux);
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id tegra_dpaux_of_match[] = {
|
|
{ .compatible = "nvidia,tegra124-dpaux", },
|
|
{ },
|
|
};
|
|
|
|
struct platform_driver tegra_dpaux_driver = {
|
|
.driver = {
|
|
.name = "tegra-dpaux",
|
|
.of_match_table = tegra_dpaux_of_match,
|
|
},
|
|
.probe = tegra_dpaux_probe,
|
|
.remove = tegra_dpaux_remove,
|
|
};
|
|
|
|
struct tegra_dpaux *tegra_dpaux_find_by_of_node(struct device_node *np)
|
|
{
|
|
struct tegra_dpaux *dpaux;
|
|
|
|
mutex_lock(&dpaux_lock);
|
|
|
|
list_for_each_entry(dpaux, &dpaux_list, list)
|
|
if (np == dpaux->dev->of_node) {
|
|
mutex_unlock(&dpaux_lock);
|
|
return dpaux;
|
|
}
|
|
|
|
mutex_unlock(&dpaux_lock);
|
|
|
|
return NULL;
|
|
}
|
|
|
|
int tegra_dpaux_attach(struct tegra_dpaux *dpaux, struct tegra_output *output)
|
|
{
|
|
unsigned long timeout;
|
|
|
|
output->connector.polled = DRM_CONNECTOR_POLL_HPD;
|
|
output->ddc = &dpaux->aux.ddc;
|
|
dpaux->output = output;
|
|
|
|
timeout = jiffies + msecs_to_jiffies(250);
|
|
while (time_before(jiffies, timeout)) {
|
|
enum drm_connector_status status;
|
|
|
|
status = tegra_dpaux_detect(dpaux);
|
|
if (status == connector_status_connected) {
|
|
enable_irq(dpaux->irq);
|
|
return 0;
|
|
}
|
|
|
|
usleep_range(1000, 2000);
|
|
}
|
|
|
|
return -ETIMEDOUT;
|
|
}
|
|
|
|
int tegra_dpaux_detach(struct tegra_dpaux *dpaux)
|
|
{
|
|
unsigned long timeout;
|
|
|
|
disable_irq(dpaux->irq);
|
|
|
|
timeout = jiffies + msecs_to_jiffies(250);
|
|
while (time_before(jiffies, timeout)) {
|
|
enum drm_connector_status status;
|
|
|
|
status = tegra_dpaux_detect(dpaux);
|
|
if (status == connector_status_disconnected) {
|
|
dpaux->output = NULL;
|
|
return 0;
|
|
}
|
|
|
|
usleep_range(1000, 2000);
|
|
}
|
|
|
|
return -ETIMEDOUT;
|
|
}
|
|
|
|
enum drm_connector_status tegra_dpaux_detect(struct tegra_dpaux *dpaux)
|
|
{
|
|
/* nyan doesn't support DP, so for eDP panel, it's always connected. */
|
|
return connector_status_connected;
|
|
}
|
|
|
|
int tegra_dpaux_enable(struct tegra_dpaux *dpaux)
|
|
{
|
|
unsigned long value;
|
|
int err;
|
|
|
|
if (dpaux->enabled)
|
|
return 0;
|
|
|
|
tegra_output_panel_prepare(dpaux->output);
|
|
tegra_unpowergate_partition(TEGRA_POWERGATE_SOR);
|
|
err = clk_prepare_enable(dpaux->clk);
|
|
if (err < 0) {
|
|
dev_info(dpaux->dev, "enable dpaux clock failed: %d\n", err);
|
|
tegra_powergate_partition(TEGRA_POWERGATE_SOR);
|
|
return err;
|
|
}
|
|
reset_control_deassert(dpaux->rst);
|
|
udelay(10);
|
|
|
|
/* enable and clear all interrupts */
|
|
value = DPAUX_INTR_AUX_DONE | DPAUX_INTR_IRQ_EVENT;
|
|
tegra_dpaux_writel(dpaux, value, DPAUX_INTR_EN_AUX);
|
|
tegra_dpaux_writel(dpaux, 0xffffffff, DPAUX_INTR_AUX);
|
|
|
|
value = DPAUX_HYBRID_PADCTL_AUX_CMH(2) |
|
|
DPAUX_HYBRID_PADCTL_AUX_DRVZ(4) |
|
|
DPAUX_HYBRID_PADCTL_AUX_DRVI(0x18) |
|
|
DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV |
|
|
DPAUX_HYBRID_PADCTL_MODE_AUX;
|
|
tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL);
|
|
|
|
value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
|
|
value &= ~DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
|
|
tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
|
|
|
|
dpaux->enabled = true;
|
|
return 0;
|
|
}
|
|
|
|
int tegra_dpaux_disable(struct tegra_dpaux *dpaux)
|
|
{
|
|
unsigned long value;
|
|
|
|
if (!dpaux->enabled)
|
|
return 0;
|
|
|
|
/* disable and clear all interrupts */
|
|
tegra_dpaux_writel(dpaux, 0, DPAUX_INTR_EN_AUX);
|
|
tegra_dpaux_writel(dpaux, 0xffffffff, DPAUX_INTR_AUX);
|
|
|
|
value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
|
|
value |= DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
|
|
tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
|
|
|
|
tegra_powergate_partition(TEGRA_POWERGATE_SOR);
|
|
reset_control_assert(dpaux->rst);
|
|
udelay(10);
|
|
clk_disable_unprepare(dpaux->clk);
|
|
|
|
tegra_output_panel_unprepare(dpaux->output);
|
|
dpaux->enabled = false;
|
|
return 0;
|
|
}
|