140 lines
3.4 KiB
C
140 lines
3.4 KiB
C
/*
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* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/cpufreq.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/suspend.h>
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#include <linux/cpu.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include "tegra-cpufreq.h"
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static struct cpufreq_frequency_table freq_table[] = {
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{ .frequency = 216000 },
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{ .frequency = 312000 },
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{ .frequency = 456000 },
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{ .frequency = 608000 },
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{ .frequency = 760000 },
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{ .frequency = 816000 },
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{ .frequency = 912000 },
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{ .frequency = 1000000 },
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{ .frequency = CPUFREQ_TABLE_END },
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};
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static struct clk *cpu_clk;
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static struct clk *pll_x_clk;
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static struct clk *pll_p_clk;
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static struct clk *emc_clk;
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static void tegra20_emc_clk_set_rate(unsigned long rate)
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{
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if (rate >= 816000)
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clk_set_rate(emc_clk, 600000000); /* cpu 816 MHz, emc max */
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else if (rate >= 456000)
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clk_set_rate(emc_clk, 300000000); /* cpu 456 MHz, emc 150Mhz */
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else
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clk_set_rate(emc_clk, 100000000); /* emc 50Mhz */
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}
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static int tegra20_cpu_clk_set_rate(unsigned long rate)
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{
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int ret;
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/*
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* Take an extra reference to the main pll so it doesn't turn
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* off when we move the cpu off of it
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*/
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clk_prepare_enable(pll_x_clk);
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ret = clk_set_parent(cpu_clk, pll_p_clk);
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if (ret) {
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pr_err("Failed to switch cpu to clock pll_p\n");
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goto out;
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}
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if (rate == clk_get_rate(pll_p_clk))
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goto out;
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ret = clk_set_rate(pll_x_clk, rate);
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if (ret) {
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pr_err("Failed to change pll_x to %lu\n", rate);
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goto out;
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}
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ret = clk_set_parent(cpu_clk, pll_x_clk);
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if (ret) {
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pr_err("Failed to switch cpu to clock pll_x\n");
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goto out;
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}
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out:
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clk_disable_unprepare(pll_x_clk);
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return ret;
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}
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static void tegra20_cpufreq_clk_init(void)
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{
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clk_prepare_enable(emc_clk);
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clk_prepare_enable(cpu_clk);
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}
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static void tegra20_cpufreq_clk_exit(void)
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{
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clk_disable_unprepare(cpu_clk);
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clk_disable_unprepare(emc_clk);
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}
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static const struct tegra_cpufreq_config tegra20_cpufreq_config = {
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.emc_clk_set_rate = tegra20_emc_clk_set_rate,
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.cpu_clk_set_rate = tegra20_cpu_clk_set_rate,
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.cpufreq_clk_init = tegra20_cpufreq_clk_init,
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.cpufreq_clk_exit = tegra20_cpufreq_clk_exit,
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};
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int tegra20_cpufreq_init(struct tegra_cpufreq_data *data,
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const struct tegra_cpufreq_config **soc_config)
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{
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cpu_clk = clk_get_sys(NULL, "cclk");
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if (IS_ERR(cpu_clk))
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return PTR_ERR(cpu_clk);
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pll_x_clk = clk_get_sys(NULL, "pll_x");
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if (IS_ERR(pll_x_clk))
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return PTR_ERR(pll_x_clk);
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pll_p_clk = clk_get_sys(NULL, "pll_p");
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if (IS_ERR(pll_p_clk))
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return PTR_ERR(pll_p_clk);
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emc_clk = clk_get_sys("cpu", "emc");
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if (IS_ERR(emc_clk)) {
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clk_put(cpu_clk);
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return PTR_ERR(emc_clk);
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}
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data->cpu_clk = cpu_clk;
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data->freq_table = freq_table;
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data->suspend_index = 0;
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*soc_config = &tegra20_cpufreq_config;
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return 0;
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}
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EXPORT_SYMBOL(tegra20_cpufreq_init);
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