243 lines
10 KiB
Plaintext
243 lines
10 KiB
Plaintext
Tegra124 External Memory Controller
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Properties:
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- compatible : Should contain "nvidia,tegra124-emc".
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- reg : Should contain the register range of the device
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- #address-cells : Should be 1
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- #size-cells : Should be 0
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- nvidia,mc : phandle to the mc bus connected to EMC.
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- clocks : phandle to EMC, EMC shared bus override, and all parent clocks.
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- clock-names : name of each clock.
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- nvidia,pmc : phandle to the PMC syscon node.
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- max-clock-frequency : optional, specifies the maximum EMC rate in kHz.
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Child device nodes describe the memory settings for different configurations and
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clock rates.
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Example:
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memory-controller@7001b000 {
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compatible = "nvidia,tegra124-emc";
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reg = <0x7001b000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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nvidia,mc = <&mc>;
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nvidia,pmc = <&pmc>;
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clocks = <&tegra_car TEGRA124_CLK_EMC>,
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<&tegra_car TEGRA124_CLK_PLL_M>,
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<&tegra_car TEGRA124_CLK_PLL_C>,
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<&tegra_car TEGRA124_CLK_PLL_P>,
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<&tegra_car TEGRA124_CLK_CLK_M>,
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<&tegra_car TEGRA124_CLK_PLL_M_UD>,
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<&tegra_car TEGRA124_CLK_PLL_C2>,
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<&tegra_car TEGRA124_CLK_PLL_C3>,
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<&tegra_car TEGRA124_CLK_PLL_C_UD>,
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<&tegra_car TEGRA124_CLK_OVERRIDE_EMC>;
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clock-names = "emc", "pll_m", "pll_c", "pll_p", "clk_m",
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"pll_m_ud", "pll_c2", "pll_c3", "pll_c_ud",
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"emc_override";
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};
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External Memory Controller ram-code table
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If the emc node has the nvidia,ram-code property present, then the next level
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of nodes below the emc table are used to specify which settings apply for
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which ram-code settings.
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If the emc node lacks the nvidia,use-ram-code property, this level is omitted
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and the tables are stored directly under the emc node (see below).
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Properties:
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- name : Should be emc-tables
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- nvidia,ram-code : the binary representation of the ram-code board strappings
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for which this node (and children) are valid.
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External Memory Controller configuration table
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This is a table containing the EMC register settings for the various operating
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speeds of the memory controller. They are always located as subnodes of the emc
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controller node.
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Properties:
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- compatible : Should contain "nvidia,tegra12-emc-table".
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- clock-frequency : the clock frequency for the EMC at which this
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table should be used (in KHz).
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- nvidia,revision : The revision of emc table
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- nvidia,emc-min-mv : min voltage
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- nvidia,gk20a-min-mv : GPU min voltage
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- nvidia,emc-src-sel-reg : CLK_SOURCE_EMC
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- nvidia,burst-regs-num : number of emc burst regs
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- nvidia,burst-up-down-regs-num : number of up_down regs
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- nvidia,emc-zcal-wait-cnt : EMC_ZCAL_WAIT_CNT after clock change
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- nvidia,emc-acal-interval : EMC_AUTO_CAL_INTERVAL
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- nvidia,emc-ctt-term-ctrl : EMC_CTT_TERM_CTRL
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- nvidia,emc-cfg : EMC_CFG
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- nvidia,emc-cfg-2 : EMC_CFG_2
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- nvidia,emc-sel-dpd-ctrl : EMC_SEL_DPD_CTRL
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- nvidia,emc-cfg-dig-dll : EMC_CFG_DIG_DLL
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- nvidia,emc-bgbias-ctl0 : EMC_BGBIAS_CTL0
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- nvidia,emc-auto-cal-config2 = EMC_AUTO_CAL_CONFIG2;
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- nvidia,emc-auto-cal-config3 = EMC_AUTO_CAL_CONFIG3;
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- nvidia,emc-auto-cal-config = EMC_AUTO_CAL_CONFIG;
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- nvidia,emc-mode-reset : Mode Register 0
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- nvidia,emc-mode-1 : Mode Register 1
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- nvidia,emc-mode-2 : Mode Register 2
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- nvidia,emc-mode-4 : Mode Register 4
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- nvidia,emc-latency : expected dvfs latency (ns)
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- nvidia,emc-registers : a 164 word array of EMC/MC registers to be
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programmed for operation at the 'clock-frequency' setting.
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The order and contents of the registers are:
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EMC_RC, EMC_RFC, EMC_RFC_SLR, EMC_RAS, EMC_RP, EMC_R2W, EMC_W2R,
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EMC_R2P, EMC_W2P, EMC_RD_RCD, EMC_WR_RCD, EMC_RRD, EMC_REXT, EMC_WEXT,
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EMC_WDV, EMC_WDV_MASK, EMC_QUSE, EMC_QUSE_WIDTH, EMC_IBDLY, EMC_EINPUT,
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EMC_EINPUT_DURATION, EMC_PUTERM_EXTRA, EMC_PUTERM_WIDTH,
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EMC_PUTERM_ADJ, EMC_CDB_CNTL_1, EMC_CDB_CNTL_2, EMC_CDB_CNTL_3,
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EMC_QSAFE, EMC_RDV, EMC_RDV_MASK, EMC_REFRESH, EMC_BURST_REFRESH_NUM,
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EMC_PRE_REFRESH_REQ_CNT, EMC_PDEX2WR, EMC_PDEX2RD, EMC_PCHG2PDEN,
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EMC_ACT2PDEN, EMC_AR2PDEN, EMC_RW2PDEN, EMC_TXSR, EMC_TXSRDLL,
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EMC_TCKE, EMC_TCKESR, EMC_TPD, EMC_TFAW, EMC_TRPAB, EMC_TCLKSTABLE,
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EMC_TCLKSTOP, EMC_TREFBW, EMC_FBIO_CFG6, EMC_ODT_WRITE, EMC_ODT_READ,
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EMC_FBIO_CFG5, EMC_CFG_DIG_DLL, EMC_CFG_DIG_DLL_PERIOD,
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EMC_DLL_XFORM_DQS0, EMC_DLL_XFORM_DQS1, EMC_DLL_XFORM_DQS2,
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EMC_DLL_XFORM_DQS3, EMC_DLL_XFORM_DQS4, EMC_DLL_XFORM_DQS5,
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EMC_DLL_XFORM_DQS6, EMC_DLL_XFORM_DQS7, EMC_DLL_XFORM_DQS8,
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EMC_DLL_XFORM_DQS9, EMC_DLL_XFORM_DQS10, EMC_DLL_XFORM_DQS11,
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EMC_DLL_XFORM_DQS12, EMC_DLL_XFORM_DQS13, EMC_DLL_XFORM_DQS14,
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EMC_DLL_XFORM_DQS15, EMC_DLL_XFORM_QUSE0, EMC_DLL_XFORM_QUSE1,
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EMC_DLL_XFORM_QUSE2, EMC_DLL_XFORM_QUSE3, EMC_DLL_XFORM_QUSE4,
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EMC_DLL_XFORM_QUSE5, EMC_DLL_XFORM_QUSE6, EMC_DLL_XFORM_QUSE7,
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EMC_DLL_XFORM_ADDR0, EMC_DLL_XFORM_ADDR1, EMC_DLL_XFORM_ADDR2,
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EMC_DLL_XFORM_ADDR3, EMC_DLL_XFORM_ADDR4, EMC_DLL_XFORM_ADDR5,
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EMC_DLL_XFORM_QUSE8, EMC_DLL_XFORM_QUSE9, EMC_DLL_XFORM_QUSE10,
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EMC_DLL_XFORM_QUSE11, EMC_DLL_XFORM_QUSE12, EMC_DLL_XFORM_QUSE13,
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EMC_DLL_XFORM_QUSE14, EMC_DLL_XFORM_QUSE15, EMC_DLI_TRIM_TXDQS0,
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EMC_DLI_TRIM_TXDQS1, EMC_DLI_TRIM_TXDQS2, EMC_DLI_TRIM_TXDQS3,
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EMC_DLI_TRIM_TXDQS4, EMC_DLI_TRIM_TXDQS5, EMC_DLI_TRIM_TXDQS6,
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EMC_DLI_TRIM_TXDQS7, EMC_DLI_TRIM_TXDQS8, EMC_DLI_TRIM_TXDQS9,
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EMC_DLI_TRIM_TXDQS10, EMC_DLI_TRIM_TXDQS11, EMC_DLI_TRIM_TXDQS12,
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EMC_DLI_TRIM_TXDQS13, EMC_DLI_TRIM_TXDQS14, EMC_DLI_TRIM_TXDQS15,
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EMC_DLL_XFORM_DQ0, EMC_DLL_XFORM_DQ1, EMC_DLL_XFORM_DQ2,
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EMC_DLL_XFORM_DQ3, EMC_DLL_XFORM_DQ4, EMC_DLL_XFORM_DQ5,
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EMC_DLL_XFORM_DQ6, EMC_DLL_XFORM_DQ7, EMC_XM2CMDPADCTRL,
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EMC_XM2CMDPADCTRL4, EMC_XM2CMDPADCTRL5, EMC_XM2DQSPADCTRL2,
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EMC_XM2DQPADCTRL2, EMC_XM2DQPADCTRL3, EMC_XM2CLKPADCTRL,
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EMC_XM2CLKPADCTRL2, EMC_XM2COMPPADCTRL, EMC_XM2VTTGENPADCTRL,
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EMC_XM2VTTGENPADCTRL2, EMC_XM2VTTGENPADCTRL3, EMC_XM2DQSPADCTRL3,
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EMC_XM2DQSPADCTRL4, EMC_XM2DQSPADCTRL5, EMC_XM2DQSPADCTRL6,
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EMC_DSR_VTTGEN_DRV, EMC_TXDSRVTTGEN, EMC_FBIO_SPARE, EMC_ZCAL_INTERVAL,
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EMC_ZCAL_WAIT_CNT, EMC_MRS_WAIT_CNT, EMC_MRS_WAIT_CNT2,
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EMC_CTT, EMC_CTT_DURATION, EMC_CFG_PIPE, EMC_DYN_SELF_REF_CONTROL,
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EMC_QPOP, MC_EMEM_ARB_CFG, MC_EMEM_ARB_OUTSTANDING_REQ,
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MC_EMEM_ARB_TIMING_RCD, MC_EMEM_ARB_TIMING_RP, MC_EMEM_ARB_TIMING_RC,
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MC_EMEM_ARB_TIMING_RAS, MC_EMEM_ARB_TIMING_FAW, MC_EMEM_ARB_TIMING_RRD,
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MC_EMEM_ARB_TIMING_RAP2PRE, MC_EMEM_ARB_TIMING_WAP2PRE,
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MC_EMEM_ARB_TIMING_R2R, MC_EMEM_ARB_TIMING_W2W, MC_EMEM_ARB_TIMING_R2W,
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MC_EMEM_ARB_TIMING_W2R, MC_EMEM_ARB_DA_TURNS, MC_EMEM_ARB_DA_COVERS,
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MC_EMEM_ARB_MISC0, MC_EMEM_ARB_RING1_THROTTLE
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- nvidia,emc-burst-up-down-regs : a 31 word array of EMC/MC registers to be
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programmed for operation at the 'clock-frequency' setting.
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The order and contents of the registers are:
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MC_MLL_MPCORER_PTSA_RATE, MC_PTSA_GRANT_DECREMENT,
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MC_LATENCY_ALLOWANCE_XUSB_0, MC_LATENCY_ALLOWANCE_XUSB_1,
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MC_LATENCY_ALLOWANCE_TSEC_0, MC_LATENCY_ALLOWANCE_SDMMCA_0,
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MC_LATENCY_ALLOWANCE_SDMMCAA_0, MC_LATENCY_ALLOWANCE_SDMMC_0,
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MC_LATENCY_ALLOWANCE_SDMMCAB_0, MC_LATENCY_ALLOWANCE_PPCS_0,
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MC_LATENCY_ALLOWANCE_PPCS_1, MC_LATENCY_ALLOWANCE_MPCORE_0,
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MC_LATENCY_ALLOWANCE_MPCORELP_0, MC_LATENCY_ALLOWANCE_HC_0,
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MC_LATENCY_ALLOWANCE_HC_1, MC_LATENCY_ALLOWANCE_AVPC_0,
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MC_LATENCY_ALLOWANCE_GPU_0, MC_LATENCY_ALLOWANCE_MSENC_0,
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MC_LATENCY_ALLOWANCE_HDA_0, MC_LATENCY_ALLOWANCE_VIC_0,
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MC_LATENCY_ALLOWANCE_VI2_0, MC_LATENCY_ALLOWANCE_ISP2_0,
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MC_LATENCY_ALLOWANCE_ISP2_1, MC_LATENCY_ALLOWANCE_ISP2B_0,
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MC_LATENCY_ALLOWANCE_ISP2B_1, MC_LATENCY_ALLOWANCE_VDE_0,
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MC_LATENCY_ALLOWANCE_VDE_1, MC_LATENCY_ALLOWANCE_VDE_2,
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MC_LATENCY_ALLOWANCE_VDE_3, MC_LATENCY_ALLOWANCE_SATA_0,
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MC_LATENCY_ALLOWANCE_AFI_0
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Example:
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emc-table@12750 {
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compatible = "nvidia,tegra12-emc-table";
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reg = <0>;
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clock-frequency = <0>;
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nvidia,revision = <0>;
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nvidia,emc-min-mv = <0>;
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nvidia,gk20a-min-mv = <0>;
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nvidia,source = "pllp_out0";
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nvidia,src-sel-reg = <0>;
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nvidia,burst-regs-num = <0>;
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nvidia,burst-up-down-regs-num = <0>;
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nvidia,emc-registers = <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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0 0 0 0>;
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nvidia,emc-burst-up-down-regs = <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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>;
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nvidia,emc-zcal-cnt-long = <0>;
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nvidia,emc-acal-interval = <0>;
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nvidia,emc-ctt-term-ctrl = <0>;
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nvidia,emc-cfg = <0>;
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nvidia,emc-cfg-2 = <0>;
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nvidia,emc-sel-dpd-ctrl = <0>;
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nvidia,emc-cfg-dig-dll = <0>;
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nvidia,emc-bgbias-ctl0 = <0>;
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nvidia,emc-auto-cal-config2 = <0>;
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nvidia,emc-auto-cal-config3 = <0>;
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nvidia,emc-auto-cal-config = <0>;
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nvidia,emc-mode-reset = <0>;
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nvidia,emc-mode-1 = <0>;
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nvidia,emc-mode-2 = <0>;
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nvidia,emc-mode-4 = <0>;
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nvidia,emc-clock-latency-change = <0>;
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};
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emc-table@20400 {
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compatible = "nvidia,tegra12-emc-table";
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reg = <0>;
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clock-frequency = <0>;
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nvidia,revision = <0>;
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nvidia,emc-min-mv = <0>;
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nvidia,gk20a-min-mv = <0>;
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nvidia,source = "pllp_out0";
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nvidia,src-sel-reg = <0>;
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nvidia,burst-regs-num = <0>;
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nvidia,burst-up-down-regs-num = <0>;
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nvidia,emc-registers = <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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0 0 0 0>;
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nvidia,emc-burst-up-down-regs = <0 0 0 0 0 0 0 0 0 0 0
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0 0 0 0 0 0 0 0 0 0 0 0
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0 0 0 0 0 0 0 0>;
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nvidia,emc-zcal-cnt-long = <0>;
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nvidia,emc-acal-interval = <0>;
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nvidia,emc-ctt-term-ctrl = <0>;
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nvidia,emc-cfg = <0>;
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nvidia,emc-cfg-2 = <0>;
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nvidia,emc-sel-dpd-ctrl = <0>;
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nvidia,emc-cfg-dig-dll = <0>;
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nvidia,emc-bgbias-ctl0 = <0>;
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nvidia,emc-auto-cal-config2 = <0>;
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nvidia,emc-auto-cal-config3 = <0>;
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nvidia,emc-auto-cal-config = <0>;
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nvidia,emc-mode-reset = <0>;
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nvidia,emc-mode-1 = <0>;
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nvidia,emc-mode-2 = <0>;
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nvidia,emc-mode-4 = <0>;
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nvidia,emc-clock-latency-change = <0>;
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};
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