470 lines
11 KiB
C
470 lines
11 KiB
C
/*
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* Copyright 2013 Emilio López
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*
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* Emilio López <emilio@elopez.com.ar>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/clk/sunxi.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include "clk-factors.h"
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static DEFINE_SPINLOCK(clk_lock);
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/**
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* sunxi_osc_clk_setup() - Setup function for gatable oscillator
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*/
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#define SUNXI_OSC24M_GATE 0
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static void __init sunxi_osc_clk_setup(struct device_node *node)
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{
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struct clk *clk;
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struct clk_fixed_rate *fixed;
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struct clk_gate *gate;
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const char *clk_name = node->name;
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u32 rate;
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/* allocate fixed-rate and gate clock structs */
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fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL);
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if (!fixed)
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return;
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gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
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if (!gate) {
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kfree(fixed);
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return;
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}
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if (of_property_read_u32(node, "clock-frequency", &rate))
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return;
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/* set up gate and fixed rate properties */
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gate->reg = of_iomap(node, 0);
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gate->bit_idx = SUNXI_OSC24M_GATE;
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gate->lock = &clk_lock;
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fixed->fixed_rate = rate;
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clk = clk_register_composite(NULL, clk_name,
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NULL, 0,
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NULL, NULL,
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&fixed->hw, &clk_fixed_rate_ops,
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&gate->hw, &clk_gate_ops,
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CLK_IS_ROOT);
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if (clk) {
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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clk_register_clkdev(clk, clk_name, NULL);
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}
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}
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/**
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* sunxi_get_pll1_factors() - calculates n, k, m, p factors for PLL1
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* PLL1 rate is calculated as follows
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* rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
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* parent_rate is always 24Mhz
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*/
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static void sunxi_get_pll1_factors(u32 *freq, u32 parent_rate,
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u8 *n, u8 *k, u8 *m, u8 *p)
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{
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u8 div;
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/* Normalize value to a 6M multiple */
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div = *freq / 6000000;
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*freq = 6000000 * div;
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/* we were called to round the frequency, we can now return */
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if (n == NULL)
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return;
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/* m is always zero for pll1 */
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*m = 0;
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/* k is 1 only on these cases */
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if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000)
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*k = 1;
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else
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*k = 0;
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/* p will be 3 for divs under 10 */
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if (div < 10)
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*p = 3;
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/* p will be 2 for divs between 10 - 20 and odd divs under 32 */
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else if (div < 20 || (div < 32 && (div & 1)))
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*p = 2;
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/* p will be 1 for even divs under 32, divs under 40 and odd pairs
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* of divs between 40-62 */
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else if (div < 40 || (div < 64 && (div & 2)))
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*p = 1;
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/* any other entries have p = 0 */
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else
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*p = 0;
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/* calculate a suitable n based on k and p */
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div <<= *p;
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div /= (*k + 1);
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*n = div / 4;
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}
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/**
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* sunxi_get_apb1_factors() - calculates m, p factors for APB1
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* APB1 rate is calculated as follows
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* rate = (parent_rate >> p) / (m + 1);
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*/
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static void sunxi_get_apb1_factors(u32 *freq, u32 parent_rate,
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u8 *n, u8 *k, u8 *m, u8 *p)
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{
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u8 calcm, calcp;
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if (parent_rate < *freq)
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*freq = parent_rate;
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parent_rate = (parent_rate + (*freq - 1)) / *freq;
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/* Invalid rate! */
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if (parent_rate > 32)
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return;
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if (parent_rate <= 4)
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calcp = 0;
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else if (parent_rate <= 8)
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calcp = 1;
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else if (parent_rate <= 16)
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calcp = 2;
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else
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calcp = 3;
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calcm = (parent_rate >> calcp) - 1;
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*freq = (parent_rate >> calcp) / (calcm + 1);
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/* we were called to round the frequency, we can now return */
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if (n == NULL)
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return;
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*m = calcm;
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*p = calcp;
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}
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/**
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* sunxi_factors_clk_setup() - Setup function for factor clocks
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*/
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struct factors_data {
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struct clk_factors_config *table;
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void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p);
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};
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static struct clk_factors_config pll1_config = {
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.nshift = 8,
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.nwidth = 5,
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.kshift = 4,
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.kwidth = 2,
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.mshift = 0,
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.mwidth = 2,
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.pshift = 16,
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.pwidth = 2,
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};
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static struct clk_factors_config apb1_config = {
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.mshift = 0,
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.mwidth = 5,
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.pshift = 16,
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.pwidth = 2,
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};
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static const __initconst struct factors_data pll1_data = {
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.table = &pll1_config,
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.getter = sunxi_get_pll1_factors,
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};
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static const __initconst struct factors_data apb1_data = {
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.table = &apb1_config,
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.getter = sunxi_get_apb1_factors,
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};
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static void __init sunxi_factors_clk_setup(struct device_node *node,
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struct factors_data *data)
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{
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struct clk *clk;
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const char *clk_name = node->name;
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const char *parent;
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void *reg;
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reg = of_iomap(node, 0);
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parent = of_clk_get_parent_name(node, 0);
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clk = clk_register_factors(NULL, clk_name, parent, 0, reg,
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data->table, data->getter, &clk_lock);
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if (clk) {
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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clk_register_clkdev(clk, clk_name, NULL);
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}
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}
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/**
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* sunxi_mux_clk_setup() - Setup function for muxes
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*/
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#define SUNXI_MUX_GATE_WIDTH 2
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struct mux_data {
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u8 shift;
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};
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static const __initconst struct mux_data cpu_data = {
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.shift = 16,
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};
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static const __initconst struct mux_data apb1_mux_data = {
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.shift = 24,
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};
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static void __init sunxi_mux_clk_setup(struct device_node *node,
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struct mux_data *data)
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{
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struct clk *clk;
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const char *clk_name = node->name;
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const char *parents[5];
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void *reg;
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int i = 0;
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reg = of_iomap(node, 0);
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while (i < 5 && (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
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i++;
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clk = clk_register_mux(NULL, clk_name, parents, i, 0, reg,
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data->shift, SUNXI_MUX_GATE_WIDTH,
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0, &clk_lock);
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if (clk) {
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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clk_register_clkdev(clk, clk_name, NULL);
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}
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}
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/**
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* sunxi_divider_clk_setup() - Setup function for simple divider clocks
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*/
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#define SUNXI_DIVISOR_WIDTH 2
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struct div_data {
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u8 shift;
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u8 pow;
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};
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static const __initconst struct div_data axi_data = {
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.shift = 0,
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.pow = 0,
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};
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static const __initconst struct div_data ahb_data = {
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.shift = 4,
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.pow = 1,
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};
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static const __initconst struct div_data apb0_data = {
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.shift = 8,
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.pow = 1,
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};
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static void __init sunxi_divider_clk_setup(struct device_node *node,
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struct div_data *data)
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{
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struct clk *clk;
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const char *clk_name = node->name;
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const char *clk_parent;
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void *reg;
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reg = of_iomap(node, 0);
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clk_parent = of_clk_get_parent_name(node, 0);
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clk = clk_register_divider(NULL, clk_name, clk_parent, 0,
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reg, data->shift, SUNXI_DIVISOR_WIDTH,
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data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
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&clk_lock);
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if (clk) {
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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clk_register_clkdev(clk, clk_name, NULL);
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}
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}
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/**
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* sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
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*/
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#define SUNXI_GATES_MAX_SIZE 64
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struct gates_data {
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DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
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};
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static const __initconst struct gates_data axi_gates_data = {
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.mask = {1},
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};
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static const __initconst struct gates_data ahb_gates_data = {
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.mask = {0x7F77FFF, 0x14FB3F},
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};
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static const __initconst struct gates_data apb0_gates_data = {
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.mask = {0x4EF},
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};
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static const __initconst struct gates_data apb1_gates_data = {
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.mask = {0xFF00F7},
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};
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static void __init sunxi_gates_clk_setup(struct device_node *node,
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struct gates_data *data)
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{
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struct clk_onecell_data *clk_data;
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const char *clk_parent;
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const char *clk_name;
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void *reg;
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int qty;
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int i = 0;
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int j = 0;
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int ignore;
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reg = of_iomap(node, 0);
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clk_parent = of_clk_get_parent_name(node, 0);
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/* Worst-case size approximation and memory allocation */
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qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE);
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clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
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if (!clk_data)
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return;
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clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL);
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if (!clk_data->clks) {
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kfree(clk_data);
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return;
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}
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for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) {
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of_property_read_string_index(node, "clock-output-names",
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j, &clk_name);
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/* No driver claims this clock, but it should remain gated */
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ignore = !strcmp("ahb_sdram", clk_name) ? CLK_IGNORE_UNUSED : 0;
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clk_data->clks[i] = clk_register_gate(NULL, clk_name,
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clk_parent, ignore,
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reg + 4 * (i/32), i % 32,
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0, &clk_lock);
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WARN_ON(IS_ERR(clk_data->clks[i]));
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j++;
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}
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/* Adjust to the real max */
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clk_data->clk_num = i;
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of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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}
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/* Matches for of_clk_init */
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static const __initconst struct of_device_id clk_match[] = {
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{.compatible = "allwinner,sun4i-osc-clk", .data = sunxi_osc_clk_setup,},
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{}
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};
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/* Matches for factors clocks */
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static const __initconst struct of_device_id clk_factors_match[] = {
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{.compatible = "allwinner,sun4i-pll1-clk", .data = &pll1_data,},
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{.compatible = "allwinner,sun4i-apb1-clk", .data = &apb1_data,},
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{}
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};
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/* Matches for divider clocks */
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static const __initconst struct of_device_id clk_div_match[] = {
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{.compatible = "allwinner,sun4i-axi-clk", .data = &axi_data,},
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{.compatible = "allwinner,sun4i-ahb-clk", .data = &ahb_data,},
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{.compatible = "allwinner,sun4i-apb0-clk", .data = &apb0_data,},
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{}
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};
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/* Matches for mux clocks */
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static const __initconst struct of_device_id clk_mux_match[] = {
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{.compatible = "allwinner,sun4i-cpu-clk", .data = &cpu_data,},
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{.compatible = "allwinner,sun4i-apb1-mux-clk", .data = &apb1_mux_data,},
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{}
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};
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/* Matches for gate clocks */
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static const __initconst struct of_device_id clk_gates_match[] = {
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{.compatible = "allwinner,sun4i-axi-gates-clk", .data = &axi_gates_data,},
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{.compatible = "allwinner,sun4i-ahb-gates-clk", .data = &ahb_gates_data,},
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{.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &apb0_gates_data,},
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{.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &apb1_gates_data,},
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{}
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};
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static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match,
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void *function)
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{
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struct device_node *np;
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const struct div_data *data;
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const struct of_device_id *match;
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void (*setup_function)(struct device_node *, const void *) = function;
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for_each_matching_node(np, clk_match) {
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match = of_match_node(clk_match, np);
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data = match->data;
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setup_function(np, data);
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}
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}
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void __init sunxi_init_clocks(void)
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{
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/* Register all the simple sunxi clocks on DT */
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of_clk_init(clk_match);
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/* Register factor clocks */
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of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup);
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/* Register divider clocks */
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of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup);
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/* Register mux clocks */
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of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
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/* Register gate clocks */
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of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
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}
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