116 lines
3.5 KiB
Plaintext
116 lines
3.5 KiB
Plaintext
* NVIDIA Tegra Secure Digital Host Controller
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This controller on Tegra family SoCs provides an interface for MMC, SD,
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and SDIO types of memory cards.
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This file documents differences between the core properties described
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by mmc.txt and the properties used by the sdhci-tegra driver.
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Required properties:
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- compatible : Should be "nvidia,<chip>-sdhci"
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Optional properties:
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- power-gpios : Specify GPIOs for power control
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- nvidia,no-runtime-suspend : No runtime PM support on the host
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- nvidia,host-off-card-on : The host is powered off while the card is powered
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on during suspend
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- tap-delay : initial tap delay value (for Rx at high freqs)
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- trim-delay : trim delay value (for Tx at high freqs)
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- ddr-trim-delay : trim delay value for DDR50
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- calib-3v3-offsets : Autocal HW offset for 3v3
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- calib-1v8-offsets : Autocal HW offset for 1v8
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- calib-1v8-offsets-uhs-modes : Mask for UHS mode calibration. Valid values are:
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Bit 1: SDR12
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Bit 2: SDR25
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Bit 3: SDR50
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Bit 4: DDR50
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Bit 5: SDR104
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Bit 6: HS200
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- uhs-mask : disables a UHS mode when corresponding bit set to 1. Valid values are:
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Bit 1: SDR12
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Bit 2: SDR25
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Bit 3: SDR50
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Bit 4: DDR50
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Bit 5: SDR104
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Bit 6: HS200
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- ddr-clk-limit : max clock frequency in DDR mode
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- nvidia,disable-ext-loopback : disable external loopback for controller in UHS modes
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- nvidia,{vmin,vmax} : corresponding min/max core voltage (in mV) for tuning
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coefficients
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- nvidia,t2t-{vmin,vmax,vnom}-{slope,int} : tap-to-tap tuning coefficients
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- per-frequency tuning data entries (should be in ascending order):
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- compatible : should be "nvidia,sdhci-tuning-data"
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- clock-frequency : tuning frequency in Hz
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- nvidia,thole-{vmin,vmax,vnom}-{slope,int} : tap-hole tuning coefficients
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Example:
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sdhci@c8000200 {
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compatible = "nvidia,tegra20-sdhci";
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reg = <0xc8000200 0x200>;
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interrupts = <47>;
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cd-gpios = <&gpio 69 0>; /* gpio PI5 */
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wp-gpios = <&gpio 57 0>; /* gpio PH1 */
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power-gpios = <&gpio 155 0>; /* gpio PT3 */
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bus-width = <8>;
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nvidia,no-runtime-suspend;
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nvidia,host-off-card-on;
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};
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Example 2:
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sdhci@700b0600 {
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compatible = "nvidia,tegra124-sdhci", "nvidia,tegra114-sdhci";
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reg = <0x700b0600 0x200>;
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interrupts = <0 31 0x04>;
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clocks = <&tegra_car 15>;
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tap-delay = <0x4>;
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trim-delay = <0x4>;
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ddr-trim-delay = <0x4>;
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ddr-clk-limit = <51000000>;
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calib-3v3-offsets = <0x0202>;
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calib-1v8-offsets = <0x0202>;
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calib-1v8-offsets-uhs-modes = <0x28>; /* DDR50 | HS200 */
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uhs-mask = <0x00>;
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nvidia,vmax = <1150>;
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nvidia,vmin = <950>;
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nvidia,t2t-vnom-slope = <27>;
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nvidia,t2t-vnom-int = <118295>;
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nvidia,t2t-vmax-slope = <27>;
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nvidia,t2t-vmax-int = <118295>;
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nvidia,t2t-vmin-slope = <48>;
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nvidia,t2t-vmin-int = <188148>;
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tuning-data@0 {
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compatible = "nvidia,sdhci-tuning-data";
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clock-frequency = <81600000>;
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nvidia,thole-vnom-slope = <3090>;
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nvidia,thole-vnom-int = <351666>;
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nvidia,thole-vmax-slope = <3090>;
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nvidia,thole-vmax-int = <351666>;
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nvidia,thole-vmin-slope = <1583>;
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nvidia,thole-vmin-int = <247913>;
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};
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tuning-data@1 {
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compatible = "nvidia,sdhci-tuning-data";
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clock-frequency = <136000000>;
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nvidia,thole-vnom-slope = <1703>;
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nvidia,thole-vnom-int = <186307>;
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nvidia,thole-vmax-slope = <1703>;
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nvidia,thole-vmax-int = <186307>;
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nvidia,thole-vmin-slope = <890>;
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nvidia,thole-vmin-int = <130617>;
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};
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tuning-data@2 {
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compatible = "nvidia,sdhci-tuning-data";
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clock-frequency = <204000000>;
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nvidia,thole-vnom-slope = <1037>;
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nvidia,thole-vnom-int = <106934>;
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nvidia,thole-vmax-slope = <1037>;
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nvidia,thole-vmax-int = <106934>;
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nvidia,thole-vmin-slope = <558>;
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nvidia,thole-vmin-int = <74315>;
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};
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};
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