159 lines
3.9 KiB
C
159 lines
3.9 KiB
C
/*
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* Copyright (c) 2012,2013, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __LINUX_TEGRA_SOC_H_
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#define __LINUX_TEGRA_SOC_H_
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#define TEGRA20 0x20
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#define TEGRA30 0x30
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#define TEGRA114 0x35
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#define TEGRA124 0x40
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#ifndef __ASSEMBLY__
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#include <asm/cputype.h>
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#include <linux/err.h>
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enum tegra_revision {
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TEGRA_REVISION_UNKNOWN = 0,
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TEGRA_REVISION_A01,
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TEGRA_REVISION_A02,
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TEGRA_REVISION_A03,
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TEGRA_REVISION_A03p,
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TEGRA_REVISION_A04,
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TEGRA_REVISION_MAX,
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};
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u32 tegra_read_straps(void);
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void tegra_init_fuse(void);
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extern int tegra_chip_id;
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extern enum tegra_revision tegra_revision;
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extern int tegra_bct_strapping;
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extern int tegra_sku_id;
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u32 tegra_read_chipid(void);
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int tegra_get_cpu_process_id(void);
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int tegra_get_core_process_id(void);
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int tegra_get_gpu_process_id(void);
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int tegra_get_cpu_speedo_id(void);
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int tegra_get_soc_speedo_id(void);
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int tegra_get_gpu_speedo_id(void);
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int tegra_get_cpu_speedo_value(void);
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int tegra_get_gpu_speedo_value(void);
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int tegra_get_cpu_iddq_value(void);
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u32 tegra_get_vp8_enable(void);
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enum {
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TEGRA_CLUSTER_G = 0,
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TEGRA_CLUSTER_LP = 1,
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};
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static inline bool is_lp_cluster(void)
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{
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return MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1) == TEGRA_CLUSTER_LP;
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}
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#ifdef CONFIG_ARCH_TEGRA_124_SOC
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int tegra_switch_cluster(int new_cluster);
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int tegra_cluster_control_init(void);
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int tegra124_get_core_speedo_mv(void);
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#else
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static inline int tegra_switch_cluster(int new_cluster)
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{
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return -EINVAL;
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}
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static inline int tegra_cluster_control_init(void)
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{
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return -EINVAL;
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}
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static inline int tegra124_get_core_speedo_mv(void)
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{ return -EINVAL; }
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#endif
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#ifdef CONFIG_TEGRA_GK20A
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struct tegra_cooling_device *tegra_get_gpu_vmin_cdev(void);
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struct tegra_cooling_device *tegra_get_gpu_vts_cdev(void);
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#else
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static inline struct tegra_cooling_device *tegra_get_gpu_vmin_cdev(void)
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{ return ERR_PTR(-EINVAL); }
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static inline struct tegra_cooling_device *tegra_get_gpu_vts_cdev(void)
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{ return ERR_PTR(-EINVAL); }
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#endif
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#ifdef CONFIG_ARM_TEGRA_CPUFREQ
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int tegra_cpufreq_init(void);
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#else
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static inline int tegra_cpufreq_init(void)
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{
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return -EINVAL;
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}
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#endif
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#ifdef CONFIG_TEGRA_CPUQUIET
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int tegra_cpuquiet_init(void);
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#else
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static inline int tegra_cpuquiet_init(void)
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{
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return -EINVAL;
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}
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#endif
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u32 tegra30_fuse_readl(const unsigned int offset);
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#ifdef CONFIG_TEGRA_KFUSE
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/* there are 144 32-bit values in total */
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#define TEGRA_KFUSE_DATA_SZ (144 * 4)
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int tegra_kfuse_read(void *dest, size_t len);
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#endif
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struct gpu_info {
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int num_pixel_pipes;
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int num_alus_per_pixel_pipe;
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};
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void tegra_gpu_get_info(struct gpu_info *pinfo);
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#if defined(CONFIG_TEGRA_GK20A) && defined(CONFIG_ARCH_TEGRA_124_SOC)
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int tegra_gpu_set_speed_cap(unsigned long *speed_cap);
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#else
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static inline int tegra_gpu_set_speed_cap(unsigned long *speed_cap)
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{ return -EINVAL; }
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#endif
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#if defined(CONFIG_TEGRA20_APB_DMA)
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int tegra_apb_readl_using_dma(unsigned long offset, u32 *value);
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int tegra_apb_writel_using_dma(u32 value, unsigned long offset);
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#else
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static inline int tegra_apb_readl_using_dma(unsigned long offset, u32 *value)
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{
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return -EINVAL;
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}
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static inline int tegra_apb_writel_using_dma(u32 value, unsigned long offset)
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{
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return -EINVAL;
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}
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#endif
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void tegra_pmc_remove_dpd_req(void);
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void tegra_pmc_clear_dpd_sample(void);
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#endif /* __ASSEMBLY__ */
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#endif /* __LINUX_TEGRA_SOC_H_ */
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