470 lines
12 KiB
C
470 lines
12 KiB
C
/*
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* include/linux/nvhost_ioctl.h
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*
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* Tegra graphics host driver
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*
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* Copyright (c) 2009-2014, NVIDIA Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#ifndef __LINUX_NVHOST_IOCTL_H
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#define __LINUX_NVHOST_IOCTL_H
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#include <linux/ioctl.h>
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#include <linux/types.h>
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#if !defined(__KERNEL__)
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#define __user
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#endif
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#define NVHOST_INVALID_SYNCPOINT 0xFFFFFFFF
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#define NVHOST_NO_TIMEOUT (-1)
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#define NVHOST_NO_CONTEXT 0x0
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#define NVHOST_IOCTL_MAGIC 'H'
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#define NVHOST_PRIORITY_LOW 50
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#define NVHOST_PRIORITY_MEDIUM 100
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#define NVHOST_PRIORITY_HIGH 150
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#define NVHOST_TIMEOUT_FLAG_DISABLE_DUMP 0
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#define NVHOST_SUBMIT_VERSION_V0 0x0
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#define NVHOST_SUBMIT_VERSION_V1 0x1
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#define NVHOST_SUBMIT_VERSION_V2 0x2
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#define NVHOST_SUBMIT_VERSION_MAX_SUPPORTED NVHOST_SUBMIT_VERSION_V2
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struct nvhost_cmdbuf {
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__u32 mem;
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__u32 offset;
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__u32 words;
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} __packed;
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struct nvhost_reloc {
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__u32 cmdbuf_mem;
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__u32 cmdbuf_offset;
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__u32 target;
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__u32 target_offset;
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};
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struct nvhost_reloc_shift {
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__u32 shift;
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} __packed;
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struct nvhost_waitchk {
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__u32 mem;
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__u32 offset;
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__u32 syncpt_id;
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__u32 thresh;
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};
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struct nvhost_gpfifo {
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__u32 entry0; /* first word of gpfifo entry */
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__u32 entry1; /* second word of gpfifo entry */
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};
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struct nvhost_syncpt_incr {
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__u32 syncpt_id;
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__u32 syncpt_incrs;
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};
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struct nvhost_get_param_args {
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__u32 value;
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} __packed;
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struct nvhost_get_param_arg {
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__u32 param;
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__u32 value;
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};
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struct nvhost_channel_open_args {
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__s32 channel_fd;
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};
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struct nvhost_set_nvmap_fd_args {
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__u32 fd;
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} __packed;
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struct nvhost_alloc_obj_ctx_args {
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__u32 class_num; /* kepler3d, 2d, compute, etc */
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__u32 padding;
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__u64 obj_id; /* output, used to free later */
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};
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struct nvhost_free_obj_ctx_args {
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__u64 obj_id; /* obj ctx to free */
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};
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struct nvhost_alloc_gpfifo_args {
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__u32 num_entries;
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/* set owner channel of this gpfifo as a vpr channel */
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#define NVHOST_ALLOC_GPFIFO_FLAGS_VPR_ENABLED (1 << 0)
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__u32 flags;
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};
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struct nvhost_fence {
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__u32 syncpt_id; /* syncpt id */
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__u32 value; /* syncpt value to wait or value for other to wait */
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};
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/* insert a wait on the fance before submitting gpfifo */
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#define NVHOST_SUBMIT_GPFIFO_FLAGS_FENCE_WAIT BIT(0)
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/* insert an fence update after submitting gpfifo and
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return the new fence for other to wait on */
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#define NVHOST_SUBMIT_GPFIFO_FLAGS_FENCE_GET BIT(1)
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/* choose between different gpfifo entry format */
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#define NVHOST_SUBMIT_GPFIFO_FLAGS_HW_FORMAT BIT(2)
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struct nvhost_submit_gpfifo_args {
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__u64 gpfifo;
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__u32 num_entries;
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__u32 flags;
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struct nvhost_fence fence;
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};
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struct nvhost_map_buffer_args {
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__u32 flags;
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#define NVHOST_MAP_BUFFER_FLAGS_ALIGN 0x0
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#define NVHOST_MAP_BUFFER_FLAGS_OFFSET BIT(0)
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#define NVHOST_MAP_BUFFER_FLAGS_KIND_PITCH 0x0
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#define NVHOST_MAP_BUFFER_FLAGS_KIND_SPECIFIED BIT(1)
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#define NVHOST_MAP_BUFFER_FLAGS_CACHEABLE_FALSE 0x0
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#define NVHOST_MAP_BUFFER_FLAGS_CACHEABLE_TRUE BIT(2)
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__u32 nvmap_handle;
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union {
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__u64 offset; /* valid if _offset flag given (in|out) */
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__u64 align; /* alignment multiple (0:={1 or n/a}) */
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} offset_alignment;
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__u32 kind;
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#define NVHOST_MAP_BUFFER_KIND_GENERIC_16BX2 0xfe
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};
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struct nvhost_unmap_buffer_args {
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__u64 offset;
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};
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struct nvhost_wait_args {
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#define NVHOST_WAIT_TYPE_NOTIFIER 0x0
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#define NVHOST_WAIT_TYPE_SEMAPHORE 0x1
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__u32 type;
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__u32 timeout;
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union {
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struct {
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/* handle and offset for notifier memory */
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__u32 nvmap_handle;
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__u32 offset;
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__u32 padding1;
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__u32 padding2;
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} notifier;
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struct {
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/* handle and offset for semaphore memory */
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__u32 nvmap_handle;
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__u32 offset;
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/* semaphore payload to wait for */
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__u32 payload;
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__u32 padding;
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} semaphore;
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} condition; /* determined by type field */
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};
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/* cycle stats support */
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struct nvhost_cycle_stats_args {
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__u32 nvmap_handle;
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};
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struct nvhost_read_3d_reg_args {
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__u32 offset;
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__u32 value;
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};
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enum nvhost_clk_attr {
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NVHOST_CLOCK = 0,
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NVHOST_BW,
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};
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/*
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* moduleid[15:0] => module id
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* moduleid[24:31] => nvhost_clk_attr
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*/
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#define NVHOST_MODULE_ID_BIT_POS 0
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#define NVHOST_MODULE_ID_BIT_WIDTH 16
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#define NVHOST_CLOCK_ATTR_BIT_POS 24
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#define NVHOST_CLOCK_ATTR_BIT_WIDTH 8
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struct nvhost_clk_rate_args {
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__u32 rate;
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__u32 moduleid;
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};
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struct nvhost_set_timeout_args {
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__u32 timeout;
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} __packed;
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struct nvhost_set_timeout_ex_args {
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__u32 timeout;
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__u32 flags;
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};
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struct nvhost_set_priority_args {
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__u32 priority;
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} __packed;
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#define NVHOST_ZCULL_MODE_GLOBAL 0
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#define NVHOST_ZCULL_MODE_NO_CTXSW 1
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#define NVHOST_ZCULL_MODE_SEPARATE_BUFFER 2
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#define NVHOST_ZCULL_MODE_PART_OF_REGULAR_BUF 3
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struct nvhost_zcull_bind_args {
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__u64 gpu_va;
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__u32 mode;
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__u32 padding;
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};
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struct nvhost_set_error_notifier {
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__u64 offset;
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__u64 size;
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__u32 mem;
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__u32 padding;
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};
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struct nvhost_ctrl_module_regrdwr_args {
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__u32 id;
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__u32 num_offsets;
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__u32 block_size;
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__u32 offsets;
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__u32 values;
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__u32 write;
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};
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struct nvhost_submit_args {
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__u32 submit_version;
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__u32 num_syncpt_incrs;
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__u32 num_cmdbufs;
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__u32 num_relocs;
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__u32 num_waitchks;
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__u32 timeout;
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__u32 syncpt_incrs;
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__u32 cmdbufs;
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__u32 relocs;
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__u32 reloc_shifts;
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__u32 waitchks;
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__u32 waitbases;
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__u32 class_ids;
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__u32 pad[2]; /* future expansion */
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__u32 fences;
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__u32 fence; /* Return value */
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} __packed;
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struct nvhost_set_ctxswitch_args {
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__u32 num_cmdbufs_save;
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__u32 num_save_incrs;
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__u32 save_incrs;
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__u32 save_waitbases;
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__u32 cmdbuf_save;
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__u32 num_cmdbufs_restore;
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__u32 num_restore_incrs;
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__u32 restore_incrs;
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__u32 restore_waitbases;
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__u32 cmdbuf_restore;
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__u32 num_relocs;
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__u32 relocs;
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__u32 reloc_shifts;
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__u32 pad;
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};
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struct nvhost_channel_buffer {
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__u32 dmabuf_fd; /* in */
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__u32 reserved0; /* reserved, must be 0 */
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__u64 reserved1[2]; /* reserved, must be 0 */
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__u64 address; /* out, device view to the buffer */
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};
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struct nvhost_channel_unmap_buffer_args {
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__u32 num_buffers; /* in, number of buffers to unmap */
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__u32 reserved; /* reserved, must be 0 */
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__u64 table_address; /* pointer to beginning of buffer */
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};
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struct nvhost_channel_map_buffer_args {
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__u32 num_buffers; /* in, number of buffers to map */
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__u32 reserved; /* reserved, must be 0 */
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__u64 table_address; /* pointer to beginning of buffer */
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};
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#define NVHOST_IOCTL_CHANNEL_GET_SYNCPOINTS \
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_IOR(NVHOST_IOCTL_MAGIC, 2, struct nvhost_get_param_args)
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#define NVHOST_IOCTL_CHANNEL_GET_WAITBASES \
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_IOR(NVHOST_IOCTL_MAGIC, 3, struct nvhost_get_param_args)
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#define NVHOST_IOCTL_CHANNEL_GET_MODMUTEXES \
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_IOR(NVHOST_IOCTL_MAGIC, 4, struct nvhost_get_param_args)
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#define NVHOST_IOCTL_CHANNEL_SET_NVMAP_FD \
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_IOW(NVHOST_IOCTL_MAGIC, 5, struct nvhost_set_nvmap_fd_args)
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#define NVHOST_IOCTL_CHANNEL_NULL_KICKOFF \
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_IOR(NVHOST_IOCTL_MAGIC, 6, struct nvhost_get_param_args)
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#define NVHOST_IOCTL_CHANNEL_READ_3D_REG \
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_IOWR(NVHOST_IOCTL_MAGIC, 8, struct nvhost_read_3d_reg_args)
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#define NVHOST_IOCTL_CHANNEL_GET_CLK_RATE \
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_IOR(NVHOST_IOCTL_MAGIC, 9, struct nvhost_clk_rate_args)
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#define NVHOST_IOCTL_CHANNEL_SET_CLK_RATE \
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_IOW(NVHOST_IOCTL_MAGIC, 10, struct nvhost_clk_rate_args)
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#define NVHOST_IOCTL_CHANNEL_SET_TIMEOUT \
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_IOW(NVHOST_IOCTL_MAGIC, 11, struct nvhost_set_timeout_args)
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#define NVHOST_IOCTL_CHANNEL_GET_TIMEDOUT \
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_IOR(NVHOST_IOCTL_MAGIC, 12, struct nvhost_get_param_args)
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#define NVHOST_IOCTL_CHANNEL_SET_PRIORITY \
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_IOW(NVHOST_IOCTL_MAGIC, 13, struct nvhost_set_priority_args)
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#define NVHOST_IOCTL_CHANNEL_MODULE_REGRDWR \
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_IOWR(NVHOST_IOCTL_MAGIC, 14, struct nvhost_ctrl_module_regrdwr_args)
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#define NVHOST_IOCTL_CHANNEL_SUBMIT \
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_IOWR(NVHOST_IOCTL_MAGIC, 15, struct nvhost_submit_args)
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#define NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT \
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_IOWR(NVHOST_IOCTL_MAGIC, 16, struct nvhost_get_param_arg)
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#define NVHOST_IOCTL_CHANNEL_GET_WAITBASE \
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_IOWR(NVHOST_IOCTL_MAGIC, 17, struct nvhost_get_param_arg)
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#define NVHOST_IOCTL_CHANNEL_SET_TIMEOUT_EX \
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_IOWR(NVHOST_IOCTL_MAGIC, 18, struct nvhost_set_timeout_ex_args)
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#define NVHOST_IOCTL_CHANNEL_GET_MODMUTEX \
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_IOWR(NVHOST_IOCTL_MAGIC, 23, struct nvhost_get_param_arg)
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#define NVHOST_IOCTL_CHANNEL_SET_CTXSWITCH \
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_IOWR(NVHOST_IOCTL_MAGIC, 25, struct nvhost_set_ctxswitch_args)
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/* START of T124 IOCTLS */
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#define NVHOST_IOCTL_CHANNEL_ALLOC_GPFIFO \
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_IOW(NVHOST_IOCTL_MAGIC, 100, struct nvhost_alloc_gpfifo_args)
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#define NVHOST_IOCTL_CHANNEL_WAIT \
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_IOWR(NVHOST_IOCTL_MAGIC, 102, struct nvhost_wait_args)
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#define NVHOST_IOCTL_CHANNEL_CYCLE_STATS \
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_IOWR(NVHOST_IOCTL_MAGIC, 106, struct nvhost_cycle_stats_args)
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#define NVHOST_IOCTL_CHANNEL_SUBMIT_GPFIFO \
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_IOWR(NVHOST_IOCTL_MAGIC, 107, struct nvhost_submit_gpfifo_args)
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#define NVHOST_IOCTL_CHANNEL_ALLOC_OBJ_CTX \
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_IOWR(NVHOST_IOCTL_MAGIC, 108, struct nvhost_alloc_obj_ctx_args)
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#define NVHOST_IOCTL_CHANNEL_FREE_OBJ_CTX \
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_IOR(NVHOST_IOCTL_MAGIC, 109, struct nvhost_free_obj_ctx_args)
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#define NVHOST_IOCTL_CHANNEL_ZCULL_BIND \
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_IOWR(NVHOST_IOCTL_MAGIC, 110, struct nvhost_zcull_bind_args)
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#define NVHOST_IOCTL_CHANNEL_MAP_BUFFER \
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_IOWR(NVHOST_IOCTL_MAGIC, 28, struct nvhost_channel_map_buffer_args)
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#define NVHOST_IOCTL_CHANNEL_UNMAP_BUFFER \
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_IOWR(NVHOST_IOCTL_MAGIC, 29, struct nvhost_channel_unmap_buffer_args)
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#define NVHOST_IOCTL_CHANNEL_SET_ERROR_NOTIFIER \
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_IOWR(NVHOST_IOCTL_MAGIC, 111, struct nvhost_set_error_notifier)
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#define NVHOST_IOCTL_CHANNEL_OPEN \
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_IOR(NVHOST_IOCTL_MAGIC, 112, struct nvhost_channel_open_args)
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#define NVHOST_IOCTL_CHANNEL_LAST \
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_IOC_NR(NVHOST_IOCTL_CHANNEL_OPEN)
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#define NVHOST_IOCTL_CHANNEL_MAX_ARG_SIZE sizeof(struct nvhost_submit_args)
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struct nvhost_ctrl_syncpt_read_args {
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__u32 id;
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__u32 value;
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};
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struct nvhost_ctrl_syncpt_incr_args {
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__u32 id;
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} __packed;
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struct nvhost_ctrl_syncpt_wait_args {
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__u32 id;
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__u32 thresh;
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__s32 timeout;
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} __packed;
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struct nvhost_ctrl_syncpt_waitex_args {
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__u32 id;
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__u32 thresh;
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__s32 timeout;
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__u32 value;
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};
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struct nvhost_ctrl_syncpt_waitmex_args {
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__u32 id;
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__u32 thresh;
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__s32 timeout;
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__u32 value;
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__u32 tv_sec;
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__u32 tv_nsec;
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__u32 reserved_1;
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__u32 reserved_2;
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};
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struct nvhost_ctrl_sync_fence_info {
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__u32 id;
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__u32 thresh;
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};
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struct nvhost_ctrl_sync_fence_create_args {
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__u32 num_pts;
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__u64 pts; /* struct nvhost_ctrl_sync_fence_info* */
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__u64 name; /* const char* */
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__s32 fence_fd; /* fd of new fence */
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};
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struct nvhost_ctrl_module_mutex_args {
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__u32 id;
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__u32 lock;
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};
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enum nvhost_module_id {
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NVHOST_MODULE_NONE = -1,
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NVHOST_MODULE_DISPLAY_A = 0,
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NVHOST_MODULE_DISPLAY_B,
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NVHOST_MODULE_VI,
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NVHOST_MODULE_ISP,
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NVHOST_MODULE_MPE,
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NVHOST_MODULE_MSENC,
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NVHOST_MODULE_TSEC,
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NVHOST_MODULE_GPU,
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NVHOST_MODULE_VIC,
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};
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#define NVHOST_IOCTL_CTRL_SYNCPT_READ \
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_IOWR(NVHOST_IOCTL_MAGIC, 1, struct nvhost_ctrl_syncpt_read_args)
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#define NVHOST_IOCTL_CTRL_SYNCPT_INCR \
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_IOW(NVHOST_IOCTL_MAGIC, 2, struct nvhost_ctrl_syncpt_incr_args)
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#define NVHOST_IOCTL_CTRL_SYNCPT_WAIT \
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_IOW(NVHOST_IOCTL_MAGIC, 3, struct nvhost_ctrl_syncpt_wait_args)
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#define NVHOST_IOCTL_CTRL_MODULE_MUTEX \
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_IOWR(NVHOST_IOCTL_MAGIC, 4, struct nvhost_ctrl_module_mutex_args)
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#define NVHOST_IOCTL_CTRL_MODULE_REGRDWR \
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_IOWR(NVHOST_IOCTL_MAGIC, 5, struct nvhost_ctrl_module_regrdwr_args)
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#define NVHOST_IOCTL_CTRL_SYNCPT_WAITEX \
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_IOWR(NVHOST_IOCTL_MAGIC, 6, struct nvhost_ctrl_syncpt_waitex_args)
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#define NVHOST_IOCTL_CTRL_GET_VERSION \
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_IOR(NVHOST_IOCTL_MAGIC, 7, struct nvhost_get_param_args)
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#define NVHOST_IOCTL_CTRL_SYNCPT_READ_MAX \
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_IOWR(NVHOST_IOCTL_MAGIC, 8, struct nvhost_ctrl_syncpt_read_args)
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#define NVHOST_IOCTL_CTRL_SYNCPT_WAITMEX \
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_IOWR(NVHOST_IOCTL_MAGIC, 9, struct nvhost_ctrl_syncpt_waitmex_args)
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#define NVHOST_IOCTL_CTRL_SYNC_FENCE_CREATE \
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_IOWR(NVHOST_IOCTL_MAGIC, 10, struct nvhost_ctrl_sync_fence_create_args)
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#define NVHOST_IOCTL_CTRL_LAST \
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_IOC_NR(NVHOST_IOCTL_CTRL_SYNC_FENCE_CREATE)
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#define NVHOST_IOCTL_CTRL_MAX_ARG_SIZE \
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sizeof(struct nvhost_ctrl_syncpt_waitmex_args)
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#endif
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