239 lines
6.1 KiB
C
239 lines
6.1 KiB
C
/*
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* vlv2_plat_clock.c - VLV2 platform clock driver
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* Copyright (C) 2013 Intel Corporation
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*
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* Author: Asutosh Pathak <asutosh.pathak@intel.com>
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* Author: Chandra Sekhar Anagani <chandra.sekhar.anagani@intel.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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*/
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/vlv2_plat_clock.h>
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/* NOTE: Most of below constants could come from platform data.
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* To be fixed when appropriate ACPI support comes.
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*/
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#define VLV2_PMC_CLK_BASE_ADDRESS 0xfed03060
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#define PLT_CLK_CTL_OFFSET(x) (0x04 * (x))
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#define CLK_CONFG_BIT_POS 0
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#define CLK_CONFG_BIT_LEN 2
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#define CLK_CONFG_D3_GATED 0
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#define CLK_CONFG_FORCE_ON 1
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#define CLK_CONFG_FORCE_OFF 2
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#define CLK_FREQ_TYPE_BIT_POS 2
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#define CLK_FREQ_TYPE_BIT_LEN 1
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#define CLK_FREQ_TYPE_XTAL 0 /* 25 MHz */
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#define CLK_FREQ_TYPE_PLL 1 /* 19.2 MHz */
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#define MAX_CLK_COUNT 5
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/* Helper macros to manipulate bitfields */
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#define REG_MASK(n) (((1 << (n##_BIT_LEN)) - 1) << (n##_BIT_POS))
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#define REG_SET_FIELD(r, n, v) (((r) & ~REG_MASK(n)) | \
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(((v) << (n##_BIT_POS)) & REG_MASK(n)))
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#define REG_GET_FIELD(r, n) (((r) & REG_MASK(n)) >> n##_BIT_POS)
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/*
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* vlv2 platform has 6 platform clocks, controlled by 4 byte registers
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* Total size required for mapping is 6*4 = 24 bytes
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*/
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#define PMC_MAP_SIZE 24
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static DEFINE_MUTEX(clk_mutex);
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static void __iomem *pmc_base;
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/*
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* vlv2_plat_set_clock_freq - Set clock frequency to a specified platform clock
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* @clk_num: Platform clock number (i.e. 0, 1, 2, ...,5)
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* @freq_type: Clock frequency (0-25 MHz(XTAL), 1-19.2 MHz(PLL) )
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*/
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int vlv2_plat_set_clock_freq(int clk_num, int freq_type)
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{
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void __iomem *addr;
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if (clk_num < 0 && clk_num > MAX_CLK_COUNT) {
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pr_err("Clock number out of range (%d)\n", clk_num);
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return -EINVAL;
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}
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if (freq_type != CLK_FREQ_TYPE_XTAL &&
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freq_type != CLK_FREQ_TYPE_PLL) {
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pr_err("wrong clock type\n");
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return -EINVAL;
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}
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if (!pmc_base) {
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pr_err("memio map is not set\n");
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return -EINVAL;
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}
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addr = pmc_base + PLT_CLK_CTL_OFFSET(clk_num);
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mutex_lock(&clk_mutex);
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writel(REG_SET_FIELD(readl(addr), CLK_FREQ_TYPE, freq_type), addr);
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mutex_unlock(&clk_mutex);
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return 0;
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}
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EXPORT_SYMBOL_GPL(vlv2_plat_set_clock_freq);
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/*
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* vlv2_plat_get_clock_freq - Get the status of specified platform clock
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* @clk_num: Platform clock number (i.e. 0, 1, 2, ...,5)
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*
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* Returns 0 for 25 MHz(XTAL) and 1 for 19.2 MHz(PLL)
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*/
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int vlv2_plat_get_clock_freq(int clk_num)
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{
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u32 ret;
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if (clk_num < 0 && clk_num > MAX_CLK_COUNT) {
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pr_err("Clock number out of range (%d)\n", clk_num);
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return -EINVAL;
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}
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if (!pmc_base) {
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pr_err("memio map is not set\n");
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return -EINVAL;
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}
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mutex_lock(&clk_mutex);
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ret = REG_GET_FIELD(readl(pmc_base + PLT_CLK_CTL_OFFSET(clk_num)),
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CLK_FREQ_TYPE);
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mutex_unlock(&clk_mutex);
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return ret;
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}
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EXPORT_SYMBOL_GPL(vlv2_plat_get_clock_freq);
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/*
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* vlv2_plat_configure_clock - Configure the specified platform clock
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* @clk_num: Platform clock number (i.e. 0, 1, 2, ...,5)
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* @conf: Clock gating:
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* 0 - Clock gated on D3 state
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* 1 - Force on
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* 2,3 - Force off
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*/
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int vlv2_plat_configure_clock(int clk_num, u32 conf)
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{
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void __iomem *addr;
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if (clk_num < 0 && clk_num > MAX_CLK_COUNT) {
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pr_err("Clock number out of range (%d)\n", clk_num);
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return -EINVAL;
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}
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if (conf != CLK_CONFG_D3_GATED &&
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conf != CLK_CONFG_FORCE_ON &&
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conf != CLK_CONFG_FORCE_OFF) {
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pr_err("Invalid clock configuration requested\n");
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return -EINVAL;
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}
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if (!pmc_base) {
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pr_err("memio map is not set\n");
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return -EINVAL;
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}
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addr = pmc_base + PLT_CLK_CTL_OFFSET(clk_num);
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mutex_lock(&clk_mutex);
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writel(REG_SET_FIELD(readl(addr), CLK_CONFG, conf), addr);
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mutex_unlock(&clk_mutex);
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return 0;
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}
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EXPORT_SYMBOL_GPL(vlv2_plat_configure_clock);
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/*
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* vlv2_plat_get_clock_status - Get the status of specified platform clock
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* @clk_num: Platform clock number (i.e. 0, 1, 2, ...,5)
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*
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* Returns 1 - On, 0 - Off
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*/
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int vlv2_plat_get_clock_status(int clk_num)
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{
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int ret;
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if (clk_num < 0 && clk_num > MAX_CLK_COUNT) {
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pr_err("Clock number out of range (%d)\n", clk_num);
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return -EINVAL;
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}
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if (!pmc_base) {
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pr_err("memio map is not set\n");
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return -EINVAL;
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}
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mutex_lock(&clk_mutex);
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ret = (int)REG_GET_FIELD(readl(pmc_base + PLT_CLK_CTL_OFFSET(clk_num)),
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CLK_CONFG);
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mutex_unlock(&clk_mutex);
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return ret;
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}
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EXPORT_SYMBOL_GPL(vlv2_plat_get_clock_status);
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static int vlv2_plat_clk_probe(struct platform_device *pdev)
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{
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pmc_base = ioremap_nocache(VLV2_PMC_CLK_BASE_ADDRESS, PMC_MAP_SIZE);
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if (!pmc_base) {
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dev_err(&pdev->dev, "I/O memory remapping failed\n");
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return -ENOMEM;
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}
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dev_info(&pdev->dev, "%s(%d)\n", __func__, __LINE__);
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return 0;
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}
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static int vlv2_plat_clk_remove(struct platform_device *pdev)
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{
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iounmap(pmc_base);
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pmc_base = NULL;
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return 0;
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}
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static const struct platform_device_id vlv2_plat_clk_id[] = {
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{"vlv2_plat_clk", 0},
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{}
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};
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MODULE_DEVICE_TABLE(platform, vlv2_plat_clk_id);
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static struct platform_driver vlv2_plat_clk_driver = {
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.probe = vlv2_plat_clk_probe,
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.remove = vlv2_plat_clk_remove,
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.id_table = vlv2_plat_clk_id,
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.driver = {
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.name = "vlv2_plat_clk",
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.owner = THIS_MODULE,
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},
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};
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static int __init vlv2_plat_clk_init(void)
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{
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return platform_driver_register(&vlv2_plat_clk_driver);
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}
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arch_initcall(vlv2_plat_clk_init);
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static void __exit vlv2_plat_clk_exit(void)
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{
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platform_driver_unregister(&vlv2_plat_clk_driver);
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}
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module_exit(vlv2_plat_clk_exit);
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MODULE_AUTHOR("Asutosh Pathak <asutosh.pathak@intel.com>");
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MODULE_DESCRIPTION("Intel VLV2 platform clock driver");
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MODULE_LICENSE("GPL v2");
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