67 lines
2.6 KiB
Plaintext
67 lines
2.6 KiB
Plaintext
NVIDIA Tegra124 DFLL clocksource data in the SoC DTS file:
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Required properties:
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- compatible : "nvidia,tegra124-dfll"
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- reg : Must contain the starting physical address and length for the
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DFLL's MMIO register space, including the DFLL-to-I2C
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controller interface and the DFLL's I2C controller.
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- clocks : Must contain an array of two-cell arrays, one per clock.
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DFLL source clocks. At minimum this should include the
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reference clock source and the IP block's main clock
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source. Also it should contain the DFLL's I2C controller
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clock source. The format is <&clock-provider-phandle
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clock-id>.
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- clock-names : Must contain an array of strings, one per 'clocks'
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two-cell array. The position in the array of these
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strings must correspond to the position in the 'clocks'
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array (see above). The DFLL driver currently requires
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the "soc", "ref", and "i2c" clock names to be populated.
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Optional properties:
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- status : device availability -- managed by the DT integration code, not
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the DFLL driver. Should be set to "disabled" in the SoC
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DTS file.
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Example:
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dfll@70110000 {
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compatible = "nvidia,tegra124-dfll";
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reg = <0x70110000 0x400>;
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clocks = <&tegra_car 265>, <&tegra_car 264>, <&tegra_car 47>;
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clock-names = "soc", "ref", "i2c";
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status = "disabled";
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};
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...
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NVIDIA Tegra124 DFLL clocksource data in the board DTS file
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Required properties:
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- vdd-supply : phandle pointing to the DFLL's voltage regulator
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- pmic-integration : phandle pointing to the PMIC integration data
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for this DFLL instance
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- board-params : phandle pointing to the board-specific tuning data
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for this DFLL instance
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- cvb-table : phandle pointing to the DFLL-specific CVB table for
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this DFLL instance
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Optional properties:
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- i2c-quiet-output-workaround : If the DFLL IP block version
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implemented on this SoC requires the
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I2C output to the PMIC to be quiesced
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before disabling it, this property
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should be set.
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- status : device availability -- managed by the DT integration code, not
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the DFLL driver. Should be set to "okay" if the DFLL is to be
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used on this board type.
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Example:
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dfll@70110000 {
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vdd-supply = <&vdd_cpu_reg>;
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board-params = <&{/cpu_dfll_board_params}>;
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pmic-integration = <&{/cpu_dfll_pmic_integration}>;
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status = "okay";
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};
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