164 lines
4.1 KiB
C
164 lines
4.1 KiB
C
/*
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* drivers/video/tegra/host/gk20a/fifo_gk20a.h
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*
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* GK20A graphics fifo (gr host)
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*
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* Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#ifndef __FIFO_GK20A_H__
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#define __FIFO_GK20A_H__
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#include "channel_gk20a.h"
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#define MAX_RUNLIST_BUFFERS 2
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/* generally corresponds to the "pbdma" engine */
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struct fifo_runlist_info_gk20a {
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unsigned long *active_channels;
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/* Each engine has its own SW and HW runlist buffer.*/
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struct runlist_mem_desc mem[MAX_RUNLIST_BUFFERS];
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u32 cur_buffer;
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u32 total_entries;
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bool stopped;
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bool support_tsg;
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struct mutex mutex; /* protect channel preempt and runlist upate */
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wait_queue_head_t runlist_wq;
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};
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/* so far gk20a has two engines: gr and ce2(gr_copy) */
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enum {
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ENGINE_GR_GK20A = 0,
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ENGINE_CE2_GK20A = 1,
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ENGINE_INVAL_GK20A
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};
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struct fifo_pbdma_exception_info_gk20a {
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u32 status_r; /* raw register value from hardware */
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u32 id, next_id;
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u32 chan_status_v; /* raw value from hardware */
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bool id_is_chid, next_id_is_chid;
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bool chsw_in_progress;
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};
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struct fifo_engine_exception_info_gk20a {
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u32 status_r; /* raw register value from hardware */
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u32 id, next_id;
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u32 ctx_status_v; /* raw value from hardware */
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bool id_is_chid, next_id_is_chid;
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bool faulted, idle, ctxsw_in_progress;
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};
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struct fifo_mmu_fault_info_gk20a {
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u32 fault_info_v;
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u32 fault_type_v;
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u32 engine_subid_v;
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u32 client_v;
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u32 fault_hi_v;
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u32 fault_lo_v;
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u64 inst_ptr;
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const char *fault_type_desc;
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const char *engine_subid_desc;
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const char *client_desc;
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};
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struct fifo_engine_info_gk20a {
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u32 sw_id;
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const char *name;
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u32 dev_info_id;
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u32 engine_id;
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u32 runlist_id;
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u32 pbdma_id;
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u32 mmu_fault_id;
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u32 rc_mask;
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struct fifo_pbdma_exception_info_gk20a pbdma_exception_info;
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struct fifo_engine_exception_info_gk20a engine_exception_info;
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struct fifo_mmu_fault_info_gk20a mmu_fault_info;
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};
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struct fifo_gk20a {
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struct gk20a *g;
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int num_channels;
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int num_pbdma;
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u32 *pbdma_map;
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struct fifo_engine_info_gk20a *engine_info;
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u32 max_engines;
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u32 num_engines;
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struct fifo_runlist_info_gk20a *runlist_info;
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u32 max_runlists;
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struct userd_desc userd;
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u32 userd_entry_size;
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u32 userd_total_size;
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struct channel_gk20a *channel;
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struct mutex ch_inuse_mutex; /* protect unused chid look up */
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void (*remove_support)(struct fifo_gk20a *);
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bool sw_ready;
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struct {
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/* share info between isrs and non-isr code */
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struct {
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struct mutex mutex;
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} isr;
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struct {
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u32 device_fatal_0;
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u32 channel_fatal_0;
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u32 restartable_0;
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} pbdma;
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struct {
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} engine;
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} intr;
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u32 mmu_fault_engines;
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bool deferred_reset_pending;
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struct mutex deferred_reset_mutex;
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struct work_struct fault_restore_thread;
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};
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int gk20a_init_fifo_support(struct gk20a *g);
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void gk20a_fifo_isr(struct gk20a *g);
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int gk20a_fifo_preempt_channel(struct gk20a *g, u32 hw_chid);
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int gk20a_fifo_enable_engine_activity(struct gk20a *g,
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struct fifo_engine_info_gk20a *eng_info);
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int gk20a_fifo_disable_engine_activity(struct gk20a *g,
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struct fifo_engine_info_gk20a *eng_info,
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bool wait_for_idle);
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int gk20a_fifo_update_runlist(struct gk20a *g, u32 engine_id, u32 hw_chid,
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bool add, bool wait_for_finish);
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int gk20a_fifo_suspend(struct gk20a *g);
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bool gk20a_fifo_mmu_fault_pending(struct gk20a *g);
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void gk20a_fifo_recover(struct gk20a *g, u32 engine_ids, bool verbose);
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int gk20a_init_fifo_reset_enable_hw(struct gk20a *g);
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void fifo_gk20a_finish_mmu_fault_handling(struct gk20a *g,
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unsigned long fault_id);
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#endif /*__GR_GK20A_H__*/
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