144 lines
3.6 KiB
C
144 lines
3.6 KiB
C
/*
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* drivers/video/tegra/host/vic/vic03.h
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*
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* Tegra VIC03 Module Support
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*
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* Copyright (c) 2011-2013, NVIDIA Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __NVHOST_VIC03_H__
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#define __NVHOST_VIC03_H__
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#include <linux/types.h>
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#include <linux/dma-attrs.h>
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#include <linux/firmware.h>
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extern struct platform_device tegra_vic03_device;
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struct ucode_bin_header_v1_vic03 {
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u32 bin_magic; /* 0x10de */
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u32 bin_ver; /* cya, versioning of bin format (1) */
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u32 bin_size; /* entire image size including this header */
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u32 os_bin_header_offset;
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u32 os_bin_data_offset;
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u32 os_bin_size;
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u32 fce_bin_header_offset;
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u32 fce_bin_data_offset;
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u32 fce_bin_size;
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};
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struct ucode_os_code_header_v1_vic03 {
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u32 offset;
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u32 size;
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};
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struct ucode_os_header_v1_vic03 {
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u32 os_code_offset;
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u32 os_code_size;
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u32 os_data_offset;
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u32 os_data_size;
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u32 num_apps;
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struct ucode_os_code_header_v1_vic03 *app_code;
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struct ucode_os_code_header_v1_vic03 *app_data;
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u32 *os_ovl_offset;
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u32 *of_ovl_size;
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};
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struct ucode_fce_header_v1_vic03 {
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u32 fce_ucode_offset;
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u32 fce_ucode_buffer_size;
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u32 fce_ucode_size;
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};
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struct ucode_v1_vic03 {
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struct ucode_bin_header_v1_vic03 *bin_header;
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struct ucode_os_header_v1_vic03 *os_header;
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struct ucode_fce_header_v1_vic03 *fce_header;
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};
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struct vic03 {
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struct nvhost_master *host;
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struct resource *reg_mem;
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void __iomem *regs;
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bool is_booted;
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struct {
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bool valid;
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size_t size;
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struct {
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u32 bin_data_offset;
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u32 data_offset;
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u32 data_size;
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u32 code_offset;
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u32 size;
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} os, fce;
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dma_addr_t dma_addr;
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u32 *mapped;
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} ucode;
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void (*remove_support)(struct vic03 *);
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};
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/* register accessors */
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static inline void vic03_writel(struct vic03 *vic, u32 r, u32 v)
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{
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nvhost_dbg(dbg_reg, " vic03 r=0x%x v=0x%x", r, v);
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writel(v, vic->regs + r);
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}
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static inline u32 vic03_readl(struct vic03 *vic, u32 r)
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{
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u32 v;
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v = readl(vic->regs + r);
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nvhost_dbg(dbg_reg, " vic03 r=0x%x v=0x%x", r, v);
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return v;
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}
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struct nvhost_hwctx_handler *nvhost_vic03_alloc_hwctx_handler(
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u32 syncpt, u32 base,
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struct nvhost_channel *ch);
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int nvhost_vic03_prepare_poweroff(struct platform_device *);
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int nvhost_vic03_finalize_poweron(struct platform_device *);
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void nvhost_vic03_busy(struct platform_device *);
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void nvhost_vic03_idle(struct platform_device *);
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void nvhost_vic03_suspend(struct platform_device *);
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int nvhost_vic03_init(struct platform_device *);
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void nvhost_vic03_deinit(struct platform_device *);
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/* hack, get these from elsewhere */
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#define NVA0B6_VIDEO_COMPOSITOR_SET_APPLICATION_ID (0x00000200)
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#define NVA0B6_VIDEO_COMPOSITOR_SET_FCE_UCODE_SIZE (0x0000071C)
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#define NVA0B6_VIDEO_COMPOSITOR_SET_FCE_UCODE_OFFSET (0x0000072C)
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#define VIC_UCLASS_METHOD_OFFSET 0x10
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#define NVHOST_ENCODE_VIC_VER(maj, min) \
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((((maj) & 0xff) << 8) | ((min) & 0xff))
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static inline void decode_vic_ver(int version, u8 *maj, u8 *min)
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{
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u32 uv32 = (u32)version;
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*maj = (u8)((uv32 >> 8) & 0xff);
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*min = (u8)(uv32 & 0xff);
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}
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#endif /* __NVHOST_VIC_H__ */
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