264 lines
6.1 KiB
C
264 lines
6.1 KiB
C
/*
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* drivers/video/tegra/host/gr3d/gr3d.c
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*
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* Tegra Graphics Host 3D
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*
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* Copyright (c) 2012-2013 NVIDIA Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/slab.h>
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#include <linux/export.h>
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#include <linux/module.h>
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#include <linux/scatterlist.h>
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#include <linux/pm_runtime.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_platform.h>
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#include <linux/pm.h>
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#include <linux/dma-buf.h>
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#include <linux/syscalls.h>
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#include <linux/platform_data/tegra_pm_domains.h>
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#include "t114/t114.h"
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#include "host1x/host1x01_hardware.h"
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#include "nvhost_hwctx.h"
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#include "nvhost_acm.h"
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#include "dev.h"
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#include "gr3d.h"
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#include "gr3d_t114.h"
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#include "scale3d.h"
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#include "bus_client.h"
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#include "nvhost_channel.h"
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#include "chip_support.h"
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#include "pod_scaling.h"
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#include "class_ids.h"
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#include "nvhost_job.h"
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void nvhost_3dctx_restore_begin(struct host1x_hwctx_handler *p, u32 *ptr)
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{
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/* set class to host */
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ptr[0] = nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
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host1x_uclass_incr_syncpt_base_r(), 1);
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/* increment sync point base */
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ptr[1] = nvhost_class_host_incr_syncpt_base(p->h.waitbase,
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p->restore_incrs);
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/* set class to 3D */
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ptr[2] = nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID, 0, 0);
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/* program PSEQ_QUAD_ID */
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ptr[3] = nvhost_opcode_imm(AR3D_PSEQ_QUAD_ID, 0);
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}
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void nvhost_3dctx_restore_direct(u32 *ptr, u32 start_reg, u32 count)
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{
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ptr[0] = nvhost_opcode_incr(start_reg, count);
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}
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void nvhost_3dctx_restore_indirect(u32 *ptr, u32 offset_reg, u32 offset,
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u32 data_reg, u32 count)
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{
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ptr[0] = nvhost_opcode_imm(offset_reg, offset);
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ptr[1] = nvhost_opcode_nonincr(data_reg, count);
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}
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void nvhost_3dctx_restore_end(struct host1x_hwctx_handler *p, u32 *ptr)
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{
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/* syncpt increment to track restore gather. */
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ptr[0] = nvhost_opcode_imm_incr_syncpt(
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host1x_uclass_incr_syncpt_cond_op_done_v(), p->h.syncpt);
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}
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/*** ctx3d ***/
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struct host1x_hwctx *nvhost_3dctx_alloc_common(struct host1x_hwctx_handler *p,
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struct nvhost_channel *ch, bool mem_flag)
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{
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struct host1x_hwctx *ctx;
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ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
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if (!ctx)
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return NULL;
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if (mem_flag)
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ctx->cpuva = dma_alloc_writecombine(&ch->dev->dev,
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p->restore_size * 4,
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&ctx->iova,
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GFP_KERNEL);
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else
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ctx->cpuva = dma_alloc_coherent(&ch->dev->dev,
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p->restore_size * 4,
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&ctx->iova,
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GFP_KERNEL);
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if (!ctx->cpuva) {
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dev_err(&ch->dev->dev, "memory allocation failed\n");
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goto fail;
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}
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kref_init(&ctx->hwctx.ref);
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ctx->hwctx.h = &p->h;
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ctx->hwctx.channel = ch;
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ctx->hwctx.valid = false;
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ctx->hwctx.save_incrs = p->save_incrs;
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ctx->hwctx.save_slots = p->save_slots;
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ctx->restore_size = p->restore_size;
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ctx->hwctx.restore_incrs = p->restore_incrs;
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ctx->mem_flag = mem_flag;
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return ctx;
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fail:
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kfree(ctx);
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return NULL;
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}
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void nvhost_3dctx_restore_push(struct nvhost_hwctx *nctx,
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struct nvhost_cdma *cdma)
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{
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struct host1x_hwctx *ctx = to_host1x_hwctx(nctx);
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_nvhost_cdma_push_gather(cdma,
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ctx->cpuva,
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ctx->iova,
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0,
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nvhost_opcode_gather(ctx->restore_size),
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ctx->iova);
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}
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void nvhost_3dctx_get(struct nvhost_hwctx *ctx)
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{
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kref_get(&ctx->ref);
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}
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void nvhost_3dctx_free(struct kref *ref)
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{
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struct nvhost_hwctx *nctx = container_of(ref, struct nvhost_hwctx, ref);
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struct host1x_hwctx *ctx = to_host1x_hwctx(nctx);
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if (ctx->cpuva) {
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if (ctx->mem_flag)
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dma_free_writecombine(&nctx->channel->dev->dev,
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ctx->restore_size * 4,
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ctx->cpuva,
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ctx->iova);
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else
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dma_free_coherent(&nctx->channel->dev->dev,
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ctx->restore_size * 4,
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ctx->cpuva,
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ctx->iova);
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ctx->cpuva = NULL;
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ctx->iova = 0;
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}
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kfree(ctx);
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}
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void nvhost_3dctx_put(struct nvhost_hwctx *ctx)
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{
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kref_put(&ctx->ref, nvhost_3dctx_free);
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}
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int nvhost_gr3d_prepare_power_off(struct platform_device *dev)
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{
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struct nvhost_device_data *pdata = platform_get_drvdata(dev);
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return nvhost_channel_save_context(pdata->channel);
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}
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static struct of_device_id tegra_gr3d_of_match[] = {
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#ifdef TEGRA_11X_OR_HIGHER_CONFIG
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{ .compatible = "nvidia,tegra114-gr3d",
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.data = (struct nvhost_device_data *)&t11_gr3d_info },
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#endif
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{ },
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};
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static int gr3d_probe(struct platform_device *dev)
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{
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int err = 0;
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struct nvhost_device_data *pdata = NULL;
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if (dev->dev.of_node) {
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const struct of_device_id *match;
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match = of_match_device(tegra_gr3d_of_match, &dev->dev);
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if (match)
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pdata = (struct nvhost_device_data *)match->data;
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} else
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pdata = (struct nvhost_device_data *)dev->dev.platform_data;
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WARN_ON(!pdata);
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if (!pdata) {
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dev_info(&dev->dev, "no platform data\n");
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return -ENODATA;
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}
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pdata->pdev = dev;
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mutex_init(&pdata->lock);
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platform_set_drvdata(dev, pdata);
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err = nvhost_client_device_get_resources(dev);
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if (err)
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return err;
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nvhost_module_init(dev);
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#ifdef CONFIG_PM_GENERIC_DOMAINS
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pdata->pd.name = "gr3d";
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err = nvhost_module_add_domain(&pdata->pd, dev);
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#endif
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err = nvhost_client_device_init(dev);
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return err;
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}
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static int __exit gr3d_remove(struct platform_device *dev)
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{
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#ifdef CONFIG_PM_RUNTIME
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pm_runtime_put(&dev->dev);
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pm_runtime_disable(&dev->dev);
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#else
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nvhost_module_disable_clk(&dev->dev);
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#endif
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return 0;
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}
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static struct platform_driver gr3d_driver = {
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.probe = gr3d_probe,
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.remove = __exit_p(gr3d_remove),
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.driver = {
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.owner = THIS_MODULE,
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.name = "gr3d",
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#ifdef CONFIG_OF
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.of_match_table = tegra_gr3d_of_match,
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#endif
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#ifdef CONFIG_PM
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.pm = &nvhost_module_pm_ops,
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#endif
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},
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};
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static int __init gr3d_init(void)
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{
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return platform_driver_register(&gr3d_driver);
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}
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static void __exit gr3d_exit(void)
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{
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platform_driver_unregister(&gr3d_driver);
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}
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module_init(gr3d_init);
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module_exit(gr3d_exit);
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