375 lines
7.9 KiB
C
375 lines
7.9 KiB
C
/*
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* drivers/video/tegra/host/gk20a/mm_gk20a.h
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*
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* GK20A memory management
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*
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* Copyright (c) 2011-2013, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#ifndef __MM_GK20A_H__
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#define __MM_GK20A_H__
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#include <linux/scatterlist.h>
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#include <linux/iommu.h>
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#include <asm/dma-iommu.h>
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#include "../nvhost_allocator.h"
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/* This "address bit" in the gmmu ptes (and other gk20a accesses)
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* signals the address as presented should be translated by the SMMU.
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* Without this bit present gk20a accesses are *not* translated.
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*/
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/* Hack, get this from manuals somehow... */
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#define NV_MC_SMMU_VADDR_TRANSLATION_BIT 34
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#define NV_MC_SMMU_VADDR_TRANSLATE(x) (x | \
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(1ULL << NV_MC_SMMU_VADDR_TRANSLATION_BIT))
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/* For now keep the size relatively small-ish compared to the full
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* 40b va. 32GB for now. It consists of two 16GB spaces. */
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#define NV_GMMU_VA_RANGE 35ULL
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#define NV_GMMU_VA_IS_UPPER(x) ((x) >= ((u64)0x1 << (NV_GMMU_VA_RANGE-1)))
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struct mem_desc {
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struct mem_handle *ref;
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struct sg_table *sgt;
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u32 size;
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};
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struct mem_desc_sub {
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u32 offset;
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u32 size;
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};
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struct gpfifo_desc {
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size_t size;
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u32 entry_num;
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u32 get;
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u32 put;
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bool wrap;
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dma_addr_t iova;
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struct gpfifo *cpu_va;
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u64 gpu_va;
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};
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struct mmu_desc {
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void *cpuva;
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dma_addr_t iova;
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size_t size;
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};
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struct inst_desc {
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dma_addr_t iova;
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void *cpuva;
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phys_addr_t cpu_pa;
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size_t size;
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};
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struct userd_desc {
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struct sg_table *sgt;
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dma_addr_t iova;
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void *cpuva;
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size_t size;
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u64 gpu_va;
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};
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struct runlist_mem_desc {
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dma_addr_t iova;
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void *cpuva;
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size_t size;
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};
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struct patch_desc {
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struct page **pages;
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dma_addr_t iova;
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size_t size;
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void *cpu_va;
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u64 gpu_va;
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u32 data_count;
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};
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struct pmu_mem_desc {
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void *cpuva;
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dma_addr_t iova;
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u64 pmu_va;
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size_t size;
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};
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struct priv_cmd_queue_mem_desc {
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dma_addr_t base_iova;
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u32 *base_cpuva;
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size_t size;
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};
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struct zcull_ctx_desc {
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struct mem_desc mem;
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u64 gpu_va;
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u32 ctx_attr;
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u32 ctx_sw_mode;
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};
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struct pm_ctx_desc {
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struct mem_desc mem;
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u64 gpu_va;
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u32 ctx_attr;
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u32 ctx_sw_mode;
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};
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struct gr_ctx_desc {
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struct page **pages;
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dma_addr_t iova;
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size_t size;
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u64 gpu_va;
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};
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struct compbit_store_desc {
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struct pages **pages;
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size_t size;
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dma_addr_t base_iova;
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};
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struct page_table_gk20a {
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/* backing for */
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/* Either a *page or a *mem_handle */
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void *ref;
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/* track mapping cnt on this page table */
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u32 ref_cnt;
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struct sg_table *sgt;
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};
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enum gmmu_pgsz_gk20a {
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gmmu_page_size_small = 0,
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gmmu_page_size_big = 1,
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gmmu_nr_page_sizes = 2
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};
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struct page_directory_gk20a {
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/* backing for */
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u32 num_pdes;
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void *kv;
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/* Either a *page or a *mem_handle */
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void *ref;
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struct sg_table *sgt;
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struct page_table_gk20a *ptes[gmmu_nr_page_sizes];
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};
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struct mapped_buffer_node {
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struct vm_gk20a *vm;
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struct rb_node node;
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struct list_head unmap_list;
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u64 addr;
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u64 size;
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struct mem_mgr *memmgr;
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struct mem_handle *handle_ref;
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struct sg_table *sgt;
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struct kref ref;
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u32 user_mapped;
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bool own_mem_ref;
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u32 pgsz_idx;
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u32 ctag_offset;
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u32 ctag_lines;
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u32 flags;
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bool va_allocated;
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};
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struct vm_gk20a {
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struct mm_gk20a *mm;
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struct nvhost_as_share *as_share; /* as_share this represents */
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u64 va_start;
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u64 va_limit;
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int num_user_mapped_buffers;
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bool big_pages; /* enable large page support */
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bool enable_ctag;
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bool tlb_dirty;
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bool mapped;
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struct kref ref;
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struct mutex update_gmmu_lock;
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struct page_directory_gk20a pdes;
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struct nvhost_allocator vma[gmmu_nr_page_sizes];
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struct rb_root mapped_buffers;
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};
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struct gk20a;
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struct channel_gk20a;
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int gk20a_init_mm_support(struct gk20a *g);
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int gk20a_init_mm_setup_sw(struct gk20a *g);
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int gk20a_init_bar1_vm(struct mm_gk20a *mm);
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int gk20a_init_pmu_vm(struct mm_gk20a *mm);
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void gk20a_mm_fb_flush(struct gk20a *g);
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void gk20a_mm_l2_flush(struct gk20a *g, bool invalidate);
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void gk20a_mm_l2_invalidate(struct gk20a *g);
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struct mm_gk20a {
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struct gk20a *g;
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u32 big_page_size;
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u32 pde_stride;
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u32 pde_stride_shift;
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struct {
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u32 order;
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u32 num_ptes;
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} page_table_sizing[gmmu_nr_page_sizes];
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struct {
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u64 size;
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} channel;
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struct {
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u32 aperture_size;
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struct vm_gk20a vm;
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struct inst_desc inst_block;
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} bar1;
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struct {
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u32 aperture_size;
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struct vm_gk20a vm;
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struct inst_desc inst_block;
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} pmu;
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struct mutex tlb_lock;
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struct mutex l2_op_lock;
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void (*remove_support)(struct mm_gk20a *mm);
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bool sw_ready;
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#ifdef CONFIG_DEBUG_FS
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u32 ltc_enabled;
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u32 ltc_enabled_debug;
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#endif
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};
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int gk20a_mm_init(struct mm_gk20a *mm);
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#define gk20a_from_mm(mm) ((mm)->g)
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#define gk20a_from_vm(vm) ((vm)->mm->g)
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#define mem_mgr_from_mm(mm) (gk20a_from_mm(mm)->host->memmgr)
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#define mem_mgr_from_vm(vm) (gk20a_from_vm(vm)->host->memmgr)
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#define dev_from_vm(vm) dev_from_gk20a(vm->mm->g)
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#define DEFAULT_ALLOC_FLAGS (mem_mgr_flag_uncacheable)
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#define DEFAULT_ALLOC_ALIGNMENT (4*1024)
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static inline int bar1_aperture_size_mb_gk20a(void)
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{
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return 128; /*TBD read this from fuses?*/
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}
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/* max address bits */
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static inline int max_physaddr_bits_gk20a(void)
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{
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return 40;/*"old" sys physaddr, meaningful? */
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}
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static inline int max_vid_physaddr_bits_gk20a(void)
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{
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/* "vid phys" is asid/smmu phys?,
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* i.e. is this the real sys physaddr? */
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return 37;
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}
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static inline int max_vaddr_bits_gk20a(void)
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{
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return 40; /* chopped for area? */
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}
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#if 0 /*related to addr bits above, concern below TBD on which is accurate */
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#define bar1_instance_block_shift_gk20a() (max_physaddr_bits_gk20a() -\
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bus_bar1_block_ptr_s())
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#else
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#define bar1_instance_block_shift_gk20a() bus_bar1_block_ptr_shift_v()
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#endif
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void gk20a_mm_dump_vm(struct vm_gk20a *vm,
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u64 va_begin, u64 va_end, char *label);
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int gk20a_mm_suspend(struct gk20a *g);
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phys_addr_t gk20a_get_phys_from_iova(struct device *d,
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dma_addr_t dma_addr);
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int gk20a_get_sgtable(struct device *d, struct sg_table **sgt,
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void *cpuva, dma_addr_t iova,
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size_t size);
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int gk20a_get_sgtable_from_pages(struct device *d, struct sg_table **sgt,
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struct page **pages, dma_addr_t iova,
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size_t size);
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void gk20a_free_sgtable(struct sg_table **sgt);
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u64 gk20a_mm_iova_addr(struct scatterlist *sgl);
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void gk20a_mm_ltc_isr(struct gk20a *g);
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bool gk20a_mm_mmu_debug_mode_enabled(struct gk20a *g);
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u64 gk20a_gmmu_map(struct vm_gk20a *vm,
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struct sg_table **sgt,
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u64 size,
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u32 flags,
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int rw_flag);
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void gk20a_gmmu_unmap(struct vm_gk20a *vm,
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u64 vaddr,
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u64 size,
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int rw_flag);
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u64 gk20a_vm_map(struct vm_gk20a *vm,
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struct mem_mgr *memmgr,
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struct mem_handle *r,
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u64 offset_align,
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u32 flags /*NVHOST_MAP_BUFFER_FLAGS_*/,
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int kind,
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struct sg_table **sgt,
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bool user_mapped,
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int rw_flag);
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/* unmap handle from kernel */
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void gk20a_vm_unmap(struct vm_gk20a *vm, u64 offset);
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/* get reference to all currently mapped buffers */
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int gk20a_vm_get_buffers(struct vm_gk20a *vm,
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struct mapped_buffer_node ***mapped_buffers,
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int *num_buffers);
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/* put references on the given buffers */
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void gk20a_vm_put_buffers(struct vm_gk20a *vm,
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struct mapped_buffer_node **mapped_buffers,
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int num_buffers);
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/* invalidate tlbs for the vm area */
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void gk20a_mm_tlb_invalidate(struct vm_gk20a *vm);
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/* find buffer corresponding to va */
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int gk20a_vm_find_buffer(struct vm_gk20a *vm, u64 gpu_va,
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struct mem_mgr **memmgr, struct mem_handle **r,
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u64 *offset);
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void gk20a_vm_get(struct vm_gk20a *vm);
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void gk20a_vm_put(struct vm_gk20a *vm);
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#endif /*_MM_GK20A_H_ */
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