379 lines
9.1 KiB
C
379 lines
9.1 KiB
C
/*
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* GK20A Graphics Engine
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*
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* Copyright (c) 2011-2013, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __GR_GK20A_H__
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#define __GR_GK20A_H__
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#include <linux/slab.h>
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#include "gr_ctx_gk20a.h"
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#define GR_IDLE_CHECK_DEFAULT 100 /* usec */
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#define GR_IDLE_CHECK_MAX 5000 /* usec */
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#define INVALID_SCREEN_TILE_ROW_OFFSET 0xFFFFFFFF
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#define INVALID_MAX_WAYS 0xFFFFFFFF
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enum /* global_ctx_buffer */ {
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CIRCULAR = 0,
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PAGEPOOL = 1,
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ATTRIBUTE = 2,
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CIRCULAR_VPR = 3,
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PAGEPOOL_VPR = 4,
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ATTRIBUTE_VPR = 5,
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GOLDEN_CTX = 6,
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NR_GLOBAL_CTX_BUF = 7
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};
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/* either ATTRIBUTE or ATTRIBUTE_VPR maps to ATTRIBUTE_VA */
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enum /*global_ctx_buffer_va */ {
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CIRCULAR_VA = 0,
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PAGEPOOL_VA = 1,
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ATTRIBUTE_VA = 2,
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GOLDEN_CTX_VA = 3,
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NR_GLOBAL_CTX_BUF_VA = 4
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};
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enum {
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WAIT_UCODE_LOOP,
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WAIT_UCODE_TIMEOUT,
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WAIT_UCODE_ERROR,
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WAIT_UCODE_OK
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};
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enum {
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GR_IS_UCODE_OP_EQUAL,
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GR_IS_UCODE_OP_NOT_EQUAL,
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GR_IS_UCODE_OP_AND,
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GR_IS_UCODE_OP_LESSER,
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GR_IS_UCODE_OP_LESSER_EQUAL,
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GR_IS_UCODE_OP_SKIP
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};
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enum {
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UCODE_HANDSHAKE_INIT_COMPLETE = 1,
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UCODE_HANDSHAKE_METHOD_FINISHED
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};
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enum {
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ELCG_RUN, /* clk always run, i.e. disable elcg */
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ELCG_STOP, /* clk is stopped */
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ELCG_AUTO /* clk will run when non-idle, standard elcg mode */
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};
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enum {
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BLCG_RUN, /* clk always run, i.e. disable blcg */
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BLCG_AUTO /* clk will run when non-idle, standard blcg mode */
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};
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#ifndef GR_GO_IDLE_BUNDLE
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#define GR_GO_IDLE_BUNDLE 0x0000e100 /* --V-B */
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#endif
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struct gr_channel_map_tlb_entry {
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u32 curr_ctx;
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u32 hw_chid;
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};
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struct gr_zcull_gk20a {
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u32 aliquot_width;
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u32 aliquot_height;
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u32 aliquot_size;
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u32 total_aliquots;
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u32 width_align_pixels;
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u32 height_align_pixels;
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u32 pixel_squares_by_aliquots;
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};
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struct gr_zcull_info {
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u32 width_align_pixels;
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u32 height_align_pixels;
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u32 pixel_squares_by_aliquots;
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u32 aliquot_total;
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u32 region_byte_multiplier;
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u32 region_header_size;
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u32 subregion_header_size;
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u32 subregion_width_align_pixels;
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u32 subregion_height_align_pixels;
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u32 subregion_count;
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};
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#define GK20A_ZBC_COLOR_VALUE_SIZE 4 /* RGBA */
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/* index zero reserved to indicate "not ZBCd" */
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#define GK20A_STARTOF_ZBC_TABLE 1
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/* match ltcs_ltss_dstg_zbc_index_address width (4) */
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#define GK20A_SIZEOF_ZBC_TABLE 16
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#define GK20A_ZBC_TABLE_SIZE (16 - 1)
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#define GK20A_ZBC_TYPE_INVALID 0
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#define GK20A_ZBC_TYPE_COLOR 1
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#define GK20A_ZBC_TYPE_DEPTH 2
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struct zbc_color_table {
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u32 color_ds[GK20A_ZBC_COLOR_VALUE_SIZE];
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u32 color_l2[GK20A_ZBC_COLOR_VALUE_SIZE];
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u32 format;
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u32 ref_cnt;
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};
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struct zbc_depth_table {
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u32 depth;
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u32 format;
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u32 ref_cnt;
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};
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struct zbc_entry {
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u32 color_ds[GK20A_ZBC_COLOR_VALUE_SIZE];
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u32 color_l2[GK20A_ZBC_COLOR_VALUE_SIZE];
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u32 depth;
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u32 type; /* color or depth */
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u32 format;
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};
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struct zbc_query_params {
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u32 color_ds[GK20A_ZBC_COLOR_VALUE_SIZE];
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u32 color_l2[GK20A_ZBC_COLOR_VALUE_SIZE];
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u32 depth;
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u32 ref_cnt;
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u32 format;
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u32 type; /* color or depth */
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u32 index_size; /* [out] size, [in] index */
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};
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struct gr_gk20a {
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struct gk20a *g;
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struct {
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bool dynamic;
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u32 buffer_size;
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u32 buffer_total_size;
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bool golden_image_initialized;
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u32 golden_image_size;
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u32 *local_golden_image;
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u32 zcull_ctxsw_image_size;
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u32 buffer_header_size;
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struct gr_ucode_gk20a ucode;
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struct av_list_gk20a sw_bundle_init;
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struct av_list_gk20a sw_method_init;
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struct aiv_list_gk20a sw_ctx_load;
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struct av_list_gk20a sw_non_ctx_load;
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struct {
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struct aiv_list_gk20a sys;
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struct aiv_list_gk20a gpc;
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struct aiv_list_gk20a tpc;
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struct aiv_list_gk20a zcull_gpc;
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struct aiv_list_gk20a ppc;
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struct aiv_list_gk20a pm_sys;
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struct aiv_list_gk20a pm_gpc;
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struct aiv_list_gk20a pm_tpc;
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} ctxsw_regs;
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int regs_base_index;
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bool valid;
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} ctx_vars;
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struct mutex ctx_mutex; /* protect golden ctx init */
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struct mutex fecs_mutex; /* protect fecs method */
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#define GR_NETLIST_DYNAMIC -1
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#define GR_NETLIST_STATIC_A 'A'
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int netlist;
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wait_queue_head_t init_wq;
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int initialized;
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u32 num_fbps;
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u32 max_gpc_count;
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u32 max_fbps_count;
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u32 max_tpc_per_gpc_count;
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u32 max_zcull_per_gpc_count;
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u32 max_tpc_count;
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u32 sys_count;
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u32 gpc_count;
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u32 pe_count_per_gpc;
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u32 ppc_count;
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u32 *gpc_ppc_count;
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u32 tpc_count;
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u32 *gpc_tpc_count;
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u32 zcb_count;
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u32 *gpc_zcb_count;
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u32 *pes_tpc_count[2];
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u32 *pes_tpc_mask[2];
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u32 *gpc_skip_mask;
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u32 bundle_cb_default_size;
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u32 min_gpm_fifo_depth;
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u32 bundle_cb_token_limit;
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u32 attrib_cb_default_size;
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u32 attrib_cb_size;
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u32 alpha_cb_default_size;
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u32 alpha_cb_size;
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u32 timeslice_mode;
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struct mem_desc global_ctx_buffer[NR_GLOBAL_CTX_BUF];
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struct mmu_desc mmu_wr_mem;
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u32 mmu_wr_mem_size;
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struct mmu_desc mmu_rd_mem;
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u32 mmu_rd_mem_size;
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u8 *map_tiles;
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u32 map_tile_count;
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u32 map_row_offset;
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#define COMP_TAG_LINE_SIZE_SHIFT (17) /* one tag covers 128K */
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#define COMP_TAG_LINE_SIZE (1 << COMP_TAG_LINE_SIZE_SHIFT)
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u32 max_comptag_mem; /* max memory size (MB) for comptag */
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struct compbit_store_desc compbit_store;
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struct nvhost_allocator comp_tags;
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struct gr_zcull_gk20a zcull;
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struct zbc_color_table zbc_col_tbl[GK20A_ZBC_TABLE_SIZE];
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struct zbc_depth_table zbc_dep_tbl[GK20A_ZBC_TABLE_SIZE];
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s32 max_default_color_index;
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s32 max_default_depth_index;
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s32 max_used_color_index;
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s32 max_used_depth_index;
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u32 status_disable_mask;
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#define GR_CHANNEL_MAP_TLB_SIZE 2 /* must of power of 2 */
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struct gr_channel_map_tlb_entry chid_tlb[GR_CHANNEL_MAP_TLB_SIZE];
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u32 channel_tlb_flush_index;
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spinlock_t ch_tlb_lock;
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void (*remove_support)(struct gr_gk20a *gr);
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bool sw_ready;
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};
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void gk20a_fecs_dump_falcon_stats(struct gk20a *g);
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struct gk20a_ctxsw_ucode_segment {
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u32 offset;
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u32 size;
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};
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struct gk20a_ctxsw_ucode_inst {
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u32 boot_entry;
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u32 boot_imem_offset;
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struct gk20a_ctxsw_ucode_segment boot;
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struct gk20a_ctxsw_ucode_segment code;
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struct gk20a_ctxsw_ucode_segment data;
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};
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struct gk20a_ctxsw_ucode_info {
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u64 *p_va;
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struct mem_desc inst_blk_desc;
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struct mem_desc surface_desc;
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u64 ucode_va;
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struct gk20a_ctxsw_ucode_inst fecs;
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struct gk20a_ctxsw_ucode_inst gpcs;
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};
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struct gk20a_ctxsw_bootloader_desc {
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u32 bootloader_start_offset;
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u32 bootloader_size;
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u32 bootloader_imem_offset;
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u32 bootloader_entry_point;
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};
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int gk20a_init_gr_support(struct gk20a *g);
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int gk20a_gr_reset(struct gk20a *g);
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void gk20a_gr_wait_initialized(struct gk20a *g);
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int gk20a_init_gr_channel(struct channel_gk20a *ch_gk20a);
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int gr_gk20a_init_ctx_vars(struct gk20a *g, struct gr_gk20a *gr);
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struct nvhost_alloc_obj_ctx_args;
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struct nvhost_free_obj_ctx_args;
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int gk20a_alloc_obj_ctx(struct channel_gk20a *c,
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struct nvhost_alloc_obj_ctx_args *args);
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int gk20a_free_obj_ctx(struct channel_gk20a *c,
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struct nvhost_free_obj_ctx_args *args);
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void gk20a_free_channel_ctx(struct channel_gk20a *c);
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int gk20a_gr_isr(struct gk20a *g);
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int gk20a_gr_clear_comptags(struct gk20a *g, u32 min, u32 max);
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/* zcull */
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u32 gr_gk20a_get_ctxsw_zcull_size(struct gk20a *g, struct gr_gk20a *gr);
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int gr_gk20a_bind_ctxsw_zcull(struct gk20a *g, struct gr_gk20a *gr,
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struct channel_gk20a *c, u64 zcull_va, u32 mode);
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int gr_gk20a_get_zcull_info(struct gk20a *g, struct gr_gk20a *gr,
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struct gr_zcull_info *zcull_params);
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/* zbc */
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int gr_gk20a_add_zbc(struct gk20a *g, struct gr_gk20a *gr,
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struct zbc_entry *zbc_val);
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int gr_gk20a_query_zbc(struct gk20a *g, struct gr_gk20a *gr,
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struct zbc_query_params *query_params);
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int gk20a_gr_zbc_set_table(struct gk20a *g, struct gr_gk20a *gr,
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struct zbc_entry *zbc_val);
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/* pmu */
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int gr_gk20a_fecs_get_reglist_img_size(struct gk20a *g, u32 *size);
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int gr_gk20a_fecs_set_reglist_bind_inst(struct gk20a *g, phys_addr_t addr);
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int gr_gk20a_fecs_set_reglist_virtual_addr(struct gk20a *g, u64 pmu_va);
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void gr_gk20a_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine);
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void gr_gk20a_init_blcg_mode(struct gk20a *g, u32 mode, u32 engine);
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void gr_gk20a_pmu_save_zbc(struct gk20a *g, u32 entries);
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/* sm */
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bool gk20a_gr_sm_debugger_attached(struct gk20a *g);
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#define gr_gk20a_elpg_protected_call(g, func) \
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({ \
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int err = 0; \
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if (support_gk20a_pmu()) \
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err = gk20a_pmu_disable_elpg(g); \
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if (!err) { \
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err = func; \
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if (support_gk20a_pmu()) \
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gk20a_pmu_enable_elpg(g); \
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} \
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err; \
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})
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int gk20a_gr_suspend(struct gk20a *g);
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struct nvhost_dbg_gpu_reg_op;
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int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch,
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struct nvhost_dbg_gpu_reg_op *ctx_ops, u32 num_ops,
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u32 num_ctx_wr_ops, u32 num_ctx_rd_ops);
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int gr_gk20a_get_ctx_buffer_offsets(struct gk20a *g,
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u32 addr,
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u32 max_offsets,
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u32 *offsets, u32 *offset_addrs,
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u32 *num_offsets,
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bool is_quad, u32 quad);
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#endif /*__GR_GK20A_H__*/
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