359 lines
10 KiB
C
359 lines
10 KiB
C
/*
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* drivers/video/tegra/host/gk20a/gk20a.h
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*
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* GK20A Graphics
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*
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* Copyright (c) 2011-2013, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#ifndef _NVHOST_GK20A_H_
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#define _NVHOST_GK20A_H_
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struct gk20a;
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struct fifo_gk20a;
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struct channel_gk20a;
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struct gr_gk20a;
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struct sim_gk20a;
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#include <linux/tegra-soc.h>
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#include <linux/spinlock.h>
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#include "clk_gk20a.h"
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#include "fifo_gk20a.h"
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#include "gr_gk20a.h"
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#include "sim_gk20a.h"
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#include "intr_gk20a.h"
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#include "pmu_gk20a.h"
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#include "priv_ring_gk20a.h"
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#include "therm_gk20a.h"
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#include "../../../../../arch/arm/mach-tegra/iomap.h"
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extern struct platform_device tegra_gk20a_device;
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extern struct nvhost_device_data tegra_gk20a_info;
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static inline bool is_gk20a_module(struct platform_device *dev)
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{
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return &tegra_gk20a_info == nvhost_get_devdata(dev);
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}
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struct cooling_device_gk20a {
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struct thermal_cooling_device *gk20a_cooling_dev;
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unsigned int gk20a_freq_state;
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unsigned int gk20a_freq_table_size;
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struct gk20a *g;
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};
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struct gpu_ops {
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struct pmu_v {
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/*used for change of enum zbc update cmd id from ver 0 to ver1*/
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u32 cmd_id_zbc_table_update;
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u32 (*get_pmu_cmdline_args_size)(struct pmu_gk20a *pmu);
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void (*set_pmu_cmdline_args_cpu_freq)(struct pmu_gk20a *pmu,
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u32 freq);
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void * (*get_pmu_cmdline_args_ptr)(struct pmu_gk20a *pmu);
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u32 (*get_pmu_allocation_struct_size)(struct pmu_gk20a *pmu);
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void (*set_pmu_allocation_ptr)(struct pmu_gk20a *pmu,
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void **pmu_alloc_ptr, void *assign_ptr);
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void (*pmu_allocation_set_dmem_size)(struct pmu_gk20a *pmu,
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void *pmu_alloc_ptr, u16 size);
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u16 (*pmu_allocation_get_dmem_size)(struct pmu_gk20a *pmu,
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void *pmu_alloc_ptr);
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u32 (*pmu_allocation_get_dmem_offset)(struct pmu_gk20a *pmu,
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void *pmu_alloc_ptr);
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u32 * (*pmu_allocation_get_dmem_offset_addr)(
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struct pmu_gk20a *pmu, void *pmu_alloc_ptr);
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void (*pmu_allocation_set_dmem_offset)(struct pmu_gk20a *pmu,
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void *pmu_alloc_ptr, u32 offset);
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void (*get_pmu_init_msg_pmu_queue_params)(
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struct pmu_queue *queue, u32 id,
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void *pmu_init_msg);
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void *(*get_pmu_msg_pmu_init_msg_ptr)(
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struct pmu_init_msg *init);
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u16 (*get_pmu_init_msg_pmu_sw_mg_off)(
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union pmu_init_msg_pmu *init_msg);
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u16 (*get_pmu_init_msg_pmu_sw_mg_size)(
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union pmu_init_msg_pmu *init_msg);
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u32 (*get_pmu_perfmon_cmd_start_size)(void);
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int (*get_perfmon_cmd_start_offsetofvar)(
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enum pmu_perfmon_cmd_start_fields field);
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void (*perfmon_start_set_cmd_type)(struct pmu_perfmon_cmd *pc,
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u8 value);
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void (*perfmon_start_set_group_id)(struct pmu_perfmon_cmd *pc,
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u8 value);
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void (*perfmon_start_set_state_id)(struct pmu_perfmon_cmd *pc,
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u8 value);
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void (*perfmon_start_set_flags)(struct pmu_perfmon_cmd *pc,
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u8 value);
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u8 (*perfmon_start_get_flags)(struct pmu_perfmon_cmd *pc);
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u32 (*get_pmu_perfmon_cmd_init_size)(void);
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int (*get_perfmon_cmd_init_offsetofvar)(
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enum pmu_perfmon_cmd_start_fields field);
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void (*perfmon_cmd_init_set_sample_buffer)(
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struct pmu_perfmon_cmd *pc, u16 value);
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void (*perfmon_cmd_init_set_dec_cnt)(
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struct pmu_perfmon_cmd *pc, u8 value);
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void (*perfmon_cmd_init_set_base_cnt_id)(
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struct pmu_perfmon_cmd *pc, u8 value);
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void (*perfmon_cmd_init_set_samp_period_us)(
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struct pmu_perfmon_cmd *pc, u32 value);
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void (*perfmon_cmd_init_set_num_cnt)(struct pmu_perfmon_cmd *pc,
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u8 value);
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void (*perfmon_cmd_init_set_mov_avg)(struct pmu_perfmon_cmd *pc,
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u8 value);
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void *(*get_pmu_seq_in_a_ptr)(
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struct pmu_sequence *seq);
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void *(*get_pmu_seq_out_a_ptr)(
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struct pmu_sequence *seq);
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} pmu_ver;
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};
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struct gk20a {
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struct nvhost_master *host;
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struct platform_device *dev;
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struct resource *reg_mem;
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void __iomem *regs;
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struct resource *bar1_mem;
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void __iomem *bar1;
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bool power_on;
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bool irq_requested;
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struct clk_gk20a clk;
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struct fifo_gk20a fifo;
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struct gr_gk20a gr;
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struct sim_gk20a sim;
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struct mm_gk20a mm;
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struct pmu_gk20a pmu;
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struct cooling_device_gk20a gk20a_cdev;
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/* Save pmu fw here so that it lives cross suspend/resume.
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pmu suspend destroys all pmu sw/hw states. Loading pmu
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fw in resume crashes when the resume is from sys_exit. */
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const struct firmware *pmu_fw;
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u32 gr_idle_timeout_default;
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u32 timeouts_enabled;
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bool slcg_enabled;
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bool blcg_enabled;
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bool elcg_enabled;
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bool elpg_enabled;
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#ifdef CONFIG_DEBUG_FS
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spinlock_t debugfs_lock;
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struct dentry *debugfs_ltc_enabled;
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struct dentry *debugfs_timeouts_enabled;
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struct dentry *debugfs_gr_idle_timeout_default;
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#endif
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struct gk20a_ctxsw_ucode_info ctxsw_ucode_info;
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/* held while manipulating # of debug/profiler sessions present */
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/* also prevents debug sessions from attaching until released */
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struct mutex dbg_sessions_lock;
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int dbg_sessions; /* number attached */
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int dbg_powergating_disabled_refcount; /*refcount for pg disable */
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void (*remove_support)(struct platform_device *);
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u64 pg_ingating_time_us;
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u64 pg_ungating_time_us;
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u32 pg_gating_cnt;
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spinlock_t mc_enable_lock;
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struct gpu_ops ops;
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};
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static inline unsigned long gk20a_get_gr_idle_timeout(struct gk20a *g)
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{
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return g->timeouts_enabled ?
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g->gr_idle_timeout_default : MAX_SCHEDULE_TIMEOUT;
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}
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static inline struct gk20a *get_gk20a(struct platform_device *dev)
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{
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return (struct gk20a *)nvhost_get_private_data(dev);
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}
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enum BAR0_DEBUG_OPERATION {
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BARO_ZERO_NOP = 0,
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OP_END = 'DONE',
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BAR0_READ32 = '0R32',
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BAR0_WRITE32 = '0W32',
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};
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struct share_buffer_head {
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enum BAR0_DEBUG_OPERATION operation;
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/* size of the operation item */
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u32 size;
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u32 completed;
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u32 failed;
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u64 context;
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u64 completion_callback;
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};
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struct gk20a_cyclestate_buffer_elem {
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struct share_buffer_head head;
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/* in */
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u64 p_data;
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u64 p_done;
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u32 offset_bar0;
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u16 first_bit;
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u16 last_bit;
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/* out */
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/* keep 64 bits to be consistent */
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u64 data;
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};
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extern const struct nvhost_as_moduleops tegra_gk20a_as_ops;
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/* register accessors */
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static inline void gk20a_writel(struct gk20a *g, u32 r, u32 v)
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{
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nvhost_dbg(dbg_reg, " r=0x%x v=0x%x", r, v);
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writel(v, g->regs + r);
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}
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static inline u32 gk20a_readl(struct gk20a *g, u32 r)
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{
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u32 v = readl(g->regs + r);
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nvhost_dbg(dbg_reg, " r=0x%x v=0x%x", r, v);
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return v;
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}
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static inline void gk20a_bar1_writel(struct gk20a *g, u32 b, u32 v)
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{
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nvhost_dbg(dbg_reg, " b=0x%x v=0x%x", b, v);
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writel(v, g->bar1 + b);
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}
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static inline u32 gk20a_bar1_readl(struct gk20a *g, u32 b)
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{
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u32 v = readl(g->bar1 + b);
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nvhost_dbg(dbg_reg, " b=0x%x v=0x%x", b, v);
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return v;
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}
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/* convenience */
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static inline struct device *dev_from_gk20a(struct gk20a *g)
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{
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return &g->dev->dev;
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}
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static inline struct nvhost_syncpt *syncpt_from_gk20a(struct gk20a *g)
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{
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return &(nvhost_get_host(g->dev)->syncpt);
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}
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static inline struct mem_mgr *mem_mgr_from_g(struct gk20a *g)
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{
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return nvhost_get_host(g->dev)->memmgr;
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}
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static inline u32 u64_hi32(u64 n)
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{
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return (u32)((n >> 32) & ~(u32)0);
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}
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static inline u32 u64_lo32(u64 n)
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{
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return (u32)(n & ~(u32)0);
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}
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static inline u32 set_field(u32 val, u32 mask, u32 field)
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{
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return (val & ~mask) | field;
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}
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/* invalidate channel lookup tlb */
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static inline void gk20a_gr_flush_channel_tlb(struct gr_gk20a *gr)
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{
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spin_lock(&gr->ch_tlb_lock);
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memset(gr->chid_tlb, 0,
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sizeof(struct gr_channel_map_tlb_entry) *
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GR_CHANNEL_MAP_TLB_SIZE);
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spin_unlock(&gr->ch_tlb_lock);
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}
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/*
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* This function can be called from two places, whichever comes first.
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* 1. nvhost calls this for gk20a driver init when client opens first gk20a
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* channel.
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* 2. client opens gk20a ctrl node.
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*/
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int nvhost_gk20a_init(struct platform_device *dev);
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void nvhost_gk20a_deinit(struct platform_device *dev);
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/* classes that the device supports */
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/* TBD: get these from an open-sourced SDK? */
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enum {
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KEPLER_C = 0xA297,
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FERMI_TWOD_A = 0x902D,
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KEPLER_COMPUTE_A = 0xA0C0,
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KEPLER_INLINE_TO_MEMORY_A = 0xA040,
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KEPLER_DMA_COPY_A = 0xA0B5, /*not sure about this one*/
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};
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#if defined(CONFIG_TEGRA_GK20A_PMU)
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static inline int support_gk20a_pmu(void)
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{
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return 1;
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}
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#else
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static inline int support_gk20a_pmu(void)
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{
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return 0;
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}
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#endif
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int nvhost_gk20a_finalize_poweron(struct platform_device *dev);
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int nvhost_gk20a_prepare_poweroff(struct platform_device *dev);
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void nvhost_gk20a_scale_notify_idle(struct platform_device *pdev);
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void nvhost_gk20a_scale_notify_busy(struct platform_device *pdev);
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void nvhost_gk20a_scale_init(struct platform_device *pdev);
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void nvhost_gk20a_scale_deinit(struct platform_device *pdev);
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void gk20a_create_sysfs(struct platform_device *dev);
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#ifdef CONFIG_DEBUG_FS
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int clk_gk20a_debugfs_init(struct platform_device *dev);
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#endif
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extern const struct file_operations tegra_gk20a_ctrl_ops;
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extern const struct file_operations tegra_gk20a_dbg_gpu_ops;
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extern const struct file_operations tegra_gk20a_prof_gpu_ops;
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struct nvhost_hwctx_handler *nvhost_gk20a_alloc_hwctx_handler(u32 syncpt,
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u32 waitbase, struct nvhost_channel *ch);
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#define GK20A_BAR0_IORESOURCE_MEM 0
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#define GK20A_BAR1_IORESOURCE_MEM 1
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#define GK20A_SIM_IORESOURCE_MEM 2
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#define TEGRA_GK20A_SIM_BASE 0x538F0000 /*tbd: get from iomap.h */
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#define TEGRA_GK20A_SIM_SIZE 0x1000 /*tbd: this is a high-side guess */
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#define TEGRA_GK20A_BAR0_BASE 0x57000000
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#define TEGRA_GK20A_BAR0_SIZE SZ_16M
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#define TEGRA_GK20A_BAR1_BASE 0x58000000
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#define TEGRA_GK20A_BAR1_SIZE SZ_16M
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void gk20a_busy(struct platform_device *pdev);
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void gk20a_idle(struct platform_device *pdev);
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void gk20a_disable(struct gk20a *g, u32 units);
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void gk20a_enable(struct gk20a *g, u32 units);
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void gk20a_reset(struct gk20a *g, u32 units);
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#endif /* _NVHOST_GK20A_H_ */
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