223 lines
5.9 KiB
C
223 lines
5.9 KiB
C
/*
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* drivers/video/tegra/host/gk20a/channel_gk20a.h
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*
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* GK20A graphics channel
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*
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* Copyright (c) 2011-2013, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#ifndef __CHANNEL_GK20A_H__
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#define __CHANNEL_GK20A_H__
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#include <linux/log2.h>
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#include <linux/slab.h>
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#include <linux/wait.h>
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#include <linux/mutex.h>
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#include <linux/nvhost_ioctl.h>
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struct gk20a;
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struct gr_gk20a;
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struct mem_mgr;
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struct mem_handle;
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#include "nvhost_channel.h"
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#include "nvhost_hwctx.h"
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#include "cdma_gk20a.h"
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#include "mm_gk20a.h"
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#include "gr_gk20a.h"
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struct gpfifo {
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u32 entry0;
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u32 entry1;
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};
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struct notification {
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struct {
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u32 nanoseconds[2];
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} timestamp;
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u32 info32;
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u16 info16;
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u16 status;
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};
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struct fence {
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u32 hw_chid;
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u32 syncpt_val;
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};
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/* contexts associated with a channel */
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struct channel_ctx_gk20a {
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struct gr_ctx_desc gr_ctx;
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struct pm_ctx_desc pm_ctx;
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struct patch_desc patch_ctx;
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struct zcull_ctx_desc zcull_ctx;
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u64 global_ctx_buffer_va[NR_GLOBAL_CTX_BUF_VA];
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bool global_ctx_buffer_mapped;
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};
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struct channel_gk20a_job {
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struct mapped_buffer_node **mapped_buffers;
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int num_mapped_buffers;
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struct nvhost_fence fence;
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struct list_head list;
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};
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/* this is the priv element of struct nvhost_channel */
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struct channel_gk20a {
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struct gk20a *g;
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bool in_use;
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int hw_chid;
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bool bound;
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bool first_init;
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bool vpr;
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pid_t pid;
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struct mem_mgr *memmgr;
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struct nvhost_channel *ch;
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struct nvhost_hwctx *hwctx;
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struct list_head jobs;
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struct mutex jobs_lock;
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struct vm_gk20a *vm;
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struct gpfifo_desc gpfifo;
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struct channel_ctx_gk20a ch_ctx;
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struct inst_desc inst_block;
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struct mem_desc_sub ramfc;
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void *userd_cpu_va;
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u64 userd_iova;
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u64 userd_gpu_va;
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s32 num_objects;
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struct priv_cmd_queue priv_cmd_q;
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wait_queue_head_t notifier_wq;
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wait_queue_head_t semaphore_wq;
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wait_queue_head_t submit_wq;
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u32 timeout_accumulated_ms;
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u32 timeout_gpfifo_get;
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bool cmds_pending;
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struct {
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bool valid;
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bool wfi; /* was issued with preceding wfi */
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u32 syncpt_value;
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u32 syncpt_id;
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} last_submit_fence;
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void (*remove_support)(struct channel_gk20a *);
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#if defined(CONFIG_TEGRA_GPU_CYCLE_STATS)
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struct {
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void *cyclestate_buffer;
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u32 cyclestate_buffer_size;
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struct mem_handle *cyclestate_buffer_handler;
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struct mutex cyclestate_buffer_mutex;
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} cyclestate;
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#endif
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struct mutex dbg_s_lock;
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struct list_head dbg_s_list;
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};
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static inline bool gk20a_channel_as_bound(struct channel_gk20a *ch)
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{
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return !!ch->hwctx->as_share;
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}
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int channel_gk20a_commit_va(struct channel_gk20a *c);
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struct nvhost_unmap_buffer_args;
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struct nvhost_zbc_query_table_args;
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struct nvhost_fence;
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struct nvhost_alloc_gpfifo_args;
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struct nvhost_map_buffer_args;
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struct nvhost_wait_args;
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struct nvhost_zcull_bind_args;
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struct nvhost_gpfifo;
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struct nvhost_zbc_set_table_args;
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struct nvhost_cycle_stats_args;
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struct nvhost_set_priority_args;
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#if defined(CONFIG_TEGRA_GK20A)
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void gk20a_channel_update(struct channel_gk20a *c);
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#else
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static inline void gk20a_channel_update(struct channel_gk20a *c)
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{
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}
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#endif
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int gk20a_init_channel_support(struct gk20a *, u32 chid);
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int gk20a_channel_init(struct nvhost_channel *ch, struct nvhost_master *host,
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int index);
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int gk20a_channel_alloc_obj(struct nvhost_channel *channel,
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u32 class_num, u32 *obj_id, u32 vaspace_share);
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int gk20a_channel_free_obj(struct nvhost_channel *channel,
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u32 obj_id);
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struct nvhost_hwctx *gk20a_open_channel(struct nvhost_channel *ch,
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struct nvhost_hwctx *ctx);
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int gk20a_alloc_channel_gpfifo(struct channel_gk20a *c,
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struct nvhost_alloc_gpfifo_args *args);
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int gk20a_submit_channel_gpfifo(struct channel_gk20a *c,
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struct nvhost_gpfifo *gpfifo, u32 num_entries,
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struct nvhost_fence *fence, u32 flags);
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void gk20a_free_channel(struct nvhost_hwctx *ctx, bool finish);
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int gk20a_init_error_notifier(struct nvhost_hwctx *ctx, u32 memhandle,
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u64 offset);
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bool gk20a_channel_update_and_check_timeout(struct channel_gk20a *ch,
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u32 timeout_delta_ms);
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void gk20a_free_error_notifiers(struct nvhost_hwctx *ctx);
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void gk20a_disable_channel(struct channel_gk20a *ch,
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bool wait_for_finish,
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unsigned long finish_timeout);
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void gk20a_disable_channel_no_update(struct channel_gk20a *ch);
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int gk20a_channel_finish(struct channel_gk20a *ch, unsigned long timeout);
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void gk20a_set_error_notifier(struct nvhost_hwctx *ctx, __u32 error);
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void gk20a_set_error_notifier_locked(struct nvhost_hwctx *ctx, __u32 error);
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int gk20a_channel_wait(struct channel_gk20a *ch,
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struct nvhost_wait_args *args);
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int gk20a_channel_zcull_bind(struct channel_gk20a *ch,
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struct nvhost_zcull_bind_args *args);
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int gk20a_channel_zbc_set_table(struct channel_gk20a *ch,
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struct nvhost_zbc_set_table_args *args);
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int gk20a_channel_zbc_query_table(struct channel_gk20a *ch,
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struct nvhost_zbc_query_table_args *args);
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int gk20a_channel_set_priority(struct channel_gk20a *ch,
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u32 priority);
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#if defined(CONFIG_TEGRA_GPU_CYCLE_STATS)
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int gk20a_channel_cycle_stats(struct channel_gk20a *ch,
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struct nvhost_cycle_stats_args *args);
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#endif
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int gk20a_channel_suspend(struct gk20a *g);
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int gk20a_channel_resume(struct gk20a *g);
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static inline
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struct mem_mgr *gk20a_channel_mem_mgr(struct channel_gk20a *ch)
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{
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return ch->hwctx->memmgr;
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}
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static inline
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struct nvhost_master *host_from_gk20a_channel(struct channel_gk20a *ch)
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{
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return nvhost_get_host(ch->ch->dev);
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}
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#endif /*__CHANNEL_GK20A_H__*/
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