404 lines
12 KiB
C
404 lines
12 KiB
C
/*
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* drivers/video/tegra/dc/dp.h
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*
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* Copyright (c) 2011-2014, NVIDIA CORPORATION, All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __DRIVER_VIDEO_TEGRA_DC_DP_H__
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#define __DRIVER_VIDEO_TEGRA_DC_DP_H__
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#include <linux/clk.h>
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#include "sor.h"
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#include "dc_priv.h"
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#include "dpaux_regs.h"
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#define DP_AUX_DEFER_MAX_TRIES 7
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#define DP_AUX_TIMEOUT_MAX_TRIES 2
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#define DP_POWER_ON_MAX_TRIES 3
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#define DP_CLOCK_RECOVERY_MAX_TRIES 7
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#define DP_CLOCK_RECOVERY_TOT_TRIES 15
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#define DP_AUX_MAX_BYTES 16
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#define DP_LCDVCC_TO_HPD_DELAY_MS 200
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#define DP_AUX_TIMEOUT_MS 40
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#define DP_DPCP_RETRY_SLEEP_NS 400
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static const u32 tegra_dp_vs_regs[][4][4] = {
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/* postcursor2 L0 */
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{
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/* pre-emphasis: L0, L1, L2, L3 */
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{0x13, 0x19, 0x1e, 0x28}, /* voltage swing: L0 */
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{0x1e, 0x25, 0x2d}, /* L1 */
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{0x28, 0x32}, /* L2 */
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{0x3c}, /* L3 */
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},
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/* postcursor2 L1 */
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{
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{0x12, 0x17, 0x1b, 0x25},
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{0x1c, 0x23, 0x2a},
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{0x25, 0x2f},
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{0x39},
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},
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/* postcursor2 L2 */
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{
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{0x12, 0x16, 0x1a, 0x22},
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{0x1b, 0x20, 0x27},
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{0x24, 0x2d},
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{0x36},
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},
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/* postcursor2 L3 */
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{
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{0x11, 0x14, 0x17, 0x1f},
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{0x19, 0x1e, 0x24},
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{0x22, 0x2a},
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{0x32},
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},
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};
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static const u32 tegra_dp_pe_regs[][4][4] = {
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/* postcursor2 L0 */
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{
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/* pre-emphasis: L0, L1, L2, L3 */
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{0x00, 0x09, 0x13, 0x25}, /* voltage swing: L0 */
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{0x00, 0x0f, 0x1e}, /* L1 */
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{0x00, 0x14}, /* L2 */
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{0x00}, /* L3 */
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},
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/* postcursor2 L1 */
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{
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{0x00, 0x0a, 0x14, 0x28},
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{0x00, 0x0f, 0x1e},
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{0x00, 0x14},
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{0x00},
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},
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/* postcursor2 L2 */
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{
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{0x00, 0x0a, 0x14, 0x28},
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{0x00, 0x0f, 0x1e},
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{0x00, 0x14},
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{0x00},
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},
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/* postcursor2 L3 */
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{
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{0x00, 0x0a, 0x14, 0x28},
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{0x00, 0x0f, 0x1e},
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{0x00, 0x14},
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{0x00},
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},
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};
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static const u32 tegra_dp_pc_regs[][4][4] = {
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/* postcursor2 L0 */
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{
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/* pre-emphasis: L0, L1, L2, L3 */
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{0x00, 0x00, 0x00, 0x00}, /* voltage swing: L0 */
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{0x00, 0x00, 0x00}, /* L1 */
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{0x00, 0x00}, /* L2 */
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{0x00}, /* L3 */
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},
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/* postcursor2 L1 */
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{
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{0x02, 0x02, 0x04, 0x05},
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{0x02, 0x04, 0x05},
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{0x04, 0x05},
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{0x05},
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},
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/* postcursor2 L2 */
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{
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{0x04, 0x05, 0x08, 0x0b},
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{0x05, 0x09, 0x0b},
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{0x08, 0x0a},
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{0x0b},
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},
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/* postcursor2 L3 */
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{
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{0x05, 0x09, 0x0b, 0x12},
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{0x09, 0x0d, 0x12},
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{0x0b, 0x0f},
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{0x12},
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},
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};
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static const u32 tegra_dp_tx_pu[][4][4] = {
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/* postcursor2 L0 */
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{
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/* pre-emphasis: L0, L1, L2, L3 */
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{0x20, 0x30, 0x40, 0x60}, /* voltage swing: L0 */
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{0x30, 0x40, 0x60}, /* L1 */
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{0x40, 0x60}, /* L2 */
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{0x60}, /* L3 */
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},
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/* postcursor2 L1 */
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{
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{0x20, 0x20, 0x30, 0x50},
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{0x30, 0x40, 0x50},
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{0x40, 0x50},
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{0x60},
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},
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/* postcursor2 L2 */
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{
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{0x20, 0x20, 0x30, 0x40},
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{0x30, 0x30, 0x40},
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{0x40, 0x50},
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{0x60},
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},
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/* postcursor2 L3 */
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{
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{0x20, 0x20, 0x20, 0x40},
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{0x30, 0x30, 0x40},
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{0x40, 0x40},
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{0x60},
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},
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};
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enum {
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drive_current_Level0 = 0,
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drive_current_Level1 = 1,
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drive_current_Level2 = 2,
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drive_current_Level3 = 3,
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};
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enum {
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preemphasis_disabled = 0,
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preemphasis_Level1 = 1,
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preemphasis_Level2 = 2,
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preemphasis_Level3 = 3,
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};
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enum {
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post_cursor2_Level0 = 0,
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post_cursor2_Level1 = 1,
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post_cursor2_Level2 = 2,
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post_cursor2_Level3 = 3,
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post_cursor2_Supported
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};
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static inline int tegra_dp_is_max_vs(u32 pe, u32 vs)
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{
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return (vs < (drive_current_Level3 - pe)) ? 0 : 1;
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}
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static inline int tegra_dp_is_max_pe(u32 pe, u32 vs)
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{
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return (pe < (preemphasis_Level3 - vs)) ? 0 : 1;
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}
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static inline int tegra_dp_is_max_pc(u32 pc)
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{
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return (pc < post_cursor2_Level3) ? 0 : 1;
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}
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/* the +10ms is the time for power rail going up from 10-90% or
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90%-10% on powerdown */
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/* Time from power-rail is turned on and aux/12c-over-aux is available */
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#define EDP_PWR_ON_TO_AUX_TIME_MS (200+10)
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/* Time from power-rail is turned on and MainLink is available for LT */
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#define EDP_PWR_ON_TO_ML_TIME_MS (200+10)
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/* Time from turning off power to turn-it on again (does not include post
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poweron time) */
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#define EDP_PWR_OFF_TO_ON_TIME_MS (500+10)
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struct tegra_dc_dp_data {
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struct tegra_dc *dc;
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struct tegra_dc_sor_data *sor;
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u32 irq;
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struct resource *aux_base_res;
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void __iomem *aux_base;
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struct clk *clk; /* dpaux clock */
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struct work_struct lt_work;
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u8 revision;
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struct tegra_dc_mode *mode;
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struct tegra_dc_dp_link_config link_cfg;
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bool enabled;
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bool suspended;
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struct tegra_edid *dp_edid;
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struct completion hpd_plug;
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struct delayed_work sink_status_work;
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};
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/* DPCD definitions */
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#define NV_DPCD_REV (0x00000000)
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#define NV_DPCD_REV_MAJOR_SHIFT (4)
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#define NV_DPCD_REV_MAJOR_MASK (0xf << 4)
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#define NV_DPCD_REV_MINOR_SHIFT (0)
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#define NV_DPCD_REV_MINOR_MASK (0xf)
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#define NV_DPCD_MAX_LINK_BANDWIDTH (0x00000001)
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#define NV_DPCD_MAX_LINK_BANDWIDTH_VAL_1_62_GPBS (0x00000006)
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#define NV_DPCD_MAX_LINK_BANDWIDTH_VAL_2_70_GPBS (0x0000000a)
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#define NV_DPCD_MAX_LINK_BANDWIDTH_VAL_5_40_GPBS (0x00000014)
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#define NV_DPCD_MAX_LANE_COUNT (0x00000002)
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#define NV_DPCD_MAX_LANE_COUNT_MASK (0x1f)
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#define NV_DPCD_MAX_LANE_COUNT_LANE_1 (0x00000001)
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#define NV_DPCD_MAX_LANE_COUNT_LANE_2 (0x00000002)
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#define NV_DPCD_MAX_LANE_COUNT_LANE_4 (0x00000004)
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#define NV_DPCD_MAX_LANE_COUNT_TPS3_SUPPORTED_YES (0x00000001 << 6)
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#define NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_NO (0x00000000 << 7)
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#define NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_YES (0x00000001 << 7)
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#define NV_DPCD_MAX_DOWNSPREAD (0x00000003)
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#define NV_DPCD_MAX_DOWNSPREAD_VAL_NONE (0x00000000)
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#define NV_DPCD_MAX_DOWNSPREAD_VAL_0_5_PCT (0x00000001)
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#define NV_DPCD_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT_F (0x00000000 << 6)
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#define NV_DPCD_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT_T (0x00000001 << 6)
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#define NV_DPCD_EDP_CONFIG_CAP (0x0000000D)
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#define NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_NO (0x00000000)
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#define NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_YES (0x00000001)
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#define NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_NO (0x00000000 << 1)
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#define NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_YES (0x00000001 << 1)
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#define NV_DPCD_LINK_BANDWIDTH_SET (0x00000100)
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#define NV_DPCD_LANE_COUNT_SET (0x00000101)
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#define NV_DPCD_LANE_COUNT_SET_ENHANCEDFRAMING_F (0x00000000 << 7)
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#define NV_DPCD_LANE_COUNT_SET_ENHANCEDFRAMING_T (0x00000001 << 7)
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#define NV_DPCD_TRAINING_PATTERN_SET (0x00000102)
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#define NV_DPCD_TRAINING_PATTERN_SET_TPS_MASK 0x3
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#define NV_DPCD_TRAINING_PATTERN_SET_TPS_NONE (0x00000000)
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#define NV_DPCD_TRAINING_PATTERN_SET_TPS_TP1 (0x00000001)
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#define NV_DPCD_TRAINING_PATTERN_SET_TPS_TP2 (0x00000002)
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#define NV_DPCD_TRAINING_PATTERN_SET_TPS_TP3 (0x00000003)
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#define NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_F (0x00000000 << 5)
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#define NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_T (0x00000001 << 5)
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#define NV_DPCD_TRAINING_LANE0_SET (0x00000103)
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#define NV_DPCD_TRAINING_LANE1_SET (0x00000104)
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#define NV_DPCD_TRAINING_LANE2_SET (0x00000105)
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#define NV_DPCD_TRAINING_LANE3_SET (0x00000106)
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#define NV_DPCD_TRAINING_LANEX_SET_DC_SHIFT 0
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#define NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_T (0x00000001 << 2)
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#define NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_F (0x00000000 << 2)
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#define NV_DPCD_TRAINING_LANEX_SET_PE_SHIFT 3
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#define NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_T (0x00000001 << 5)
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#define NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_F (0x00000000 << 5)
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#define NV_DPCD_DOWNSPREAD_CTRL (0x00000107)
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#define NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP_NONE (0x00000000 << 4)
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#define NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP_LT_0_5 (0x00000001 << 4)
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#define NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET (0x00000108)
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#define NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET_ANSI_8B10B 1
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#define NV_DPCD_EDP_CONFIG_SET (0x0000010A)
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#define NV_DPCD_EDP_CONFIG_SET_ASC_RESET_DISABLE (0x00000000)
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#define NV_DPCD_EDP_CONFIG_SET_ASC_RESET_ENABLE (0x00000001)
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#define NV_DPCD_EDP_CONFIG_SET_FRAMING_CHANGE_DISABLE (0x00000000 << 1)
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#define NV_DPCD_EDP_CONFIG_SET_FRAMING_CHANGE_ENABLE (0x00000001 << 1)
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#define NV_DPCD_TRAINING_LANE0_1_SET2 (0x0000010F)
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#define NV_DPCD_TRAINING_LANE2_3_SET2 (0x00000110)
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#define NV_DPCD_LANEX_SET2_PC2_SHIFT 0
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#define NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_T (0x00000001 << 2)
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#define NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_F (0x00000000 << 2)
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#define NV_DPCD_LANEXPLUS1_SET2_PC2_SHIFT 4
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#define NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_T (0x00000001 << 6)
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#define NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_F (0x00000000 << 6)
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#define NV_DPCD_SINK_COUNT (0x00000200)
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#define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR (0x00000201)
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#define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_AUTO_TEST_NO (0x00000000 << 1)
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#define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_AUTO_TEST_YES (0x00000001 << 1)
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#define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_CP_NO (0x00000000 << 2)
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#define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_CP_YES (0x00000001 << 2)
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#define NV_DPCD_LANE0_1_STATUS (0x00000202)
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#define NV_DPCD_LANE2_3_STATUS (0x00000203)
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#define NV_DPCD_STATUS_LANEX_CR_DONE_SHIFT 0
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#define NV_DPCD_STATUS_LANEX_CR_DONE_NO (0x00000000)
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#define NV_DPCD_STATUS_LANEX_CR_DONE_YES (0x00000001)
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#define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_SHIFT 1
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#define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_NO (0x00000000 << 1)
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#define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_YES (0x00000001 << 1)
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#define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_SHFIT 2
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#define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_NO (0x00000000 << 2)
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#define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_YES (0x00000001 << 2)
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#define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_SHIFT 4
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#define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_NO (0x00000000 << 4)
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#define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES (0x00000001 << 4)
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#define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_SHIFT 5
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#define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_NO (0x00000000 << 5)
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#define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_YES (0x00000001 << 5)
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#define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_SHIFT 6
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#define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_NO (0x00000000 << 6)
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#define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_YES (0x00000001 << 6)
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#define NV_DPCD_LANE_ALIGN_STATUS_UPDATED (0x00000204)
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#define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_DONE_NO (0x00000000)
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#define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_DONE_YES (0x00000001)
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#define NV_DPCD_SINK_STATUS (0x00000205)
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#define NV_DPCD_SINK_STATUS_PORT0_IN_SYNC (0x1 << 0)
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#define NV_DPCD_LANE0_1_ADJUST_REQ (0x00000206)
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#define NV_DPCD_LANE2_3_ADJUST_REQ (0x00000207)
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#define NV_DPCD_ADJUST_REQ_LANEX_DC_SHIFT 0
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#define NV_DPCD_ADJUST_REQ_LANEX_DC_MASK 0x3
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#define NV_DPCD_ADJUST_REQ_LANEX_PE_SHIFT 2
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#define NV_DPCD_ADJUST_REQ_LANEX_PE_MASK (0x3 << 2)
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#define NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_SHIFT 4
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#define NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_MASK (0x3 << 4)
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#define NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_SHIFT 6
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#define NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_MASK (0x3 << 6)
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#define NV_DPCD_ADJUST_REQ_POST_CURSOR2 (0x0000020C)
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#define NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_MASK 0x3
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#define NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_SHIFT(i) (i*2)
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#define NV_DPCD_TEST_REQUEST (0x00000218)
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#define NV_DPCD_SOURCE_IEEE_OUI (0x00000300)
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#define NV_DPCD_SINK_IEEE_OUI (0x00000400)
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#define NV_DPCD_BRANCH_IEEE_OUI (0x00000500)
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#define NV_DPCD_SET_POWER (0x00000600)
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#define NV_DPCD_SET_POWER_VAL_RESERVED (0x00000000)
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#define NV_DPCD_SET_POWER_VAL_D0_NORMAL (0x00000001)
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#define NV_DPCD_SET_POWER_VAL_D3_PWRDWN (0x00000002)
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#define NV_DPCD_HDCP_BKSV_OFFSET (0x00068000)
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#define NV_DPCD_HDCP_RPRIME_OFFSET (0x00068005)
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#define NV_DPCD_HDCP_AKSV_OFFSET (0x00068007)
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#define NV_DPCD_HDCP_AN_OFFSET (0x0006800C)
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#define NV_DPCD_HDCP_VPRIME_OFFSET (0x00068014)
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#define NV_DPCD_HDCP_BCAPS_OFFSET (0x00068028)
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#define NV_DPCD_HDCP_BSTATUS_OFFSET (0x00068029)
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#define NV_DPCD_HDCP_BINFO_OFFSET (0x0006802A)
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#define NV_DPCD_HDCP_KSV_FIFO_OFFSET (0x0006802C)
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#define NV_DPCD_HDCP_AINFO_OFFSET (0x0006803B)
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static __maybe_unused
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void tegra_dp_aux_pad_on_off(struct tegra_dc *dc, bool on)
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{
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struct clk *clk;
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struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(dc);
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clk = clk_get_sys(NULL, "dpaux");
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if (IS_ERR_OR_NULL(clk)) {
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pr_err("%s: get dpaux clock failed.\n", __func__);
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return;
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}
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clk_prepare_enable(clk);
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tegra_dc_io_start(dc);
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writel((on ? DPAUX_HYBRID_SPARE_PAD_PWR_POWERUP :
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DPAUX_HYBRID_SPARE_PAD_PWR_POWERDOWN),
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dp->aux_base + DPAUX_HYBRID_SPARE * 4);
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tegra_dc_io_end(dc);
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clk_disable_unprepare(clk);
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}
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#endif
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