157 lines
3.8 KiB
C
157 lines
3.8 KiB
C
/*
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* Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/string.h>
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#include <linux/tegra-soc.h>
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/* register definition */
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#define KFUSE_STATE 0x80
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#define KFUSE_STATE_DONE (1u << 16)
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#define KFUSE_STATE_CRCPASS (1u << 17)
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#define KFUSE_KEYADDR 0x88
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#define KFUSE_KEYADDR_AUTOINC (1u << 16)
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#define KFUSE_KEYS 0x8c
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struct tegra_kfuse_info {
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struct platform_device *pdev;
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void __iomem *base;
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struct clk *clk;
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};
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static struct tegra_kfuse_info *kfuse_info;
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static inline u32 tegra_kfuse_readl(unsigned long offset)
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{
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return readl_relaxed(kfuse_info->base + offset);
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}
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static inline void tegra_kfuse_writel(u32 value, unsigned long offset)
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{
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writel_relaxed(value, kfuse_info->base + offset);
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}
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static int tegra_kfuse_wait_for_done(void)
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{
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u32 reg;
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int retries = 50;
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do {
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reg = tegra_kfuse_readl(KFUSE_STATE);
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if (reg & KFUSE_STATE_DONE)
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return 0;
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usleep_range(10000, 11000);
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} while (--retries);
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return -ETIMEDOUT;
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}
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/* read up to TEGRA_KFUSE_DATA_SZ bytes into dest.
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* always starts at the first kfuse.
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*/
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int tegra_kfuse_read(void *dest, size_t len)
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{
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int err;
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u32 v;
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unsigned cnt;
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if (len > TEGRA_KFUSE_DATA_SZ)
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return -EINVAL;
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err = clk_prepare_enable(kfuse_info->clk);
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if (err)
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return err;
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tegra_kfuse_writel(KFUSE_KEYADDR_AUTOINC, KFUSE_KEYADDR);
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err = tegra_kfuse_wait_for_done();
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if (err) {
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dev_err(&kfuse_info->pdev->dev, "Read timeout");
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clk_disable_unprepare(kfuse_info->clk);
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return err;
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}
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if ((tegra_kfuse_readl(KFUSE_STATE) & KFUSE_STATE_CRCPASS) == 0) {
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dev_err(&kfuse_info->pdev->dev, "CRC failed\n");
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clk_disable_unprepare(kfuse_info->clk);
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return -EIO;
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}
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for (cnt = 0; cnt < len; cnt += 4) {
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v = tegra_kfuse_readl(KFUSE_KEYS);
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memcpy(dest + cnt, &v, sizeof(v));
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}
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clk_disable_unprepare(kfuse_info->clk);
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return 0;
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}
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EXPORT_SYMBOL_GPL(tegra_kfuse_read);
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static int tegra_kfuse_probe(struct platform_device *pdev)
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{
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struct clk *fuse_clk;
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struct resource *res;
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int err = 0;
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kfuse_info = devm_kzalloc(&pdev->dev,
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sizeof(struct tegra_kfuse_info), GFP_KERNEL);
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if (!kfuse_info)
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return -ENOMEM;
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fuse_clk = devm_clk_get(&pdev->dev, "kfuse");
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if (IS_ERR(fuse_clk)) {
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dev_err(&pdev->dev, "Could not obtain clk");
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return PTR_ERR(fuse_clk);
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}
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kfuse_info->clk = fuse_clk;
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kfuse_info->pdev = pdev;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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kfuse_info->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(kfuse_info->base)) {
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dev_err(&pdev->dev, "Could not obtain base address");
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return PTR_ERR(kfuse_info->base);
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}
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return err;
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}
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static const struct of_device_id tegra_kfuse_of_match[] = {
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{ .compatible = "nvidia,tegra-kfuse" },
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{},
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};
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static struct platform_driver tegra_kfuse_driver = {
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.probe = tegra_kfuse_probe,
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.driver = {
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.name = "tegra_kfuse",
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.owner = THIS_MODULE,
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.of_match_table = tegra_kfuse_of_match,
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}
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};
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module_platform_driver(tegra_kfuse_driver);
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("Tegra KFuse driver for accessing HDCP key stores");
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