491 lines
10 KiB
C
491 lines
10 KiB
C
/*
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* Copyright (C) 2000-2007, Axis Communications AB.
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*/
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/mm.h>
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#include <linux/smp.h>
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#include <linux/errno.h>
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#include <linux/ptrace.h>
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#include <linux/user.h>
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#include <linux/signal.h>
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#include <linux/security.h>
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#include <asm/uaccess.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/processor.h>
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#include <arch/hwregs/supp_reg.h>
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/*
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* Determines which bits in CCS the user has access to.
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* 1 = access, 0 = no access.
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*/
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#define CCS_MASK 0x00087c00 /* SXNZVC */
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#define SBIT_USER (1 << (S_CCS_BITNR + CCS_SHIFT))
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static int put_debugreg(long pid, unsigned int regno, long data);
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static long get_debugreg(long pid, unsigned int regno);
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static unsigned long get_pseudo_pc(struct task_struct *child);
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void deconfigure_bp(long pid);
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extern unsigned long cris_signal_return_page;
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/*
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* Get contents of register REGNO in task TASK.
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*/
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long get_reg(struct task_struct *task, unsigned int regno)
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{
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/* USP is a special case, it's not in the pt_regs struct but
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* in the tasks thread struct
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*/
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unsigned long ret;
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if (regno <= PT_EDA)
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ret = ((unsigned long *)task_pt_regs(task))[regno];
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else if (regno == PT_USP)
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ret = task->thread.usp;
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else if (regno == PT_PPC)
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ret = get_pseudo_pc(task);
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else if (regno <= PT_MAX)
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ret = get_debugreg(task->pid, regno);
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else
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ret = 0;
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return ret;
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}
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/*
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* Write contents of register REGNO in task TASK.
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*/
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int put_reg(struct task_struct *task, unsigned int regno, unsigned long data)
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{
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if (regno <= PT_EDA)
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((unsigned long *)task_pt_regs(task))[regno] = data;
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else if (regno == PT_USP)
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task->thread.usp = data;
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else if (regno == PT_PPC) {
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/* Write pseudo-PC to ERP only if changed. */
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if (data != get_pseudo_pc(task))
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task_pt_regs(task)->erp = data;
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} else if (regno <= PT_MAX)
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return put_debugreg(task->pid, regno, data);
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else
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return -1;
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return 0;
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}
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void user_enable_single_step(struct task_struct *child)
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{
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unsigned long tmp;
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/*
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* Set up SPC if not set already (in which case we have no other
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* choice but to trust it).
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*/
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if (!get_reg(child, PT_SPC)) {
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/* In case we're stopped in a delay slot. */
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tmp = get_reg(child, PT_ERP) & ~1;
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put_reg(child, PT_SPC, tmp);
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}
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tmp = get_reg(child, PT_CCS) | SBIT_USER;
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put_reg(child, PT_CCS, tmp);
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}
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void user_disable_single_step(struct task_struct *child)
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{
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put_reg(child, PT_SPC, 0);
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if (!get_debugreg(child->pid, PT_BP_CTRL)) {
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unsigned long tmp;
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/* If no h/w bp configured, disable S bit. */
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tmp = get_reg(child, PT_CCS) & ~SBIT_USER;
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put_reg(child, PT_CCS, tmp);
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}
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}
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/*
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* Called by kernel/ptrace.c when detaching.
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*
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* Make sure the single step bit is not set.
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*/
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void
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ptrace_disable(struct task_struct *child)
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{
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/* Deconfigure SPC and S-bit. */
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user_disable_single_step(child);
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put_reg(child, PT_SPC, 0);
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/* Deconfigure any watchpoints associated with the child. */
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deconfigure_bp(child->pid);
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}
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long arch_ptrace(struct task_struct *child, long request,
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unsigned long addr, unsigned long data)
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{
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int ret;
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unsigned int regno = addr >> 2;
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unsigned long __user *datap = (unsigned long __user *)data;
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switch (request) {
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/* Read word at location address. */
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case PTRACE_PEEKTEXT:
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case PTRACE_PEEKDATA: {
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unsigned long tmp;
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int copied;
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ret = -EIO;
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/* The signal trampoline page is outside the normal user-addressable
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* space but still accessible. This is hack to make it possible to
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* access the signal handler code in GDB.
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*/
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if ((addr & PAGE_MASK) == cris_signal_return_page) {
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/* The trampoline page is globally mapped, no page table to traverse.*/
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tmp = *(unsigned long*)addr;
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} else {
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copied = access_process_vm(child, addr, &tmp, sizeof(tmp), 0);
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if (copied != sizeof(tmp))
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break;
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}
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ret = put_user(tmp,datap);
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break;
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}
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/* Read the word at location address in the USER area. */
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case PTRACE_PEEKUSR: {
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unsigned long tmp;
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ret = -EIO;
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if ((addr & 3) || regno > PT_MAX)
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break;
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tmp = get_reg(child, regno);
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ret = put_user(tmp, datap);
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break;
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}
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/* Write the word at location address. */
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case PTRACE_POKETEXT:
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case PTRACE_POKEDATA:
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ret = generic_ptrace_pokedata(child, addr, data);
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break;
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/* Write the word at location address in the USER area. */
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case PTRACE_POKEUSR:
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ret = -EIO;
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if ((addr & 3) || regno > PT_MAX)
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break;
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if (regno == PT_CCS) {
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/* don't allow the tracing process to change stuff like
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* interrupt enable, kernel/user bit, dma enables etc.
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*/
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data &= CCS_MASK;
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data |= get_reg(child, PT_CCS) & ~CCS_MASK;
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}
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if (put_reg(child, regno, data))
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break;
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ret = 0;
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break;
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/* Get all GP registers from the child. */
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case PTRACE_GETREGS: {
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int i;
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unsigned long tmp;
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for (i = 0; i <= PT_MAX; i++) {
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tmp = get_reg(child, i);
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if (put_user(tmp, datap)) {
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ret = -EFAULT;
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goto out_tsk;
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}
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datap++;
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}
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ret = 0;
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break;
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}
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/* Set all GP registers in the child. */
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case PTRACE_SETREGS: {
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int i;
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unsigned long tmp;
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for (i = 0; i <= PT_MAX; i++) {
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if (get_user(tmp, datap)) {
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ret = -EFAULT;
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goto out_tsk;
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}
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if (i == PT_CCS) {
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tmp &= CCS_MASK;
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tmp |= get_reg(child, PT_CCS) & ~CCS_MASK;
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}
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put_reg(child, i, tmp);
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datap++;
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}
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ret = 0;
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break;
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}
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default:
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ret = ptrace_request(child, request, addr, data);
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break;
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}
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out_tsk:
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return ret;
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}
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void do_syscall_trace(void)
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{
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if (!test_thread_flag(TIF_SYSCALL_TRACE))
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return;
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if (!(current->ptrace & PT_PTRACED))
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return;
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/* the 0x80 provides a way for the tracing parent to distinguish
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between a syscall stop and SIGTRAP delivery */
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ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD)
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? 0x80 : 0));
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/*
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* This isn't the same as continuing with a signal, but it will do for
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* normal use.
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*/
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if (current->exit_code) {
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send_sig(current->exit_code, current, 1);
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current->exit_code = 0;
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}
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}
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/* Returns the size of an instruction that has a delay slot. */
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static int insn_size(struct task_struct *child, unsigned long pc)
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{
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unsigned long opcode;
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int copied;
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int opsize = 0;
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/* Read the opcode at pc (do what PTRACE_PEEKTEXT would do). */
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copied = access_process_vm(child, pc, &opcode, sizeof(opcode), 0);
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if (copied != sizeof(opcode))
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return 0;
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switch ((opcode & 0x0f00) >> 8) {
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case 0x0:
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case 0x9:
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case 0xb:
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opsize = 2;
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break;
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case 0xe:
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case 0xf:
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opsize = 6;
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break;
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case 0xd:
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/* Could be 4 or 6; check more bits. */
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if ((opcode & 0xff) == 0xff)
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opsize = 4;
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else
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opsize = 6;
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break;
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default:
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panic("ERROR: Couldn't find size of opcode 0x%lx at 0x%lx\n",
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opcode, pc);
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}
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return opsize;
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}
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static unsigned long get_pseudo_pc(struct task_struct *child)
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{
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/* Default value for PC is ERP. */
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unsigned long pc = get_reg(child, PT_ERP);
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if (pc & 0x1) {
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unsigned long spc = get_reg(child, PT_SPC);
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/* Delay slot bit set. Report as stopped on proper
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instruction. */
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if (spc) {
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/* Rely on SPC if set. FIXME: We might want to check
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that EXS indicates we stopped due to a single-step
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exception. */
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pc = spc;
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} else {
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/* Calculate the PC from the size of the instruction
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that the delay slot we're in belongs to. */
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pc += insn_size(child, pc & ~1) - 1;
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}
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}
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return pc;
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}
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static long bp_owner = 0;
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/* Reachable from exit_thread in signal.c, so not static. */
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void deconfigure_bp(long pid)
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{
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int bp;
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/* Only deconfigure if the pid is the owner. */
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if (bp_owner != pid)
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return;
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for (bp = 0; bp < 6; bp++) {
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unsigned long tmp;
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/* Deconfigure start and end address (also gets rid of ownership). */
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put_debugreg(pid, PT_BP + 3 + (bp * 2), 0);
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put_debugreg(pid, PT_BP + 4 + (bp * 2), 0);
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/* Deconfigure relevant bits in control register. */
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tmp = get_debugreg(pid, PT_BP_CTRL) & ~(3 << (2 + (bp * 4)));
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put_debugreg(pid, PT_BP_CTRL, tmp);
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}
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/* No owner now. */
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bp_owner = 0;
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}
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static int put_debugreg(long pid, unsigned int regno, long data)
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{
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int ret = 0;
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register int old_srs;
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#ifdef CONFIG_ETRAX_KGDB
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/* Ignore write, but pretend it was ok if value is 0
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(we don't want POKEUSR/SETREGS failing unnessecarily). */
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return (data == 0) ? ret : -1;
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#endif
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/* Simple owner management. */
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if (!bp_owner)
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bp_owner = pid;
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else if (bp_owner != pid) {
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/* Ignore write, but pretend it was ok if value is 0
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(we don't want POKEUSR/SETREGS failing unnessecarily). */
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return (data == 0) ? ret : -1;
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}
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/* Remember old SRS. */
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SPEC_REG_RD(SPEC_REG_SRS, old_srs);
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/* Switch to BP bank. */
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SUPP_BANK_SEL(BANK_BP);
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switch (regno - PT_BP) {
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case 0:
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SUPP_REG_WR(0, data); break;
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case 1:
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case 2:
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if (data)
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ret = -1;
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break;
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case 3:
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SUPP_REG_WR(3, data); break;
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case 4:
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SUPP_REG_WR(4, data); break;
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case 5:
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SUPP_REG_WR(5, data); break;
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case 6:
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SUPP_REG_WR(6, data); break;
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case 7:
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SUPP_REG_WR(7, data); break;
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case 8:
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SUPP_REG_WR(8, data); break;
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case 9:
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SUPP_REG_WR(9, data); break;
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case 10:
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SUPP_REG_WR(10, data); break;
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case 11:
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SUPP_REG_WR(11, data); break;
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case 12:
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SUPP_REG_WR(12, data); break;
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case 13:
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SUPP_REG_WR(13, data); break;
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case 14:
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SUPP_REG_WR(14, data); break;
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default:
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ret = -1;
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break;
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}
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/* Restore SRS. */
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SPEC_REG_WR(SPEC_REG_SRS, old_srs);
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/* Just for show. */
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NOP();
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NOP();
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NOP();
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return ret;
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}
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static long get_debugreg(long pid, unsigned int regno)
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{
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register int old_srs;
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register long data;
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if (pid != bp_owner) {
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return 0;
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}
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/* Remember old SRS. */
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SPEC_REG_RD(SPEC_REG_SRS, old_srs);
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/* Switch to BP bank. */
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SUPP_BANK_SEL(BANK_BP);
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switch (regno - PT_BP) {
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case 0:
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SUPP_REG_RD(0, data); break;
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case 1:
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case 2:
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/* error return value? */
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data = 0;
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break;
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case 3:
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SUPP_REG_RD(3, data); break;
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case 4:
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SUPP_REG_RD(4, data); break;
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case 5:
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SUPP_REG_RD(5, data); break;
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case 6:
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SUPP_REG_RD(6, data); break;
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case 7:
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SUPP_REG_RD(7, data); break;
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case 8:
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SUPP_REG_RD(8, data); break;
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case 9:
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SUPP_REG_RD(9, data); break;
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case 10:
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SUPP_REG_RD(10, data); break;
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case 11:
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SUPP_REG_RD(11, data); break;
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case 12:
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SUPP_REG_RD(12, data); break;
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case 13:
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SUPP_REG_RD(13, data); break;
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case 14:
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SUPP_REG_RD(14, data); break;
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default:
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/* error return value? */
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data = 0;
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}
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/* Restore SRS. */
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SPEC_REG_WR(SPEC_REG_SRS, old_srs);
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/* Just for show. */
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NOP();
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NOP();
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NOP();
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return data;
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}
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