150 lines
4.1 KiB
Plaintext
150 lines
4.1 KiB
Plaintext
config ARCH_TEGRA
|
|
bool "NVIDIA Tegra" if ARCH_MULTI_V7
|
|
select ARCH_HAS_CPUFREQ
|
|
select ARCH_REQUIRE_GPIOLIB
|
|
select CLKDEV_LOOKUP
|
|
select CLKSRC_MMIO
|
|
select CLKSRC_OF
|
|
select COMMON_CLK
|
|
select GENERIC_CLOCKEVENTS
|
|
select HAVE_ARM_SCU if SMP
|
|
select HAVE_ARM_TWD if LOCAL_TIMERS
|
|
select HAVE_CLK
|
|
select HAVE_SMP
|
|
select MIGHT_HAVE_CACHE_L2X0
|
|
select SOC_BUS
|
|
select SPARSE_IRQ
|
|
select USE_OF
|
|
help
|
|
This enables support for NVIDIA Tegra based systems.
|
|
|
|
menu "NVIDIA Tegra options"
|
|
depends on ARCH_TEGRA
|
|
|
|
config ARCH_TEGRA_2x_SOC
|
|
bool "Enable support for Tegra20 family"
|
|
select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
|
|
select ARM_ERRATA_720789
|
|
select ARM_ERRATA_754327 if SMP
|
|
select ARM_ERRATA_764369 if SMP
|
|
select ARM_GIC
|
|
select CPU_V7
|
|
select PINCTRL
|
|
select PINCTRL_TEGRA20
|
|
select PL310_ERRATA_727915 if CACHE_L2X0
|
|
select PL310_ERRATA_769419 if CACHE_L2X0
|
|
select USB_ULPI if USB_PHY
|
|
select USB_ULPI_VIEWPORT if USB_PHY
|
|
help
|
|
Support for NVIDIA Tegra AP20 and T20 processors, based on the
|
|
ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
|
|
|
|
config ARCH_TEGRA_3x_SOC
|
|
bool "Enable support for Tegra30 family"
|
|
select ARM_ERRATA_754322
|
|
select ARM_ERRATA_764369 if SMP
|
|
select ARM_GIC
|
|
select CPU_V7
|
|
select PINCTRL
|
|
select PINCTRL_TEGRA30
|
|
select PL310_ERRATA_769419 if CACHE_L2X0
|
|
select USB_ULPI if USB_PHY
|
|
select USB_ULPI_VIEWPORT if USB_PHY
|
|
help
|
|
Support for NVIDIA Tegra T30 processor family, based on the
|
|
ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
|
|
|
|
config ARCH_TEGRA_114_SOC
|
|
bool "Enable support for Tegra114 family"
|
|
select ARM_ARCH_TIMER
|
|
select ARM_ERRATA_798181
|
|
select ARM_GIC
|
|
select ARM_L1_CACHE_SHIFT_6
|
|
select CPU_FREQ_TABLE if CPU_FREQ
|
|
select CPU_V7
|
|
select PINCTRL
|
|
select PINCTRL_TEGRA114
|
|
help
|
|
Support for NVIDIA Tegra T114 processor family, based on the
|
|
ARM CortexA15MP CPU
|
|
|
|
config ARCH_TEGRA_124_SOC
|
|
bool "Enable support for Tegra124 family"
|
|
select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
|
|
select ARM_ARCH_TIMER
|
|
select ARM_GIC
|
|
select ARM_L1_CACHE_SHIFT_6
|
|
select CPU_V7
|
|
select PINCTRL
|
|
select PINCTRL_TEGRA124
|
|
help
|
|
Support for NVIDIA Tegra T124 processor family, based on the
|
|
ARM CortexA15MP CPU
|
|
|
|
config TEGRA_PCI
|
|
bool "PCI Express support"
|
|
depends on ARCH_TEGRA_2x_SOC
|
|
select PCI
|
|
|
|
config TEGRA_AHB
|
|
bool "Enable AHB driver for NVIDIA Tegra SoCs"
|
|
default y
|
|
help
|
|
Adds AHB configuration functionality for NVIDIA Tegra SoCs,
|
|
which controls AHB bus master arbitration and some
|
|
performance parameters(priority, prefech size).
|
|
|
|
config TEGRA_DVFS
|
|
bool "Tegra DVFS support"
|
|
help
|
|
This adds Tegra DVFS support. There could be several power
|
|
rails involved and there might be rails dependency based
|
|
on different SoCs, this config enable the generic DVFS
|
|
library needed by each SoCs DVFS files.
|
|
|
|
If in doubt, say N.
|
|
|
|
config TEGRA_124_DVFS
|
|
bool "Tegra124 DVFS support"
|
|
depends on ARCH_TEGRA_124_SOC
|
|
select TEGRA_DVFS
|
|
help
|
|
This enable Tegra124 DVFS functionality, it implements SoC
|
|
specific initialization code to be invoked by probe function
|
|
defined in generic Tegra DVFS driver, so while enabled it
|
|
needs the config TEGRA_DVFS to be enabled as well.
|
|
|
|
config TEGRA_EMC_SCALING_ENABLE
|
|
bool "Enable scaling the memory frequency"
|
|
|
|
config EDP_MANAGEMENT
|
|
bool "EDP management"
|
|
help
|
|
Power “sources” like batteries and regulators have limits
|
|
on how much current they can supply, the maximum current
|
|
the power source can supply is its “EDP limit”.
|
|
This is the NVIDIA technique for managing the peak current
|
|
consumption of the power rail.
|
|
EDP management manages the components to avoid exceeding
|
|
the design limits, it limits peak current consumption
|
|
while maximizing performance.
|
|
|
|
if EDP_MANAGEMENT
|
|
config TEGRA_CPU_EDP_LIMITS
|
|
bool "VDD_CPU EDP"
|
|
depends on ARCH_TEGRA
|
|
depends on CPU_FREQ && THERMAL
|
|
default n
|
|
help
|
|
Enforce electrical design limits on CPU rail.
|
|
VDD_CPU EDP prevents the CPU from drawing more current than
|
|
its voltage regulator can supply.
|
|
Limit maximum CPU frequency based on temperature and number
|
|
of on-line CPUs to keep CPU rail current within power supply
|
|
capabilities.
|
|
If in doubt, say "Y".
|
|
|
|
endif
|
|
|
|
endmenu
|