113 lines
4.4 KiB
Plaintext
113 lines
4.4 KiB
Plaintext
Tegra SOC XUSB PHY
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The device node for the Tegra SOC XUSB PHY:
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Required properties:
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- compatible: Should be "nvidia,tegra114-xusb-phy" or
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"nvidia,tegra124-xusb-phy".
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- reg: Address and length of the register sets. There should be two
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entries in the following order: XUSB_PADCTL registers and USB2.0 PHY
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registers.
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- interrupts: PADCTL interrupt, used for wake from runtime and LP0 suspend.
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- clocks: Handles to XUSB SS, SS source, PLL_U_480M, CLK_M, and pad clocks.
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- clock-names: Should be "xusb_ss", "xusb_ss_src", "pll_u_480M", "clk_m",
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and "pad_clk" respectively.
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- nvidia,pmc: Handle to the PMC syscon node.
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- nvidia,clkrst: Handle to the clock-reset module syscon node.
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- nvidia,ss-pads: Bitmap of enabled SuperSpeed pads:
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bit 0 - SuperSpeed port 0
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bit 1 - SuperSpeed port 1
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- nvidia,utmi-pads: Bitmap of enabled USB2.0 UTMI pads:
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bit 0 - UTMI port 0
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bit 1 - UTMI port 1
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bit 2 - UTMI port 2
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- nvidia,hsic-pads: Bitmap of enabled USB2.0 HSIC pads:
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bit 0 - HSIC port 0
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bit 1 - HSIC port 1
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- nvidia,hsic{0,1}-config: byte array with 9 elements specifiying the
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configuration for the corresponding HISC port:
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byte 0 - rx_strobe_trim
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byte 1 - rx_data_trim
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byte 2 - tx_rtune_n
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byte 3 - tx_rtune_p
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byte 4 - tx_slew_n
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byte 5 - tx_slew_p
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byte 6 - auto_term_en
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byte 7 - strb_trim_val
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byte 8 - pretend_connect
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Only required for enabled HISC ports.
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- nvidia,ss-portmap: Mapping from SS ports to their corresponding USB2.0 port:
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bits 3-0 - SuperSpeed port 0
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bits 7-4 - SuperSpeed port 1
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Both fields have valid values from 0 to 2 (USB2.0 ports 0, 1, 2).
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- nvidia,lane-owner: Program ownership of lanes owned by USB3.0:
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bit 0 - set when super-speed port 1 uses SATA lane. Valid for Tegra124.
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= 0 (SATA lane owner = SATA)
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= 1 (SATA lane owner = USB3_SS port1)
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bit 1 - set when super-speed port 0 uses PCIe lane 0 (always).
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= 0 (PCIe lane0 owner = PCIe),
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= 1 (PCIe lane0 owner = USB3_SS port0)
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bit 2 - set when super-speed port 1 uses PCIe lane 1.
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= 0 (PCIe lane1 owner = PCIe),
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= 1 (PCIe lane1 owner = USB3_SS port1)
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- vbus{1,2,3}-supply: VBUS regulator for the corresponding UTMI pad.
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Only required when the respective UTMI pad is enabled.
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- vddio-hsic-supply: HSIC supply regulator. Only required when HSIC ports
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are enabled.
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Optional properties:
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- nvidia,xusb-hs-xcvr-setup-offset: used for high-speed transceiver setup
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and for data eye swing.
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bit 7-0: for PAD0 (port0)
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bit 15-8: for PAD1 (port1)
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bit 23-16: for PAD2 (port2)
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USB parameter HS_CURR_LEVEL is calibrated and fused. Software reads
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the fuse value and programs it to the correct level.
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Actual product may have additional losses on the PCB (connectors).
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This reduces the actual signal at the USB connector.
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Software has the option of adding an offset to the FUSE value before
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it is programmed to register.
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Programmed value = Fuse value + Offset
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This corrects any losses.
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The objective is to get the data eye swing as close as possible to 400mv
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without falling below the mark under typical operating conditions.
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Offset (nvidia,xusb-hs-xcvr-setup-offset) is design dependant
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(PCB type, length of PCB, switches used, etc).
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If "nvidia,xusb-hs-xcvr-setup-offset" is not defined or has
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value 0 for the pad, then
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Programmed value = Fuse value
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usb@70090000 {
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...
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nvidia,xusb-phy = <&xusb_phy>;
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...
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};
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xusb_phy: phy@7009f000 {
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compatible = "nvidia,tegra124-xusb-phy";
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reg = <0x0 0x7009f000 0x1000>,
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<0x0 0x7000e400 0x800>;
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_XUSB_SS>,
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<&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
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<&tegra_car TEGRA124_CLK_PLL_U_480M>,
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<&tegra_car TEGRA124_CLK_CLK_M>,
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<&tegra_car TEGRA124_CLK_USBD>;
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clock-names = "xusb_ss", "xusb_ss_src", "pll_u_480M",
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"clk_m", "pad_clk";
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nvidia,pmc = <&pmc>;
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nvidia,clkrst = <&tegra_car>;
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nvidia,ss-pads = <0x3>; /* SSP0, SSP1 */
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nvidia,hsic-pads = <0x0>;
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nvidia,utmi-pads = <0x7>; /* USB2P0, USB2P1, USB2P2 */
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nvidia,ss-portmap = <0x20>; /* SSP0->USB2P0, SSP1->USB2P2 */
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nvidia,lane-owner = <0x6>; /* USB3P0 USB3P1 */
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vbus1-supply = <&usb1_vbus_reg>;
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vbus2-supply = <&run_cam_2v8>;
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vbus3-supply = <&usb3_vbus_reg>;
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vddio-hsic-supply = <&gen_avdd_1v2>;
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nvidia,xusb-hs-xcvr-setup-offset = <0x020004>;
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};
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