48 lines
1.8 KiB
Plaintext
48 lines
1.8 KiB
Plaintext
NVIDIA Tegra 30 IOMMU H/W, SMMU (System Memory Management Unit)
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Required properties in the IOMMU node:
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- compatible : "nvidia,tegra124-smmu", "nvidia,tegra30-smmu"
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- reg : Can contain multiple register banks(address and length) for each
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of the SMMU register blocks.
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- interrupts : Should contain MC General interrupt.
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- nvidia,#asids : # of ASIDs
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- dma-window : IOVA start address and length.
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- nvidia,ahb : phandle to the ahb bus connected to SMMU.
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- iommus: phandle to an iommu device which a device is
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attached to and indicates which swgroups a device belongs to(SWGROUP ID).
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SWGROUP ID is from 0 to 63, and a device can belong to multiple SWGROUPS.
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- #iommu-cells. Should be 2. In client IOMMU specifiers, the two cells
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represent a 64-bit bitmask of SWGROUP IDs under which the device
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initiates transactions. The least significant word is first. See
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<dt-bindings/memory/tegra-swgroup.h> for a list of valid values.
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Required properties in device nodes affected by the IOMMU:
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- iommus: A list of phandle plus specifier pairs for each IOMMU that
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affects master transactions initiated by the device. The number of
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cells in each specifier is defined by the #iommu-cells property in
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the IOMMU node referred to by the phandle. The meaning of the
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specifier cells is defined by the referenced IOMMU's binding.
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Example:
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smmu: iommu {
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compatible = "nvidia,tegra30-smmu";
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reg = <0x7000f010 0x02c
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0x7000f1f0 0x010
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0x7000f228 0x05c>;
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nvidia,#asids = <4>; /* # of ASIDs */
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dma-window = <0 0x40000000>; /* IOVA start & length */
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nvidia,ahb = <&ahb>;
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#iommu-cells = <2>;
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};
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host1x {
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compatible = "nvidia,tegra30-host1x", "simple-bus";
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iommus = <&smmu TEGRA_SWGROUP_CELLS(HC)>;
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....
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gr3d {
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compatible = "nvidia,tegra30-gr3d";
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iommus = <&smmu TEGRA_SWGROUP_CELLS(NV)
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TEGRA_SWGROUP_CELLS(NV2)>;
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....
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};
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