87 lines
3.7 KiB
Plaintext
87 lines
3.7 KiB
Plaintext
DFLL CVB table characterization data in the DFLL DTS file
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Required properties:
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- speedo-id : Note that the properties in this node are applicable for chips
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with this Speedo ID set in the chip's fuses. See also
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the 'process-id' property below.
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- therm-floors : list of two-cell arrays representing the minimum
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voltage required on the DFLL voltage rail when the
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temperature is at or below the given trip point. The
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first of the two cells is the trip point temperature
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in degrees Celsius. The second cell is the minimum
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voltage in millivolts.
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- therm-caps : list of two-cell arrays representing the maximum
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voltage limitted on the DFLL voltage rail when the
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temperature is at or above the trip point. The first
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of the two cells is the trip point temperature in
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degrees Celsius. The sencond cell is the maximum voltage
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in millivolts.
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- cvb-max-millivolts : limit CVB starting voltages to this voltage.
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- cvb-speedo-scale : silicon characterization multiplier, from e-fuses
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- cvb-voltage-scale : CVB voltage scale factor (to microvolts)
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- cvb-voltage-curves : list of four-cell arrays mapping the first cell
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(the DFLL target frequency) to three
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coefficients (the remaining three cells) used
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to compute the starting voltage to program the
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PMIC to. The DFLL should automatically adjust
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the PMIC voltage below this point.
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Optional properties:
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- process-id : If present, indicates that the properties in this node only
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apply to chips with the matching process ID set in the chip's
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fuses. 'speedo-id' must also match the chip fuses.
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The address of the characterization nodes is arbitrary and ignored.
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Example:
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cpu_dfll_cvb_table {
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...
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characterization@1 {
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speedo-id = <1>;
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process-id = <0>;
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therm-floors = < 20 1000>;
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therm-caps = < 62 1230 72 1210 82 1180>;
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cvb-max-millivolts = <1350>;
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cvb-speedo-scale = <100>;
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cvb-voltage-scale = <1000>;
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cvb-voltage-curves = < 306000000 2190643 0xfffdd5e5 3576>,
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< 408000000 2250968 0xfffdcc35 3576>,
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< 510000000 2313333 0xfffdc285 3576>,
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< 612000000 2377738 0xfffdb8d5 3576>,
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< 714000000 2444183 0xfffdaf25 3576>,
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< 816000000 2512669 0xfffda575 3576>,
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< 918000000 2583194 0xfffd9bc5 3576>,
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<1020000000 2655759 0xfffd9215 3576>,
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<1122000000 2730365 0xfffd8865 3576>,
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<1224000000 2807010 0xfffd7eb5 3576>,
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<1326000000 2885696 0xfffd7505 3576>,
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<1428000000 2966422 0xfffd6b55 3576>,
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<1530000000 3049183 0xfffd61af 3576>,
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<1606500000 3112179 0xfffd5a75 3576>,
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<1708500000 3198504 0xfffd50c5 3576>,
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<1810500000 3304747 0xfffd444a 3576>;
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};
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};
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...
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DFLL CVB table data in the DFLL DTS file
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Required properties:
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- #address-cells : Set to 1
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- #size-cells : Set to 0
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Example:
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cpu_dfll_cvb_table {
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#address-cells = <1>;
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#size-cells = <0>;
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characterization@1 {
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...
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};
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};
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